JPH0562386A - Control device of magnetic disk device - Google Patents

Abstract

(57) [Abstract] [Purpose] To shorten the access time when moving a read / write head of a magnetic disk device (hereinafter referred to as FDD) and improve high-speed processing of a computer. An FDD 7 in which a read / write head for reading or writing data from or to a medium is moved by a stepping motor driven by a step pulse signal.
Are controlled by the FDD controller 5. When the step pulse signal is continuously output to the FDD controller 5, a step rate switching circuit 31 that switches the pulse time interval of the step pulse signal is provided, so that the stepping motor has a long pulse interval when starting and a short pulse interval when rotating. To

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for controlling the movement of a read / write head of a magnetic disk device (hereinafter referred to as FDD).

[0002]

2. Description of the Related Art FIGS. 3 to 6 are diagrams showing a conventional FDD control device. FIG. 3 is an overall block diagram, FIG. 4 is a block diagram of an FDD controller, and FIG. 5 is an FDD stepping motor (hereinafter referred to as STM). Block diagram of the control circuit,
FIG. 6 is a timing chart showing the operation of the STM.

In the figure, 1 is a CPU, 2 is a memory, and 3
Is a CPU bus for exchanging data with the CPU 1, the memory 2, and external devices other than the CPU 4, 4 is a CPU interface connected to the CPU bus 3, 5 is an FDD controller connected to the CPU interface 4, and 6 is an FDD controller 5. A connected FDD interface, 7 is an FDD connected to the FDD interface 6.

In FIG. 4, 8 is an FDD controller 5
Status register that outputs the operating state of
Reference numeral 9 is a data register for exchanging data between the FDD controller 5 and the CPU 1 and memory 2, and 10 is an FDD 7
A read / write controller that receives an instruction to perform read / write operation from the CPU 1, 11 is a data separator that converts data read from the FDD 7 into data that can be read by the CPU 1, and 12 is writable by the FDD 7 when writing data to the FDD 7. It is a compensation circuit that converts data.

Reference numeral 13 is a command register for automatically selecting an instruction received from the CPU 1, 14 is a drive interface for exchanging data between the FDD controller 5 and FDD 7, 15 is a step rate timer for selecting the rotation speed of the STM, 17 Is an input port that receives a signal from the FDD 7, and 18 is an output port that sends a signal to the FDD 7.

In FIG. 5, 21 is a step pulse signal output from the FDD interface 6, 22 is also a direction signal, 23 is an input pulse limiting circuit for limiting the input of the step pulse signal 21, and 23a is the output thereof. Step pulse signal, 24 is a pulse train generation circuit, 2
4a is a pulse train signal which is its output, 25 is an STM drive circuit, 25a is STM phase excitation which is its output, and 26 is an ST for driving a read / write head (not shown) of the FDD.
M and 27 are track 0 detection circuits for detecting the reference position of the read / write head, 27a is a track 0 detection signal which is an output thereof, 28 is a track 0 discrimination circuit, and 28a is a track 0 signal which is an output thereof.

The conventional magnetic disk drive controller is constructed as described above, and its operation will be described below. Generally F
The signal handled by the DD7 has a wide range from analog to digital, and the signal level is also very different from that handled by the CPU bus 3. Therefore, the FDD7 is directly processed by the CPU.
It is difficult to connect to the bus 3. Therefore, the CPU
The connection between the bus 3 and the FDD 7 is connected to the CPU bus 3-CPU interface 4-FDD controller 5-FDD interface 6-FDD7 via the interface surrounded by a broken line in FIG.

The CPU interface 4 is a CPU bus 3
CPU 1 and memory 2 and FDD controller 5 via
The conversion of the exchange of data (signal level, signal format, etc.) is performed. The FDD controller 5 is the CPU 1
And the data in the memory 2 are converted so that the FDD 7 can understand them to control the FDD 7. For example, F
In addition to the control of writing and reading of data to the DD 7, the formatting of the medium to the initial state and the control of the mechanical portion of the FDD 7 are also performed. FDD interface 6
Performs logic level conversion with the FDD controller 5 because all signals on the FDD 7 side are negative logic, and logic conversion depending on the difference between the FDD controller 5 and the FDD 7.

Now, when the operator turns on the power, the power is also supplied to the FDD 7, and the FDD 7 is reset to the initial state (detailed description is omitted). When the operator inserts a medium, which is a disk-shaped magnetic body, into the FDD 7, a spindle motor (not shown) rotates to rotate the medium in the circumferential direction. Then, the rotation of the medium becomes steady after a certain period of time, data can be read from and written to the medium, and a standby state waiting for a read / write operation command from the CPU 1 is set.

When performing write control on the FDD 7, the CPU 1 sends a "write command" to the CPU interface 4 via the CPU bus 3. The CPU interface 4 logically converts the “write command” and sends it to the FDD controller 5. Similarly, the “write data” is stored in the memory 2 or the like from the CPU bus 3 and the CPU interface 4.
Is sent to the FDD controller 5 via. The "write command" and the "write data" are converted by the FDD controller 5 so that the FDD 7 can understand them.

The "write command" is input to the read / write controller 10 of the FDD controller 5 via the CPU interface 4, and the command for automatically writing data to the FDD 7 is selected from the command register 13 when the command is executed. In response to this instruction, the status register 8 sends to the CPU 1 via the CPU interface 4 that it is ready to write data. The “write data” is input to the data register 9 via the CPU interface 4.

Upon receiving the "write data", the FDD controller 5 sends the data to the write compensating circuit 12 in order to make the data writable to the FDD 7. The converted "write command" and "write data" are
It is sent to the output port 18 via the drive interface 14 and output to the FDD interface 6. FDD
The “write command” and “write data” logically converted by the interface 6 are sent to the FDD 7 and the FDD 7
Performs an operation of writing data to the medium.

Similarly, when the read control is performed on the FDD 7, the CPU 1 executes the CPU via the CPU bus 3.
A “read command” is sent to the interface 4. The CPU interface 4 logically converts the “read command” and
Send to the DD controller 5. This "read command" is F
It is converted by the DD controller 5 so that the FDD 7 can be understood. The “read command” is input to the read / write controller 10 of the FDD controller 5 via the CPU interface 4, and a command for automatically reading data from the FDD 7 is selected from the command register 13 when the command is executed. In response to this instruction, status register 8
Sends to the CPU 1 via the CPU interface 4 that it is ready to read data.

Further, the "read command" is sent to the output port 18 via the drive interface 14 and the FD
It is output to the D interface 6. The “read command” logically converted by the FDD interface 6 is sent to the FDD 7, and the FDD 7 performs a data read operation from the medium. The "read data" read from the medium is FD
The data is output from D7 via the FDD interface 6 to the input port 17 of the FDD controller 5. The FDD controller 5 sends the “read data” input from the input port 17 to the data separator 11 via the drive interface 14 in order to convert the “read data” into data that can be read by the CPU 1. The converted “read data” is sent to the data register 9, is logically converted by the CPU interface 4, and then is transferred to the CPU via the CPU bus 3.
1 or stored in the memory 2.

When the FDD controller 5 executes the above-mentioned "write command" and "read command", the FDD 7
Signal from the FDD 7 indicating that the FDD 7 is in a command standby state in which read / write operation is possible.
Must be received by the input port 17 of the FDD controller 5 via. Further, the data written on the medium is stored on the concentric circumference of the medium. For example, in the case of a 3.5-inch medium, there are 80 recording positions on the concentric circumference, that is, 80 tracks.

Generally, regarding the track, the outermost circumference of the medium is called "track 0" and the innermost circumference is called "track 79". Therefore, when making the FDD 7 read and write data, it is necessary to specify this track. As a means for moving the read / write head to a track at a specified position on the medium, ST
The M26 is used, and the mechanical portion of the read / write head converts the rotational movement of the STM26 into a linear movement to reach a designated track. Here, it is assumed that the linear movement of one track corresponds to the rotation angle of two steps of the STM 26. The "movement command" will be described below.

Before the CPU 1 sends a "read / write command" to the FDD controller 5, the CPU 1 sends a "move command" to the FDD controller 5 to move the read / write head to a designated track for read / write operation. Generally, the FDD controller 5 stores the current track position of the read / write head, and moves the read / write head by the difference between the track of the "move command" and the current track. If the current track position of the read / write head is unknown, FDD
The controller 5 operates to move the read / write head to the outermost track 0 of the medium, and then sends a command to move to the designated track. Here, the FDD controller 5
Assumes that the track position of the read / write head has been stored in advance, and that track is "track 0". Further, the moving track position of the “moving command” is “track 20”.

The "movement command" output by the CPU 1 is the CP
It is sent to the read / write controller 10 of the FDD controller 5 via the U bus 3. The “designated track 20” of the “move command” is sent to the data register 9 of the FDD controller 5 via the CPU bus 3. "Move command"
The FDD controller 5 that has received the command causes the command register 13 to automatically select an instruction to move the read / write head. The FDD controller 5 has a data register 9
The "designated track 20" received by is compared with the "current track" of the read / write head to obtain the step pulse number and the moving direction required for the read / write head to move to the "designated track 20".

Here, the required number of step pulses is 20.
And the moving direction is the inner circumferential direction of the medium. The step pulse number 20 is output to the output port 18 via the drive interface 14 at the step pulse time interval T1 selected by the step rate timer 15. Similarly, the fact that the movement direction is the inner peripheral direction is output to the output port 18 via the drive interface 14. The step pulse intervals at this time are equal intervals designated in advance, and are generally determined by the specifications of the computer designer, and the FDD 7 matching them is selected and connected to the computer.

The step pulse number 20 and the inner circumferential direction according to the "movement command" and the "designated track 20" are transferred from the output port 18 to the FDD 7 via the FDD interface 6.
It is output as a step pulse signal 21 and a direction signal 22, respectively. By the way, the signals between the FDD interface 6 and the FDD 7, such as the step pulse signal 21, the direction signal 22, the track 0 signal 28a, etc., have a negative logic, and the edge when the step pulse signal 21 is at the “L” level is the step pulse, When the direction signal 22 is at the "L" level, movement to the inner circumferential direction is designated, and when the track 0 signal 28a is at the "L" level, the read / write head is located at "track 0".

The step pulse signal 21 is sent to the input pulse limiting circuit 23 and the track 0 discriminating circuit 28, and the direction signal 22
Are sent to the input pulse limiting circuit 23, the pulse train generating circuit 24 and the track 0 discriminating circuit 28, respectively. Further, since the read / write head is located at "track 0", the track 0 detection circuit 27 outputs the track 0 detection signal 27a to the track 0 discrimination circuit 28 and the track 0 discrimination circuit 2
8 makes a determination in combination with other conditions for "track 0" to be satisfied, and outputs the track 0 signal 28a to the FDD interface. In this case, “track 0” is established before the step pulse signal 21 is input.

The input pulse limiting circuit 23 includes a direction signal 22.
Is at "H" level, that is, in the outer peripheral direction and the track 0 signal
The step pulse input is limited only when 8a is at "L" level, that is, "track 0". In this case, since the direction signal 22 is at the “L” level, the step pulse signal 2
1 is all accepted and internal step pulse signal 23
a is the same as the step pulse signal 21. When the first step pulse signal 21 is input, the track 0 discriminating circuit 28 switches the track 0 signal 28a to the "H" level because the direction signal 22 is at the "L" level and the condition for establishing the track 0 is not satisfied. Further, since the read / write head moves in the inner circumferential direction, the track 0 detection signal 27a also sequentially becomes "H".
It becomes a level.

The pulse train generation circuit 24 is the STM 26 1
Since the track feed corresponds to two steps, the internal pulse is combined to output the pulse train signal 24a to the STM drive circuit 2.
Output to 5. Since the STM26 is a two-phase motor,
There are four types of STM phase excitation, and the movement in the inner circumferential direction is A →
The phase excitation direction is B → C → D → A, and the STM drive circuit 25
Outputs the STM phase excitation 25a. With this, STM26
Moves the read / write head to "specified track 20",
The "movement command" ends. After the "move command" is completed, the CPU
1 executes a "write command" or a "read command".

[0024]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the DD control device, when the read / write head is moved to the designated track, the time interval T1 of the step pulse signal 21 is increased.
Is constant, the access time increases in proportion to the amount of movement of the read / write head from the current track position,
There is a problem in that the waiting time until the next instruction after the "movement instruction" ends becomes long, which hinders the improvement of high-speed processing of the computer.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to shorten the access time with respect to the movement amount of the read / write head and to improve the high-speed processing of the computer. The purpose is to provide.

[0026]

An FDD control device according to the present invention is adapted to shorten a pulse time interval of a step pulse signal when a step pulse signal for driving a read / write head is continuously output. Is.

[0027]

In the present invention, since the pulse time interval of the step pulse signal is shortened, the rotation speed of the STM, that is, the moving speed of the read / write head is increased.

[0028]

1 and 2 are views showing an embodiment of the present invention, FIG. 1 is a block diagram of an FDD controller, and FIG. 2 is a timing chart showing the operation of an STM. Are denoted by the same reference numerals. Note that FIG. 3 and FIG.
Is also shared with this embodiment.

In FIG. 1, reference numeral 31 is a step rate switching circuit for controlling the pulse time interval when a continuous step pulse signal 21 is output, and reference numeral 31a is the output step rate switching signal.

Next, the operation of this embodiment will be described with reference to FIG. However, the description of the same parts as those of the conventional device will be omitted. From the "specified track 20" received by the data register 9 of the FDD controller 5 and the "current track" of the read / write head, the step pulse number 20 required to move the read / write head is calculated.
0 is input to the step rate switching circuit 31. When the number of step pulses becomes 2 or more, the step rate switching circuit 31 switches the step rate switching signal 31a from the third step pulse signal 21 from "H" level to "L" level. The step rate switching signal 31a is reset to "H" level if no step pulse is input for a certain period of time.

The step rate timer 15 to which the step pulse number 20 and the step rate switching signal 31a are input, steps the step pulse time interval T1 when the step rate switching signal 31a is at "H" level, and when the step rate switching signal 31a is at "L" level. Each pulse time interval T2 is selected. At the step pulse time interval T2 selected by the step rate timer 15, it is output to the output port 18 via the drive interface 14, and as described above, the STM.
26 is driven and the read / write head is moved.

By the way, the pulse time interval of the step pulse signal 21 for rotating the STM 26 depends on the torque in the rotating direction of the STM 26. Generally, when driving with continuous pulses, the driving force is most required at the time of startup, and when the rotation starts, inertial force acts in the rotation direction, so it is possible to rotate with a small torque. Become. This steady torque is about half of the starting torque.

These torques are proportional to the product of the time of one phase excitation of the STM phase excitation 25a and the phase current of the STM 26. Therefore, in the conventional device, the pulse time interval T1 of the step pulse signal 21 is changed from the starting torque of the STM 26.
Is obtained and becomes a step pulse signal 21 consisting of continuous step pulses having this time interval T1. Therefore, in the conventional apparatus, since the torque equivalent to the starting torque is generated during the rotation of the STM 26, the read / write head is moved with a torque more than necessary.

However, the step pulse time interval T1 is
It is only necessary when the STM 26 is activated, and in this embodiment, the second pulse time interval of the step pulse signal 21 is the time interval T1, and the third and subsequent time intervals are the time interval T2.
T1> T2, and T2 is half of T1. And
The time interval T1 is set in order to generate the necessary starting torque only when the STM 26 is started, and the time interval T2 is set in order to generate only the steady torque necessary for the rotation while the STM 26 is rotating. Therefore, when the amount of movement of the read / write head is large, the "movement instruction" can be executed with almost half the access time of the conventional device.

[0035]

As described above, according to the present invention, when the step pulse signal for driving the read / write head is continuously output, the pulse time interval of the step pulse signal is shortened. That is, the moving speed of the read / write head is increased, the access time when the read / write head is moved by a large amount can be shortened, and the high-speed processing of the computer can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an FDD controller showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the STM showing the embodiment of the present invention.

FIG. 3 is an overall block diagram showing a conventional FDD control device.

4 is a block diagram of the FDD controller of FIG.

5 is a block diagram of the SDD control circuit of the FDD of FIG.

6 is a timing chart showing the operation of the STM of FIG.

[Explanation of symbols]

 7 magnetic disk device (FDD) 21 step pulse signal 26 stepping motor 31 step rate switching circuit T1, T2 step pulse time interval

Claims (1)

[Claims] 1. A device for moving a read / write head for reading or writing data to and from a disk-shaped medium to a predetermined track position on the medium by a stepping motor driven by the step pulse signal, wherein the step pulse signal is A controller for a magnetic disk drive, comprising a step rate switching circuit for shortening a pulse time interval of the step pulse signal when continuously output.