JPH056997A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor device having a novel structure that can be highly integrated by integrating a level sensor and a timer into an LSI. A first source / drain region is provided on one main surface of a semiconductor substrate, and a first insulating film is provided on at least one main surface of the semiconductor substrate between the first source / drain regions.
A semiconductor region is provided on the first insulating film, a second source / drain region is provided on an upper surface of the semiconductor region, and a second insulating film is provided on at least a main surface of the semiconductor region between the second source / drain regions. And a gate electrode was provided on the second insulating film. Then, by the gate potential applied to the gate electrode,
The substrate current flowing in the semiconductor region, and thus the potential of the substrate in the semiconductor region, is changed to control the current flowing between the first source / drain provided in the lower semiconductor substrate. [Effect] The semiconductor device can be formed with a small occupied area, and the degree of integration can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effective when applied to a semiconductor device, for example, a technique particularly effective when applied to a semiconductor device incorporating a level sensor or a timer.

[0002]

2. Description of the Related Art Conventional semiconductor devices used as level sensors and timers have not been suitable for LSI.

[0003]

Therefore, it is difficult to improve the degree of integration of an LSI incorporating a level sensor or a timer.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a novel structure which can easily be highly integrated even when a level sensor or a timer is incorporated. There is.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a first source region and a first drain region are provided on one main surface of the semiconductor substrate, and a first source region and a first drain region are provided on at least one main surface of the semiconductor substrate between the first source region and the first drain region. A first insulating film, a semiconductor region on the first insulating film, a second source region and a second drain region on the upper surface of the semiconductor region, and at least the second source region and the second drain. A second insulating film was provided on the main surface of the semiconductor region between the regions, and a gate electrode was provided on the second insulating film. Then, the gate potential applied to the gate electrode changes the substrate current flowing in the semiconductor region, and thus the potential of the substrate in the semiconductor region, and between the first source region and the first drain region provided in the lower semiconductor substrate. Control the current flowing.

[0008]

According to the above means, when the gate potential on the semiconductor region formed on the semiconductor substrate becomes a certain value or more,
Since the drain current flows through the transistor formed on the semiconductor substrate, it functions as a level sensor, and further, the response of the drain current to the input of the gate potential has a delay to some extent and thus functions as a timer. Since such a function is realized by the SOI / MIS structure in the present invention, high integration is facilitated even when a level sensor or a timer is incorporated.

[0009]

Embodiments of the semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic structural view of a semiconductor device according to an embodiment. In the semiconductor device of the embodiment, a source / drain region (first source / drain region) 4 and an insulating film (first insulating film) 2 are provided on the upper surface of the semiconductor substrate 1, and the source / drain region 4 is provided between the source / drain region 4. A semiconductor region 3 is provided on the insulating film 2, and a source / drain region (second source / drain region) 7, a gate insulating film (second insulating film) 5, and a gate electrode 6 are provided on the upper surface of the semiconductor region 3. Has a structure. In other words, the semiconductor device of this embodiment has an SOI / MIS (Silicon on Insu)
Later / Metal Insulator Sem
It has an icon structure). The source / drain region 4 includes the source electrode S2 and the drain electrode D.
2 and the source / drain region 7 is the source electrode S
1, connected to the drain electrode D1.

In this semiconductor device, when the gate potential VG applied to the gate electrode 6 is increased, the current ID1 flowing between the source / drain 7 of the SOI / MIS formed in the semiconductor region 3 is increased and the semiconductor region is also increased. Three
An SOI substrate current Isoi flowing inside is generated. This substrate current Isoi is generated by a collision ionization phenomenon that occurs in a high electric field region near the drain, and a certain gate potential V0 (1 V
Value of VG = V1 (about 2V) and has a maximum value with respect to the gate potential of VG = V1 (about 2V).
It will not be observed above about V) (see FIG. 2). Therefore, the SOI substrate potential Vsoi is generated in the semiconductor region 3 with respect to the gate potential VG of V0 or more and V2 or less, and the SOI substrate potential Vsoi when the gate potential VG is input.
Response is as shown in FIGS.

3 to 6, the gate potential VG, the SOI substrate potential Vsoi, and the current ID between the source / drain 4 are shown.
2 shows the time t dependence. Here, FIG. 3 shows a case where the final value of the gate potential VG is lower than V0, a case where V0 is not less than V1 in FIG. 4, a case where it is larger than V1 and lower than V2 in FIG. 4, and a case where it is not less than V2 in FIG. .

First, as shown in FIG. 3, the gate potential VG
When the final value of V is lower than V0, the substrate current Isoi does not flow (see FIG. 2), so that the SOI substrate potential Vsoi also does not occur in the semiconductor region 3. Therefore, no channel is formed on the surface of the semiconductor substrate 1 between the source / drain 4,
No current ID2 flows between the source and drain 4.

Next, as shown in FIG. 4, gate potential VG
If the final value of is greater than or equal to V0 and less than or equal to V1, the following behavior is exhibited. First, when t0 time elapses, the gate potential VG becomes V
It becomes 0 and the substrate current Isoi starts to flow (see FIG. 2).
Therefore, after the lapse of t0 time, the SOI substrate potential Vso
i starts to occur, and then the SOI substrate potential VSOI increases until it reaches a constant value. In this way, since the SOI substrate potential Vsoi is generated in the semiconductor region 3 after the lapse of time t0,
A channel is formed on the surface of the semiconductor substrate 1 existing thereunder via an insulating film, and S is formed between the source and drain 4.
The current ID2 corresponding to the value of the OI substrate potential Vsoi comes to be observed.

Further, as shown in FIG. 5, the gate potential V
When the final value of G increases and becomes equal to or higher than V1 and equal to or lower than V2, the SOI substrate potential Vsoi and the current ID between the source / drain 4 are kept until the gate potential VG reaches V1.
2 shows the same behavior as in FIG. 4, but when the value of the gate potential VG exceeds V1, the substrate current Isoi decreases (see FIG.
Accordingly, the SOI substrate potential Vsoi generated in the semiconductor region 3 correspondingly decreases, and the current ID2 between the source and drain 4 also decreases.

When the final value of the gate voltage VG further increases to V2 or more, the substrate current Isoi becomes difficult to flow (see FIG. 2), and as shown in FIG. 6, the SOI substrate potential Vsoi also becomes less likely to occur. The current ID2 between the source and drain 4 also stops flowing.

As described above, the final value of the gate potential VG is V
If it is within a predetermined range of 0 or more, the SOI substrate potential Vsoi is generated in the semiconductor region 3 at or after the rise of the gate potential VG. Therefore, for a gate potential VG of V0 or higher, a channel is formed on the semiconductor substrate 1 below the semiconductor region 3, and a current ID2 is observed between the source / drain 4 formed on the upper surface of the semiconductor substrate 1. As described above, the current ID2 functions as a monitor for detecting the potential V0, so that the semiconductor device has a function as a level sensor.

The current ID2 has a gate potential VG of V0.
Since the current does not flow until time t0, the current ID2
Also serves as a monitor at time t0, and this semiconductor device also has a timer function.

7 to 9 show an example of the process of forming the semiconductor device of the embodiment.

First, as shown in FIG. 7, a p-type Si semiconductor substrate 1 is manufactured according to a usual method for manufacturing a MOS transistor.
After forming the field stopper layer 8 by ion implantation of boron, the region is selectively oxidized to form a field oxide film (LOCOS) 9 for element isolation. After that, a silicon oxide film (first insulating film) 2 of about 500 Å is formed on the entire surface by a thermal oxidation method, and then p-type polysilicon (polycrystalline silicon) is formed on the entire surface by a CVD method (chemical vapor deposition method). About 5000Å is formed. Next, the p-type polysilicon is anisotropically etched using the resist film 10 as a mask, and further, the source / drain regions are formed on the semiconductor substrate 1 using the resist film 10 and the p-type polysilicon (semiconductor region) 3 as a mask. (First source / drain region) 4 is formed by ion implantation of arsenic or phosphorus.

Then, as shown in FIG. 8, a resist film 1 is formed.
After removing 0, the p-type polysilicon 3 becomes the SOI region
On the upper and side surfaces of the gate oxide film (second insulating film) 5
About 200Å. Next, the gate electrode 6 is formed by depositing n-type polysilicon, followed by lithography and etching. Then, the gate electrode 6
Is used as a mask to implant arsenic or phosphorus ions into the p-type polysilicon 3 to form source / drain regions (second source / drain regions) 7.

Then, as shown in FIG. 9, BPSG (b
orosilicate glass) film 11 is deposited on the entire surface, then contact hole 12 is opened, metal wiring 13 is formed of Al or W, and source electrode S1 and drain electrode D1 connected to source / drain region 7 and source / drain electrode D1 and source / drain region 7 are formed. Forming a source electrode S2 and a drain region D2 connected to the drain region 4,
Complete the semiconductor electrode.

Further, as shown in FIG. 10, when forming the source / drain regions 7 on the p-type polysilicon 3, after forming the sidewall insulating film 14 on the side surface of the gate electrode 6, the gate electrode 6 and the sidewall insulating film 14 are formed. Arsenic or phosphorus ions may be implanted using the film 14 as a mask. In this way, the drain region can be separated from the gate electrode 6,
The electric field in the drain region can be relaxed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

Although the semiconductor region 3 is made of polysilicon in the above embodiment, it may be made of single crystal silicon.

Further, the SOI is formed in multiple stages, the source / drain regions are formed respectively, and the current flowing in each source / drain region is controlled by the gate potential applied to the uppermost gate electrode. You may

[0027]

According to the present invention, when the gate potential on the semiconductor region formed on the semiconductor substrate exceeds a certain value,
Since the drain current flows through the transistor formed on the semiconductor substrate, it functions as a level sensor, and since the response of the drain current to the input of the gate potential has a certain delay, it also functions as a timer and the number of semiconductor devices is small. It can be formed in an occupied area, and the degree of integration can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor device of an example.

FIG. 2 is a drain current ID1 and an SOI substrate current Isoi.
FIG. 6 is a diagram showing the gate voltage VG dependency of the above.

FIG. 3 is a characteristic diagram showing a response of an SOI substrate potential Vsoi and a current ID2 flowing through a drain formed on the substrate side when a gate voltage VG is input.

FIG. 4 is a characteristic diagram showing a response of an SOI substrate potential Vsoi and a current ID2 flowing through a drain formed on the substrate side when a gate voltage VG is input.

FIG. 5 is a characteristic diagram showing a response of an SOI substrate potential Vsoi and a current ID2 flowing through a drain formed on the substrate side when a gate voltage VG is input.

FIG. 6 is a characteristic diagram showing a response of an SOI substrate potential Vsoi and a current ID2 flowing through a drain formed on the substrate side when a gate voltage VG is input.

FIG. 7 is a vertical cross-sectional view for explaining an example of the forming process of the semiconductor device.

FIG. 8 is a vertical cross-sectional view for explaining an example of the forming process of the semiconductor device.

FIG. 9 is a vertical cross-sectional view for explaining an example of the forming process of the semiconductor device.

FIG. 10 is a vertical sectional view for explaining another example of the forming process of the semiconductor device.

[Explanation of symbols]

1 semiconductor substrate 2 insulating film (first insulating film) 3 semiconductor region 4 source / drain region (first source / drain region) 5 gate insulating film (second insulating film) 6 gate electrode 7 source / drain region ( Second source / drain region)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical display location 9056-4M 311 J (72) Inventor Osamu Tsuchiya 2326 Imai, Ome, Tokyo Hitachi, Ltd. Device Development In the center (72) Inventor Jun Sugiura 2326 Imai, Ome City, Tokyo Hitachi Device Development Center

Claims (2)

[Claims] 1. A semiconductor substrate, a first source region and a first drain region provided on one main surface of the semiconductor substrate, and at least one of the first source region and the first drain region between the first source region and the first drain region. A first insulating film provided on the main surface, a semiconductor region provided on the first insulating film, and a second source region and a second drain region provided on the upper surface of the semiconductor region. A second insulating film provided at least on the main surface of the semiconductor region between the second source region and the second drain region, and a gate electrode provided on the second insulating film. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein a current flowing between the first source region and the first drain region is controlled by a gate potential applied to the gate electrode.