JPH0573273B2 - - Google Patents
Info
- Publication number
- JPH0573273B2 JPH0573273B2 JP61233615A JP23361586A JPH0573273B2 JP H0573273 B2 JPH0573273 B2 JP H0573273B2 JP 61233615 A JP61233615 A JP 61233615A JP 23361586 A JP23361586 A JP 23361586A JP H0573273 B2 JPH0573273 B2 JP H0573273B2
- Authority
- JP
- Japan
- Prior art keywords
- gallium arsenide
- insulating film
- mask
- electrodes
- arsenide substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D88/00—Three-dimensional [3D] integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はガリウム砒素集積回路のMIM容量に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to MIM capacitance of gallium arsenide integrated circuits.
MIM容量は配線金属を容量の両電極として使
用し、これら両電極間に絶縁膜をはさみ込むこと
により容量としているが、従来、ガリウム砒素集
積回路に用いられていたMIM容量はガリウム砒
素基板の平坦部分に形成されていた。
MIM capacitors use wiring metal as both capacitor electrodes and sandwich an insulating film between these two electrodes to create capacitance. Conventionally, MIM capacitors used in gallium arsenide integrated circuits It was formed in parts.
容量の容量値は電極の対向面積に比例し、電極
間の距離に反比例するため、容量値を大きくする
には、電極の面積を大きくするか、電極間の絶縁
膜を薄くすればよいが、電極の面積の増大はチツ
プ面積の増大になり、絶縁間を薄くすれば、ピン
ホールが発生しやすくなり信頼性が低下する。そ
のため、従来のガリウム砒素集積回路のMIM容
量は小面積で大きい容量値を得ることができない
という欠点がある。
The capacitance value of a capacitor is proportional to the opposing area of the electrodes and inversely proportional to the distance between the electrodes, so to increase the capacitance value, it is possible to increase the area of the electrodes or to thin the insulating film between the electrodes. Increasing the area of the electrodes increases the chip area, and if the insulation gap is made thinner, pinholes are more likely to occur, reducing reliability. Therefore, the MIM capacitor of the conventional gallium arsenide integrated circuit has the drawback that a large capacitance value cannot be obtained with a small area.
本発明によれば、ガリウム砒素基板上に成長し
不要部分を除去して段差を設けたマスクと、マス
ク間に存在し、マスクに対して自己整合してガリ
ウム砒素基板に形成された溝と、段差の部分を含
むマスクの外表面及び溝の表面に沿つて形成した
絶縁膜と、絶縁膜に沿つて形成した上側の電極層
とを備えたガリウム砒素集積回路のMIM容量が
得られる。
According to the present invention, a mask grown on a gallium arsenide substrate and provided with a step by removing an unnecessary portion; a groove existing between the masks and formed in the gallium arsenide substrate in self-alignment with the mask; A MIM capacitor of a gallium arsenide integrated circuit is obtained, which includes an insulating film formed along the outer surface of the mask including the step portion and the surface of the groove, and an upper electrode layer formed along the insulating film.
次に、図面を参照して本発明について説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。 FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
１はガリウム砒素基板２上に成長した絶縁膜で
あり、不要部分を除去して段差を設けてある。ガ
リウム砒素基板２には絶縁膜１をマスクにしてウ
エツトで異方性エツチングを施してＶ字型の溝が
つくられている。３，５はそれぞれ容量の下側と
上側との電極であり、配線金属を用いて形成す
る。４は容量に用いる絶縁膜である。 Reference numeral 1 denotes an insulating film grown on a gallium arsenide substrate 2, and an unnecessary portion is removed to provide a step. A V-shaped groove is formed in the gallium arsenide substrate 2 by wet anisotropic etching using the insulating film 1 as a mask. Reference numerals 3 and 5 denote electrodes on the lower and upper sides of the capacitor, respectively, which are formed using wiring metal. 4 is an insulating film used for capacitance.
以上説明したように本発明は、ガリウム砒素基
板上に成長した絶縁膜の不要部分を除去して段差
を設け、この絶縁膜とこの絶縁膜をマスクにして
異方性エツチングを施してガリウム砒素基板に設
けた窪みとの上にMIM容量を形成することによ
り、従来のMIM容量より大きな電極の対向面積
を得ることができるので、小面積で大きい容量値
を得ることができる効果がある。
As explained above, the present invention removes unnecessary parts of an insulating film grown on a gallium arsenide substrate to form a step, and then performs anisotropic etching using the insulating film as a mask to form a gallium arsenide substrate. By forming the MIM capacitor on top of the recess provided in the MIM capacitor, it is possible to obtain a larger opposing area of electrodes than the conventional MIM capacitor, which has the effect of obtaining a large capacitance value with a small area.
第１図は本発明の一実施例の縦断面図である。
１……絶縁膜、２……ガリウム砒素基板、３…
…下側の電極、４……絶縁膜、５……上側の電
極。
FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. 1... Insulating film, 2... Gallium arsenide substrate, 3...
... lower electrode, 4 ... insulating film, 5 ... upper electrode.
Claims (1)
して段差を設けたマスクと、前記マスク間に存在
し、前記マスクに対して自己整合して前記ガリウ
ム砒素基板に形成された溝と、前記段差の部分を
含む前記マスクの外表面及び前記溝の表面に沿つ
て形成した絶縁膜と、前記絶縁膜に沿つて形成し
た上側の電極層とを備えたことを特徴とするガリ
ウム砒素集積回路のMIM容量。1. A mask grown on a gallium arsenide substrate and provided with a step by removing an unnecessary portion, a groove existing between the mask and formed in the gallium arsenide substrate in self-alignment with the mask, and the step. An MIM for a gallium arsenide integrated circuit, comprising: an insulating film formed along the outer surface of the mask and the surface of the groove, and an upper electrode layer formed along the insulating film. capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61233615A JPS6387761A (en) | 1986-09-30 | 1986-09-30 | Metal insulator metal (mim) capacitance gallium arsenide integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61233615A JPS6387761A (en) | 1986-09-30 | 1986-09-30 | Metal insulator metal (mim) capacitance gallium arsenide integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6387761A JPS6387761A (en) | 1988-04-19 |
| JPH0573273B2 true JPH0573273B2 (en) | 1993-10-14 |
Family
ID=16957820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61233615A Granted JPS6387761A (en) | 1986-09-30 | 1986-09-30 | Metal insulator metal (mim) capacitance gallium arsenide integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6387761A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6251740B1 (en) | 1998-12-23 | 2001-06-26 | Lsi Logic Corporation | Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit |
| US6441419B1 (en) | 1998-03-31 | 2002-08-27 | Lsi Logic Corporation | Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same |
| US6417535B1 (en) * | 1998-12-23 | 2002-07-09 | Lsi Logic Corporation | Vertical interdigitated metal-insulator-metal capacitor for an integrated circuit |
| US6504202B1 (en) | 2000-02-02 | 2003-01-07 | Lsi Logic Corporation | Interconnect-embedded metal-insulator-metal capacitor |
| US6342734B1 (en) | 2000-04-27 | 2002-01-29 | Lsi Logic Corporation | Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same |
| US6341056B1 (en) | 2000-05-17 | 2002-01-22 | Lsi Logic Corporation | Capacitor with multiple-component dielectric and method of fabricating same |
| US6566186B1 (en) | 2000-05-17 | 2003-05-20 | Lsi Logic Corporation | Capacitor with stoichiometrically adjusted dielectric and method of fabricating same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6066851A (en) * | 1983-09-22 | 1985-04-17 | Oki Electric Ind Co Ltd | Ic capacitor and manufacture thereof |
| JPS60178659A (en) * | 1984-02-24 | 1985-09-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH079944B2 (en) * | 1984-07-30 | 1995-02-01 | 株式会社東芝 | Semiconductor memory device |
-
1986
- 1986-09-30 JP JP61233615A patent/JPS6387761A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6387761A (en) | 1988-04-19 |
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