JPH0574155B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a volume level display circuit for a magnetic recording/reproducing device, for example, a digital audio/playback device.
The present invention relates to a volume level display circuit that displays a volume level in a magnetic recording and reproducing device that records or reproduces audio signals on a magnetic tape, such as a tape recorder (hereinafter referred to as DAT).

[Prior art] Recently, using the principle of the rotating head of a VTR,
DAT, which records and plays PCM audio signals onto magnetic tape, is attracting attention. In such a DAT, the volume level of an audio signal to be recorded or reproduced can be visually checked using a level meter. To display the volume level using a level meter, the playback signal or recording signal is sampled within a certain period of time, and when the volume level reaches the maximum level (0 dB), a microcomputer displays the signal on the level meter display. There is one that displays “OVER”. With this method, when the volume level reached the maximum level only once, "OVER" was displayed even though it should have been displayed as "0 dB", resulting in an incorrect display.

[Problem to be solved by the invention] If the volume level reaches the maximum level only once within a certain period of time, "0 dB" is displayed, and if the maximum level is reached multiple times within a certain period of time, "OVER" is displayed. In order to display it, it is necessary to have such a display program built into the microcomputer. However, “0dB” and “OVER”
In order to be able to display both of these programs, the program capacity increases, and the memory capacity for storing such programs has to be increased.

Therefore, the main object of the present invention is to provide a peak detection means for detecting that the maximum level has been reached at least twice within a certain period of time by means of a hardware configuration, so that the normal volume can be adjusted without increasing the program capacity of the microcomputer. An object of the present invention is to provide a volume level display circuit for a magnetic recording/reproducing device capable of displaying the level.

[Means for Solving the Problems] The present invention is a volume level display circuit for a magnetic recording/reproducing device that displays the volume level using a display, and provides a circuit for displaying a volume level of a magnetic recording/reproducing device when the level of an input audio signal reaches a maximum level. and peak detection means for detecting the peak detection means, and detecting that the level of the input audio signal has reached the maximum level only once within a predetermined period of time, and has reached the maximum level at least twice or more according to the detection output of the peak detection means. a storage means for storing that the level of the audio signal has reached the maximum level only once; The apparatus further comprises a display means for displaying that the maximum level has been exceeded when it is remembered that the level has been reached.

[Function] The volume level display circuit of the magnetic recording and reproducing apparatus according to the present invention displays an "OVER" signal when the maximum level is reached at least twice within a predetermined time.
and when the maximum level is reached only once within a predetermined time, "0dB" is displayed.
It becomes possible to display the regular volume level.

[Embodiment of the Invention] FIG. 1 is a schematic block diagram of an embodiment of the present invention, and FIG. 2 is a specific block diagram of the peak detection circuit shown in FIG. 1 and its peripheral circuits.

First, the configuration of an embodiment of the present invention will be described with reference to FIGS. 1 and 2. The serial-parallel conversion circuit 1 is supplied with 16-bit serial sampling data indicating the volume level. The serial-parallel conversion circuit 1 converts the 16-bit serial sampling data into parallel sampling data. The converted sampling data is given to a peak detection circuit 2, a comparison circuit 3, and a data selector 4. The peak detection circuit 2 detects when the sampling data reaches the maximum level within a predetermined time. When the peak detection circuit 2 detects that the sampling data has reached the maximum level within a predetermined time, it applies an "H" level signal to the LSB of the parallel-to-serial conversion circuit 6 so that the sampling data does not reach the maximum level. When the maximum level is reached or only once, an "L" level signal is applied to the LSB of the parallel-serial conversion circuit 6.

The comparison circuit 3 compares the input sampling data with the sampling data input immediately before and which is latched in the latch circuit 5, and the input sampling data is larger than the sampling data input immediately before. When the input sampling data is smaller than or equal to the sampling data input immediately before, an “L” level signal is applied to the data selector 4. If the output of the comparison circuit 3 is "H" level, the data selector 4 selects the output of the serial-parallel conversion circuit 1 and causes the latch circuit 5 to latch it, and if the output of the comparison circuit 3 is "L" level, The output of the latch circuit 5 is selected and the latch circuit 5 is latched again. That is, the comparator circuit 3, data selector 4, and latch circuit 5 form a loop for constantly maintaining the maximum volume level.

The maximum level sampling data latched in the latch circuit 5 is applied to the parallel-serial conversion circuit 6. The parallel-to-serial conversion circuit 6 converts the data indicating whether the data is a peak value given from the peak detection circuit 2 and the sampling data into serial data, and provides the serial data to the microcomputer 7. The microcomputer 7 causes the level meter 8 to display the volume level according to the data.

Next, referring to FIG. 2, a more specific configuration of the peak detection circuit 2 shown in FIG. 1 will be described. The serial-parallel conversion circuit 1 converts the sampling data of the left channel (hereinafter referred to as L CH) and the right channel (hereinafter referred to as R CH) into parallel data, and supplies the data to comparison circuits 20 and 21, respectively. Comparing circuits 20 and 21 compare input sampling data with a maximum level. Here, the maximum level is set to 15 bits and "7FFF", for example.
The comparison circuits 20 and 21 are L CH and R, respectively.
Compare the CH input sampling data with the maximum level "7FFF", and if the input data is the maximum level "7FFF", output an "H" level signal,
If it is not "7FFF", it outputs an "L" level signal. The comparison outputs of comparison circuits 20 and 21 are applied to latch circuits 22 and 23, respectively. Latch circuits 22 and 23 latch the respective outputs of comparator circuits 20 and 21 based on sampling clock pulses, respectively. The Q outputs of the latch circuits 22 and 23 are given to the latch circuits 24 and 25, and these latch circuits 24 and 25 operate the latch circuits 22 and 2 based on the next sampling clock pulse.
Latch the Q output of 3.

Therefore, when the input data reaches the maximum level "7FFF" twice or more within a predetermined time, the latch circuits 22, 23, 24, and 25 each latch the "H" level. latch circuit 22,
The Q outputs of each of the latch circuits 24 and 24 are applied to an AND gate 26, and the Q outputs of each of the latch circuits 23 and 25 are applied to an AND gate 27. The AND gate 26 calculates the AND of the respective Q outputs of the latch circuits 22 and 24, and if the "H" level is latched in both, it supplies the "H" level signal to the LSB generating circuit 28 as a clock pulse. Also,
The AND gate 27 calculates the logical product of the Q outputs of the latch circuits 23 and 25, and if "H" is latched in both, the "H" level signal is used as a clock pulse to be sent to the LSB generation circuit 29. give.

The LSB generation circuits 28 and 29 include an AND gate 26,
If each output of 27 is “H” level,
An "H" signal is given to the parallel-serial conversion circuit 6. That is, when the input data reaches the maximum value level "7FFF" twice or more within a predetermined time, the LSB generation circuits 28 and 29 send an "H" level signal indicating the peak value to the parallel-serial conversion circuit 6. If the value is less than the peak value, an “L” level signal is provided to the parallel-to-serial conversion circuit 6.

FIG. 3 is a diagram showing an example of display data given to the microcomputer shown in FIG.
FIG. 4 is a diagram showing an example of a waveform diagram of a reproduction or recording signal.

Next, with reference to FIGS. 1 to 4, a specific operation of an embodiment of the present invention will be described.
First, in FIG. 1, if L does not reach the maximum level within a certain time t as shown in FIG. 4c,
It is assumed that sampling data of CH and R CH reproduction or recording signals is given to the serial-parallel conversion circuit 1.

In the peak detection circuit 2, the 16-bit parallel data converted as shown in FIG. 2 is applied to comparison circuits 20 and 21. Comparing circuits 20 and 21 compare the input parallel data with the maximum value "7FFF", and if the levels are the same, output a 1-bit "H" level signal, and if other data is input, Outputs only 1 bit of "L" level signal. Since the signal shown in FIG. 4c is below the maximum level, the comparison circuits 20 and 21 always output an "L" level signal within the fixed time t.
The Q outputs of the latch circuits 22, 23, 24, and 25 also become "L" level. Therefore,
Since the outputs of AND gates 26 and 27 also go to "L" level, the outputs of LSB generation circuits 28 and 29 also output "L" level signals. Therefore, the LSB of the parallel-serial conversion circuit 6 becomes "L" level.

Further, the sampling data outputted from the serial-parallel conversion circuit 1 is compared by the comparison circuit 3 shown in FIG. 1 with the peak level at the immediately previous sampling point latched by the latch circuit 5. The comparator circuit 3 gives an "H" level signal to the data selector 4 if the input sampling data is higher than the peak value at the sampling point on the screen, and if the level of the input sampling data is higher than the peak value at the previous sampling point. When they are smaller or equal, an "L" level signal is given to the data selector 4. Data selector 4 selects the output of serial-parallel conversion circuit 1 when the output of comparison circuit 3 is at "H" level, and selects the output of latch circuit 5 when the output of comparison circuit 3 is at "L" level. Therefore, the latch circuit 5
is always held at its maximum level.

The above operation is repeated at a constant sampling period within a constant time t, and the latch circuit 5 receives an L
The peak values of each 15 bits of CH and R CH are latched and applied to the parallel-to-serial converter circuit 6. Then, the parallel-to-serial conversion circuit 6 receives the “L” level from the peak detection circuit 2.
Latch each 15-bit data of L CH R CH along with LSB. This data is converted into serial data by a parallel-to-serial conversion circuit 6, and then displayed on a level meter 8 by a microcomputer 7.

Next, as shown in FIG. 4B, it is assumed that sampling data of a reproduced or recorded signal that reaches the maximum level only once within a certain period of time t is input to the serial-parallel conversion circuit 1. In this case as well, the input data is compared with the maximum value "7FFF" by the comparison circuits 20 and 21 of the peak detection circuit 2 in the same manner as described above. At this time, since the input data has reached the maximum value "7FFF" at the point in FIG. 4, the comparison circuits 20 and 21 each output an "H" level signal. The latch circuits 22 and 23 then latch the "H" level signal based on the sampling clock pulse.

At the point in FIG. 4, the input data is less than the maximum value "7FFF", so the comparator circuits 20, 21
The output becomes "L" level. Therefore, when the next sampling clock pulse is applied, the latch circuits 24 and 25 latch the "H" level signal which is the Q output of each of the latch circuits 22 and 23, but the latch circuits 22 and 23 circuit 20,
21 is latched. That is, the Q outputs of each of latch circuits 22 and 23 go to "L" level, and the Q outputs of each of latch circuits 24 and 25 go to "H" level. Therefore, AND gates 26 and 27 are closed, and the outputs of LSB generation circuits 28 and 29 become "L" level.

Furthermore, the comparator circuit 3, data selector 4, and latch circuit 5 shown in FIG. is latched, and this data is given to the parallel-to-serial conversion circuit 6. That is, the parallel-to-serial conversion circuit 6 is supplied with maximum value data and data whose LSB is "0" as shown in FIG. 3a. The microcomputer 7 then displays the data converted into serial data by the parallel-to-serial conversion circuit 6 on the level meter 8.
That is, "0 dB" is displayed on the level meter, indicating that the data has reached the maximum value.

Next, as shown in FIG. 4a, it is assumed that a reproduced or recorded signal in which the sampled data reaches the maximum level more than once within a certain period of time t is input to the serial-parallel conversion circuit 1. Then,
For example, the comparison circuits 20 and 21 of the peak detection circuit 2 detect that the sampling data at a point is the maximum value "7FFF".
The latch circuits 22 and 23 latch the "H" level comparison outputs of the comparison circuits 20 and 21, respectively. At the next sampling point, the comparator circuits 20 and 21 are at "H" because the input data exceeds the maximum value "7FFF".
Outputs level signal. And latch circuit 2
2 and 23 latch the outputs of the comparison circuits 20 and 21 at "H" level in response to the next sampling clock pulse, and latch circuits 24 and 25 output "H" level. Latch the output of

Therefore, the Q output of each of latch circuits 22, 23, 24 and 25 becomes "H" level.
As a result, AND gates 26 and 27 are opened, respectively, and provide "H" level clock signals to LSB generation circuits 28 and 29. LSB generation circuit 28,
29 outputs an "H" level signal to the LSB of the parallel-serial conversion circuit 6. At this time, since the input data has reached the maximum value, the latch circuit 5 shown in FIG. 1 latches "7FFF". Therefore, the parallel-to-serial conversion circuit 6 is supplied with data as shown in FIG. 3b.
The microcomputer 7 displays "OVER" on the level meter 8 based on the output of the parallel-serial conversion circuit 6.

[Effects of the Invention] As described above, according to the present invention, the level of the input audio signal increases by at least 2 within a predetermined time.
When the maximum level is reached more than once, the display means displays that the maximum level has been exceeded, and when the audio signal level reaches the maximum level only once, it is displayed that the maximum level has been reached. , it is possible to distinguish between exceeding the maximum value and reaching the maximum value and accurately display it.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of one embodiment of the present invention. FIG. 2 is a concrete block diagram of the peak detection circuit shown in FIG. 1 and its peripheral circuits. FIG. 3 is a diagram showing an example of display data given to the microcomputer shown in FIG. 1. FIG. 4 is a diagram showing an example of a waveform diagram of a reproduction or recording signal. In the figure, 1 is a serial-parallel conversion circuit;
2 is a peak detection circuit, 3, 20, 21 is a comparison circuit, 4 is a data selector, 5, 22, 23, 2
4 and 25 are latch circuits, 6 is a parallel-serial conversion circuit, 7 is a microcomputer, 8 is a level meter, 26 and 27 are AND gates, 28 and 29
indicates the LSB generation circuit.

Claims (1)

[Claims] 1. A magnetic recording and reproducing device that displays a volume level using a display device, comprising: peak detection means for detecting that the level of an input audio signal has reached a maximum level; storage means for storing, based on the detection output, that the level of the input audio signal has reached the maximum level only once within a predetermined period of time, and that the level of the input audio signal has reached the maximum level at least twice; and the storage means displays that the maximum level has been reached when it remembers that the audio signal level has reached the maximum level only once, and the audio signal level has reached the maximum level at least twice in a row. A volume level display circuit for a magnetic recording/reproducing device, comprising display means for displaying that the maximum level has been exceeded when the maximum level has been memorized.