JPH0574861B2 - - Google Patents

Info

Publication number
JPH0574861B2
JPH0574861B2 JP24574084A JP24574084A JPH0574861B2 JP H0574861 B2 JPH0574861 B2 JP H0574861B2 JP 24574084 A JP24574084 A JP 24574084A JP 24574084 A JP24574084 A JP 24574084A JP H0574861 B2 JPH0574861 B2 JP H0574861B2
Authority
JP
Japan
Prior art keywords
peripheral device
area
processing
flag
channel control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP24574084A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61123964A (ja
Inventor
Norio Shimada
Koichi Kondo
Kyoshi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24574084A priority Critical patent/JPS61123964A/ja
Publication of JPS61123964A publication Critical patent/JPS61123964A/ja
Publication of JPH0574861B2 publication Critical patent/JPH0574861B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP24574084A 1984-11-20 1984-11-20 チヤネル制御方式 Granted JPS61123964A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24574084A JPS61123964A (ja) 1984-11-20 1984-11-20 チヤネル制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24574084A JPS61123964A (ja) 1984-11-20 1984-11-20 チヤネル制御方式

Publications (2)

Publication Number Publication Date
JPS61123964A JPS61123964A (ja) 1986-06-11
JPH0574861B2 true JPH0574861B2 (de) 1993-10-19

Family

ID=17138094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24574084A Granted JPS61123964A (ja) 1984-11-20 1984-11-20 チヤネル制御方式

Country Status (1)

Country Link
JP (1) JPS61123964A (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE441872B (sv) * 1984-04-06 1985-11-11 Ericsson Telefon Ab L M Anordning for overvakning av ett databehandlingssystem

Also Published As

Publication number Publication date
JPS61123964A (ja) 1986-06-11

Similar Documents

Publication Publication Date Title
US4912631A (en) Burst mode cache with wrap-around fill
JPH0623968B2 (ja) データ転送制御システム
US4811280A (en) Dual mode disk controller
US4513369A (en) Information processing system
JPH0574861B2 (de)
JPH05197619A (ja) マルチｃｐｕ用メモリ制御回路
JPH01125644A (ja) データ転送装置
EP0787326B1 (de) System und verfahren zur verarbeitung von speicherdaten und kommunikationssystemen mit diesem system
JPH0225958A (ja) 高速データ転送システム
JP3157673B2 (ja) 仮想記憶システム
JPH05158795A (ja) キャッシュメモリシステム
JPS6211751B2 (de)
KR940006963Y1 (ko) 다채널 dma 회로
JPH0236012B2 (de)
JPS6174040A (ja) アドレス拡張方法
JPS60159954A (ja) メモリ制御方式
JPH037980B2 (de)
JPS6137655B2 (de)
JPH0727490B2 (ja) キャッシュメモリ
JPH0431417B2 (de)
JPS6174046A (ja) アドレス拡張方法
JPH01177661A (ja) データ転送装置
JPH04241047A (ja) アドレス拡張方式
JPS61272821A (ja) 磁気デイスク制御装置
JPS60126749A (ja) メモリ制御方式

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees