JPH0576207B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a hysteresis circuit composed of MOS transistors. [Prior Art] Conventionally, as a hysteresis circuit, a voltage comparator 21 and three resistors 25, 26, 27 shown in FIG.
A circuit configured with the following is known. In this example, resistors 25 and 26 are connected in series between the power supplies, and resistor 2
5 and the resistor 26 is connected to the reference voltage input terminal 22 of the voltage comparator 21 and also to one end of the resistor 27, and the other end of the resistor 27 is connected to the output 24 of the voltage comparator 21. It is configured. The voltage comparator 21 has a reference voltage input terminal 22 and a signal input terminal 23, and when the voltage level of the signal input terminal 23 is V _I <V _R , the voltage level of the output terminal 24 is the same as the power supply voltage V _DD . The voltage level is output and V _I
<V _R , the voltage level of the output terminal 24 is 0V. The resistance values of resistors 25, 26, and 27 are respectively
R ₂₅ , R ₂₆ , R ₂₇ , the voltage V _R at the reference voltage input terminal 22 is the voltage V _I at the input signal terminal 23
It has two states, V _RH and V _RL , depending on the state of , and each is expressed by the following equation. When V _I <V _R , the output of voltage comparator 21 is V _DD
It is becoming. Assuming that the output impedance of this voltage comparator 21 can be ignored, V _RH is
Since it is expressed by the parallel resistance of R ₂₅ and R ₂₇ and the divided voltage of R ₂₆ , V _RH = R ₂₆ / (R ₂₅ R ₂₇ ) + R ₂₆ · V _DD where (R ₂₅ R ₂₇ ) = R ₂₅ · R ₂₇ /R ₂₅ +R ₂₇ ∴V _RH =V _DD ×R ₂₆ /R ₂₅・R ₂₇ /R ₂₅ +R ₂₇ +R ₂₆ =V _DD × (R ₂₅ +R ₂₇ )R ₂₆ /R ₂₅・R ₂₇ + (R ₂₅ + _R27 )
R ₂₆ = V _DD × (R ₂₅ + R ₂₇ ) R ₂₆ /R ₂₅ R ₂₆ + R ₂₆ R ₂₇ + R ₂₅ R ₂₇
...(1) When V _I > V _R , the output of the voltage comparator 21 is OV
It is becoming. Therefore, since V _RL is expressed as the voltage divided by the parallel resistance of R ₂₆ and R 27 _and R ₂₅ , V _RL = (R ₂₆ R ₂₇ )/R ₂₅ + (R ₂₆ R ₂₇ )・V _DD Here (R ₂₆ R ₂₇ ) = R ₂₆・R ₂₇ /R ₂₆ +R ₂₇ ∴V _RL =V _DD ×R ₂₆・R ₂₇ /R ₂₆ +R ₂₇ /R ₂₅ +R ₂₆・R ₂₇ /R
₂₆ +R ₂₇ =V _DD ×R ₂₆・R ₂₇ / (R ₂₆ +R ₂₇ )R ₂₅ +R ₂₆・R ₂₇ =V _DD ×R ₂₆・R ₂₇ /R ₂₅ R ₂₆ +R ₂₆ R ₂₇ +R ₂₅ R ₂₇ …… (2) If V _RH > V _RL and V _I increases from 0V to V _DD , the voltage at output 24 will increase from V _DD to 0V with V _I = V _RH .
When V I changes from V DD to 0V, conversely, when V _I changes from V _DD to 0V,
When V _I =V _RL , it changes from 0V to V _DD , resulting in the input/output characteristics having hysteresis as shown in FIG. [Problem to be solved by the invention] The hysteresis width (V _RH − V _RL , hereinafter omitted) of the above-mentioned hysteresis circuit is ΔV=V _RH −V _RL =V _DD (R ₂₅ +R ₂₇ )R ₂₆ /R ₂₅ R ₂₆ +R ₂₆ R ₂₇ +R ₂₅ R ₂₇ −V _DD・R ₂₆・R ₂₇ /R ₂₅ R ₂₆ +R ₂₆ R ₂₇ +R ₂₅ R ₂₇ =V _DD ×R ₂₆・R ₂₇ /R ₂₅・R ₂₆ + (R ₂₅ +R ₂₆ ) R ₂₇ = V _DD ×R ₂₅・R ₂₆ /R ₂₅ +R ₂₆ /R ₂₅・R ₂₆ /R ₂₅ +R ₂₆ +R
₂₇ = V _DD × (R ₂₅ R ₂₆ )/(R ₂₅ R ₂₆ ) + R ₂₇ ……(3
) (∴(R ₂₅ R ₂₆ ) = R ₂₅ · R ₂₆ / R ₂₅ + R ₂₆ ) However, when setting ΔV small, the resistance values R ₂₅ , R ₂₆
It is necessary to make the resistance value R ₂₇ a large value compared to . For example, when V _DD = 5V and ΔV = 50mV, R ₂₅ = R ₂₆ and R ₂₅ :R ₂₆ :R ₂₇ =
The ratio is 1:1:49.5. Generally, when integrating the above-mentioned circuits, obtaining a resistor with a high resistance value increases the chip size, so it is necessary to use a resistor with a relatively low resistance value, so it is necessary to connect the power supply with a resistor with a relatively low resistance value. connected resistor 25,2
6, which has the disadvantage of increasing current consumption. Also, in order to improve the accuracy of the hysteresis width ΔV in the above explanation,
The output impedance of the voltage comparator 21 must be sufficiently low, and the voltage ratio comparator 21 must be a MOS transistor.
In order to obtain a low output impedance using a transistor, it is necessary to use a large MOS transistor, which also poses a problem in terms of integration. An object of the present invention is to provide a hysteresis circuit that consumes less current, is not affected by the output impedance of a voltage comparator, and is suitable for integration. [Means for Solving the Problems] The present invention has three MOS transistors, first, second, and third, and a voltage comparator, and the drain electrode and gate electrode of the first MOS transistor and the second
The drain electrodes of the MOS transistors are commonly connected to a first voltage source, and the source electrodes and substrates of the first and second MOS transistors are commonly connected to a third voltage source.
The drain electrode and gate electrode of the second MOS transistor are connected to the reference voltage input terminal of the voltage comparator, the gate electrode of the second MOS transistor is connected to the output of the voltage comparator, and the source electrode of the third MOS transistor and the substrate obtains a hysteresis circuit configured by being connected to the second voltage source. [Example] Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention.
This embodiment has a voltage comparator 1 composed of an N-type MOS transistor, three N-type MOS transistors 5, 6, and 7, and a MOS transistor 5.
The gate electrode and drain electrode of MOS transistor 7 are connected to the power supply in common, and the source electrode and substrate of MOS transistors 5 and 7 are connected to the drain electrode and gate electrode of MOS transistor 6 and the reference voltage comparator 1. The MOS transistor 7 is connected to the voltage input 2, the gate electrode of the MOS transistor 7 is connected to the output 4 of the voltage comparator 1, and the source electrode and substrate of the MOS transistor 6 are grounded. Voltage comparator 1 converts the voltage of reference voltage input 2 into V _R ,
When the voltage of the signal input 3 is V _I , when V _I <V _R , the same voltage as the power supply V _DD is output, and when V _I > V _R , the ground voltage 0V is output. In general, the drain current formula for a MOS transistor is I _DS = K・W/L (V _GS − V _T ) ² ...(4) where K is the conductivity coefficient, W is the channel width, L is the channel length, and V _GS is the gate.・The source-to-source voltage, V _T , is expressed as a threshold voltage. As β=K・W/L, three
Let β of MOS transistors 5, 6, and 7 be β ₅ ,
Expressed as β ₆ and β ₇ , the voltage of the reference voltage input when V _I < _VR is V _RH , and the voltage of the reference voltage input when V _I > _VR is
When V _{RL and} V _RL are V _I <V _R , the output of voltage comparator 1 is V _DD , and the current flowing through each MOS transistor is
From equation (4) and β=K·W/L, it is as follows. I _DS5 = β ₅ {(V _DD − V _RH ) − V _T } ² I _DS7 = β ₇ {(V _DD − V _RH ) − V _T } ² I _DS6 = β ₆ (V _RH − V _T ) ² or , I _DS5 + I _DS7 = I _DS6 , (β ₅ + β ₇ ) {(V _DD −V _RH )−V _T } ² = β ₆ (V _RH −V _T ) ^2Here , if we take the square root of both sides, we get √ ₅ + ₇ {V _DD −V _RH −V _T } =√ ₆ (V _RH −V _T )

[ka]

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[C] When V _I > V _R , the output of voltage comparator 1 becomes 0V, and the current flowing through each MOS transistor is
It will look like this: I _DS5 = β ₅ {(V _DD − V _RL ) − V _T } ² I _DS6 = β ₆ (V _RL − V _T ) ² I _DS7 = 0 (∴MOS transistor 7 is turned off) Also, I _DS5 =I From _DS6 , β ₅ {(V _DD −V _RL )−V _T } ² = β ₆ (V _RL −V _T ) ^2Here , if we take the square root of both sides, √ ₅ {(V _DD −V _RL ) −V _T } =√ ₆ (V _RL −V _T ) (V _DD −V _T )+√ _{6 5}・V _T = (1+√ _{6 5} )V _RL

[ ] becomes. In equations (5) and (6), when the relationship V _RH > V _RL holds and V _I rises from 0V to V _DD ,
When V _I = V _RH , the output voltage of voltage comparator 1 is from V _DD to
0V, V _R becomes V _RL , and V _I changes from V _DD to 0V
When V _I =V _RL , the output voltage of the voltage comparator 1 changes from 0V to V _DD and V _R becomes V _RH , so the hysteresis characteristic shown in FIG. 3 is obtained. In this example, the channel lengths L of the three MOS transistors are the same, and in this case, the above equation
(5) and (6) are expressed as follows, assuming that the channel widths of MOS transistors 5, 6, and ₇ are W ₅ , W ₆ , and W 7 .

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〔Effect of the invention〕

As described above, according to the present invention, the hysteresis width can be set by the ratio of channel widths of MOS transistors, and since the output of the voltage comparator is connected to the gate electrode of the MOS transistor, the voltage The effect of the output impedance of the comparator can be ignored, and a voltage comparator with high output impedance made up of MOS transistors can be used. In addition, the channel length of the MOS transistor can be set without affecting the hysteresis width, so the current A hysteresis circuit suitable for integration can be obtained by optimizing the hysteresis circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a hysteresis circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional hysteresis circuit, and FIG. 3 is a diagram showing hysteresis characteristics. 1, 21... Voltage comparator, 2, 22... Signal input, 3, 23... Reference voltage input, 4, 24... Output, 5, 6, 7... N-type MOS transistor, 2
5, 26, 27...Resistor, 8, 28...Power supply.

Claims (1)

[Claims] 1. A voltage comparator having a signal input terminal, a reference input terminal, and an output terminal, an input terminal connected to the signal input terminal of the voltage comparator, and an input terminal connected to the output terminal of the voltage comparator. and a first, second, and third MOS transistor connected to the output terminal;
The drain electrode and gate electrode of the MOS transistor and the drain electrode of the second MOS transistor are commonly connected to a first voltage source, and the source electrode and substrate electrode of the first and second MOS transistors are commonly connected to the first voltage source. The drain electrode and the gate electrode of the third MOS transistor are connected to the reference input terminal of the voltage comparator, the gate electrode of the second MOS transistor is connected to the output terminal of the voltage comparator, and the third MOS transistor is connected to the drain electrode and the gate electrode of the third MOS transistor. A hysteresis circuit characterized in that a source electrode and a substrate electrode of a MOS transistor are connected to a second voltage source. 2. The hysteresis circuit according to claim 1, wherein the first, second and third MOS transistors are N-type MOS transistors. 3. The hysteresis circuit according to claim 1, wherein the first, second and third MOS transistors are P-type MOS transistors. 4. Claim 1, wherein the voltage comparator is composed of a MOS transistor.
The hysteresis circuit according to item 1, 2 or 3.