JPH0577295B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement in a method of manufacturing a semiconductor integrated circuit incorporating a vertical PNP transistor and a normal bipolar NPN transistor.

(b) Prior Art A conventional method for manufacturing a semiconductor integrated circuit will be described with reference to FIGS. 2A to 2E.

First, as shown in FIG. 2A, a P-type silicon substrate is used as the semiconductor substrate 1, and antimony (Sb) is selectively deposited on the substrate 1 to form a plurality of buried layers 2. Boron (B) is deposited on the surface of the substrate 1 surrounding the substrate 2 and on a predetermined buried layer 2 to form a lower diffusion layer 4 of the upper and lower isolation regions 3 and a collector buried layer 5 of the vertical PNP transistor.

Next, as shown in FIG. 2B, an N-type epitaxial layer 6 is formed to a predetermined thickness over the entire surface of the substrate 1 by a well-known vapor phase growth method.

Next, as shown in FIG. 2C, an epitaxial layer 6 is formed.
Phosphorus (P) is ion-implanted into the region corresponding to the collector buried layer 5 on the surface, and the base region 7 of the vertical PNP transistor is attached. This ion implantation is performed at a dose of 10 ¹² to 10 ¹³ cm ^-2 and an acceleration voltage of 80 to 100 KeV.

Next, as shown in FIG. 2D, an epitaxial layer 6 is formed.
Vertical type with upper diffusion layer 8 of upper and lower separation regions 3 from the surface
The collector lead-out area 9 of the PNP transistor is approximately
Selective diffusion is performed at 1200° C. for 3 to 4 hours, and at the same time, the buried layer 2, lower diffusion layer 4, collector buried layer 5, and base region 7 are driven in. In this process, the upper diffusion layer 8
and lower diffusion layer 4 are connected to form upper and lower isolation regions 3, and epitaxial layer 6 is junction separated to form first and second island regions 10 and 11. In addition, the collector lead-out region 9 reaches as far as the collector buried layer 5,
surrounding the base region 7; Specifically, if the thickness of the epitaxial layer 6 is 13 μm, the thickness of the upper diffusion layer 8 is approximately 9 μm.
m, the lower diffusion layer 4 and the collector buried layer 5 are formed to a depth of approximately 7 μm, and the base region 7 is formed to a depth of approximately 4 μm. Here, between the upper diffusion layer 8 and the lower diffusion layer 4 of the upper and lower separation regions 3, the upper diffusion layer 8 is in a state where more impurities are supplied, that is, the diffusion source film containing a large amount of boron (B) remains attached. Due to reasons such as diffusion in the above state, the upper diffusion layer 8 is inevitably formed deeper than the lower diffusion layer 4.

Next, as shown in FIG. 2E, an epitaxial layer 6 is formed.
Selectively diffuse boron (B) from the surface to form the first island region 1
0 is the emitter region 1 of the vertical PNP transistor.
2, a base region 13 of a normal NPN transistor is formed in the second island region 11, and then phosphorus (P) is selectively diffused to form a base contact of a vertical PNP transistor in the first island region 10. Area 1
4, an emitter region 15 and a collector contact region 16 of an NPN transistor are formed in the second island region 11, respectively.

The vertical type formed in the first island region 10 in this way
Since a part of the active base of the PNP transistor is formed by the base region 7 formed by ion implantation, the impurity concentration gradient causes an internal drift electric field to increase the traveling speed of carriers, resulting in a high gain bandwidth product f _T is obtained. Also vertical PNP
Since the h _FE of the transistor is almost determined by the base region 7, even if the resistivity and thickness of the epitaxial layer 6 vary, the h _FE does not vary much. A vertical PNP transistor with such a structure is known, for example, as described in Japanese Patent Application Laid-open No.
It is described in Publication No. 59-211270.

A normal bipolar NPN transistor is then formed in the second island region 11, and its base region 13 is connected to the emitter region 12 of the vertical PNP transistor and the emitter region 15 of the NPN transistor.
is formed by diffusion at the same time as the base contact region 14 of the vertical PNP transistor.

(c) Problems to be solved by the invention However, in order to obtain a predetermined V _CE (sat), the collector buried layer 5 must be largely diffused upward, and the To get V _CEO , you have to have some base width. In the conventional manufacturing method, the base region 7 and the collector buried layer 5 are driven in by the diffusion process of the upper diffusion layer 8 of the upper and lower separation regions 3 , so due to the above-mentioned restrictions, the upper diffusion layer 8 is diffused for a long time. However, due to the lateral diffusion, the surface area is large and high integration is not possible.

Furthermore, in the NPN transistor formed in the second island region 11, the epitaxial layer 6 is set to be as thick as 10μ or more for the reason explained above, so the collector output resistance is large and V _CE (sat) is large. There was a certain drawback.

(d) Means for Solving the Problems The present invention was made in view of the above-mentioned drawbacks, and the lower diffusion layer 24 of the upper and lower isolation regions 23 and the collector buried layer 25 are made to have a thickness that is half the thickness of the epitaxial layer 26. After the base region 27 and the collector low resistance region 36 are driven in at the same time, the upper diffusion layer 28 and the collector lead-out region 29 of the upper and lower separation regions 23 are formed into the lower diffusion layer 24 and the collector buried layer, respectively. Bipolar type with greatly improved integration density by forming it to reach 25.
The present invention provides a method for manufacturing a semiconductor integrated circuit in which NPN transistors and vertical PNP transistors coexist.

(e) Effects According to the present invention, the upper diffusion layer 28 is formed after driving in the lower diffusion layer 24, the collector buried layer 25, and the base region 27 sufficiently deeply in advance, so that the upper diffusion layer 28 can be made shallow. , its lateral diffusion can be suppressed. Therefore, the degree of integration can be greatly improved without deteriorating the characteristics of the vertical PNP transistor.

Further, in the NPN transistor, the collector low resistance region 36 can be formed sufficiently deeper than the upper diffusion layer 28, so that a good V _CE (sat) can be obtained.

(F) Embodiment The method for manufacturing a semiconductor integrated circuit according to the present invention will be described in detail below with reference to FIGS. 1A to 1F.

First, as shown in FIG. 1A, a P-type silicon substrate is used as the semiconductor substrate 21, and antimony (Sb) is selectively deposited on the substrate 21 to form a plurality of buried layers 22. Substrate 2 surrounding 22
1 surface and a predetermined buried layer 22, boron (B) is deposited to form the lower diffusion layer 24 of the upper and lower isolation regions 23 and the collector buried layer 25 of the vertical PNP transistor.
form.

Next, as shown in FIG. 1B, an N-type epitaxial layer 26 is formed on the entire surface of the substrate 21 by a well-known vapor phase growth method.
is formed to a thickness of approximately 7 μm.

Next, as shown in FIG. 1C, an epitaxial layer 2 is formed.
6. Deposit phosphorus (P) to form the collector low resistance region 36 of the NPN transistor in a predetermined region on the surface of the epitaxial layer 26, and then ion-implant phosphorus (P) into the region corresponding to the collector buried layer 25 on the surface of the epitaxial layer 26. The base region 27 of the vertical PNP transistor
Attach. This ion implantation has a dose of 10 ¹² ~
10 ¹³ cm ^-2 and an accelerating voltage of 80 to 100 KeV.

Next, as shown in FIG.
By applying heat treatment at 1200°C for 2 hours, the lower diffusion layer 24 of the upper and lower isolation regions 23 and the collector buried layer 25 of the vertical PNP transistor are raised and diffused by more than half the thickness of the epitaxial layer 26, and at the same time, the vertical Drive in the base region 27 of the type PNP transistor. Specifically, the lower diffusion layer 24 and the collector buried layer 25 are raised by about 5 μm and diffused.
The base region 27 is formed to a depth of about 3 μm, and the collector low resistance region 36 is formed to a depth of about 4 μm. Therefore, the base region 27 completely reaches the collector buried layer 25. Note that the impurity concentration in the base region 27 may be made slightly lower so that it does not completely reach the collector buried layer 25.

Next, as shown in FIG. 1E, an epitaxial layer 2 is formed.
6. From the surface, the upper diffusion layer 28 of the upper and lower isolation regions 23 and the collector lead-out region 29 of the vertical PNP transistor are selectively diffused at the same time, and the upper and lower isolation regions 23 are connected at a position shallower than half the thickness of the epitaxial layer 26. , forming second island regions 30 and 31.

This step is a characteristic step of the present invention, in which the collector buried layer 25 and the lower diffusion layer 24 are raised and diffused in advance to a depth of more than half the thickness of the epitaxial layer 26, and at the same time the base region 27 and the collector low resistance region 36 are After diffusing deeply enough, the upper diffusion layer 28
Since the collector lead-out region 29 is formed, the upper diffusion layer 28 and the collector lead-out region 29 can be made shallow to about 3 μm without being limited by the base region 27 etc., and the diffusion time can be shortened to about 1 hour. Therefore, the lateral diffusion of the upper diffusion layer 28 and the collector lead-out region 29 can be suppressed to about 3 μm, and the surface area occupied by them can be significantly reduced. Specifically, if the width of the diffusion window is 4 μm, the width of the upper diffusion layer 28 and the collector lead-out region 29 is approximately 10 μm, and the width of the lower diffusion layer 2 is approximately 10 μm.
4 is approximately 14μ due to the amount of diffusion deeper than the upper diffusion layer 28.
It is formed as wide as m.

Next, as shown in FIG. 1F, an epitaxial layer 2 is formed.
Boron (B) is selectively diffused from the surface of 6, and the emitter region 32 of a vertical PNP transistor is formed in the first island region 30, and the base region 33 of a normal NPN transistor is formed in the second island region 31 with a thickness of about 2 μm. Then, phosphorus (P) is selectively diffused to form the base contact region 34 of the vertical PNP transistor in the first island region 30 and the base contact region 34 of the vertical PNP transistor in the second island region 31.
An emitter region 35 and a collector low resistance region 36 of the NPN transistor are each formed to a depth of about 1.5 μm. Note that since the emitter region 32 of the vertical PNP transistor is formed on the surface of the base region 27 which has a higher impurity concentration than the epitaxial layer 26,
It is formed somewhat shallower than the base region 33 of the NPN transistor. And finally electrode 3 on each area
7 is disposed and the manufacturing process is completed.

In the semiconductor integrated circuit formed in this manner, the upper diffusion layer 28 can be made significantly shallower, so that its lateral diffusion can be suppressed and the surface area occupied can be significantly reduced.
At this time, although the lower diffusion layer 24 is formed to be wider than the upper diffusion layer 28, its peripheral edge is curved due to lateral diffusion and gradually becomes narrower upward from the surface of the substrate 21. Even if the width is about 14 μm at the surface, it becomes about 4 μm at the top of the lower diffusion layer 24, which is the line width of the diffusion window. In addition, the epitaxial layer 26
The region formed by diffusion from the surface is also curved due to lateral diffusion, so that the width of the bottom of the region is equal to the width of the diffusion window. Therefore, the top of the lower diffusion layer 24 and the bottom of the region formed by diffusion from the surface of the epitaxial layer 26 are sufficiently spaced apart from each other, and from the viewpoint of breakdown voltage, the lower diffusion layer 24, which is formed wide, is closer to the epitaxial layer 26. Does not hinder the improvement of the degree of integration on the surface.

And the vertical PNP formed in the first island region 30
In the transistor, since the collector buried layer 25 and the base region 27 are driven in at the same time as the lower diffusion layer 24 of the upper and lower separation regions 23, they can be formed deep enough so that both collide with each other, resulting in an extremely good
V _CE (sat) characteristics are obtained. In addition, an epitaxial layer 26 in which all or substantially all of the active region as a base is formed by diffusion from the surface of the epitaxial layer 26
Since the base region 27 can be formed with a higher impurity concentration, a higher f _T can be obtained by sandwiching the base width _while considering the withstand voltage V _CEO and by applying electric field acceleration due to the concentration gradient. The variation in is reduced. Furthermore, since the collector lead-out region 29 is formed in the same process as the upper diffusion layer 28, the surface area occupied by the collector lead-out region 29 is significantly reduced, contributing to an improvement in the degree of integration.

On the other hand, in the NPN transistor formed in the second island region 31, the collector low resistance region 36 is formed in the same process as the lower diffusion layer 24 of the upper and lower isolation regions 23 , so the collector low resistance region 36 is formed more fully than the upper diffusion layer 28. If the optimum conditions are selected, the layer can be formed deep to reach the buried layer 22, resulting in extremely good V _CE (sat).
is obtained.

(G) Effects of the Invention As explained above, according to the present invention, the upper diffusion layer 28 is formed after the lower diffusion layer 24 is raised by more than half the thickness of the epitaxial layer 26 and then diffused. 28 can be made shallow, its lateral diffusion can be suppressed, and the degree of integration can be greatly improved. Furthermore, according to the present invention, since the collector buried layer 25, the base region 27, and the collector low resistance region 36 are driven in at the same time as the lower diffusion layer 34, even if the epitaxial layer 26 is set thin, it can be formed sufficiently deep. It has the advantage that a vertical PNP transistor and a bipolar transistor with good characteristics can coexist in an integrated manner.

Further, according to the present invention, since the diffusion time of the upper diffusion layer 28 is short, there are fewer crystal defects on the surface of the epitaxial layer 26 due to thermal diffusion, and furthermore, since the lower diffusion layer 24 is formed wider than the upper diffusion layer 28, some It has the advantage that complete junction separation can be obtained even if there is mask misalignment.

[Brief explanation of the drawing]

1A to 1F are cross-sectional views for explaining the manufacturing method according to the present invention, and FIGS. 2A to 2E
FIG. 2 is a cross-sectional view for explaining a conventional manufacturing method. 21 is a semiconductor substrate, 22 is a buried layer, 24 is a diffusion layer below the upper and lower separation region 23 , 25 is a collector buried layer, 26 is an epitaxial layer, 27 is a vertical PNP
The base region of the transistor, 28 is an upper diffusion layer of the upper and lower isolation regions 23, and 36 is a collector low resistance region.

Claims (1)

[Claims] 1 Impurities of opposite conductivity type forming a plurality of buried layers are attached to the surface of a semiconductor substrate of one conductivity type, and a diffusion layer below the upper and lower separation regions is formed on the surface of the substrate surrounding the buried layers. a step of depositing an impurity of one conductivity type to form a collector buried layer of a vertical PNP transistor on each of the predetermined buried layers; forming an epitaxial layer of the opposite conductivity type on the entire surface of the substrate; During the epitaxial growth step, re-diffusing each impurity adhering to the surface of the substrate in an upward direction; A step of ion-implanting an impurity of the opposite conductivity type to form the base region of the PNP transistor, and attaching an impurity of the opposite conductivity type to a part of the surface of the epitaxial layer to form the collector low resistance region of the NPN transistor. , Heat-treating the entire substrate to remove impurities forming the lower diffusion layer and the collector buried layer until they reach a position above half the thickness of the epitaxial layer, and simultaneously heat-treating the vertical PNP transistor. a step of stretching and diffusing the impurity forming the base region to a position below the top of the lower diffusion layer, and simultaneously stretching and diffusing the collector low resistance region; An upper diffusion layer and a collector lead-out region of the vertical PNP transistor are formed, and the upper and lower isolation regions are connected at a position deeper than the base of the NPN transistor to form a first island region and a second island region. a step of selectively diffusing impurities of one conductivity type from the surface of the epitaxial layer;
The emitter region of the PNP transistor is
A base region of an NPN transistor is formed in each of the island regions, and then impurities of opposite conductivity type are selectively diffused to form a base contact region of the vertical PNP transistor in the first island region and a base contact region of the vertical PNP transistor in the second island region. A method of manufacturing a semiconductor integrated circuit, comprising the step of forming emitter regions of the NPN transistors in each island region.