JPH0582581A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0582581A
JPH0582581A JP3240950A JP24095091A JPH0582581A JP H0582581 A JPH0582581 A JP H0582581A JP 3240950 A JP3240950 A JP 3240950A JP 24095091 A JP24095091 A JP 24095091A JP H0582581 A JPH0582581 A JP H0582581A
Authority
JP
Japan
Prior art keywords
film
pad
bonding
aluminum
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3240950A
Other languages
Japanese (ja)
Inventor
Junichi Ito
純一 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3240950A priority Critical patent/JPH0582581A/en
Publication of JPH0582581A publication Critical patent/JPH0582581A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • H10W72/01515Forming coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/981Auxiliary members, e.g. spacers
    • H10W72/983Reinforcing structures, e.g. collars

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】 アルミニウムパッドの腐食防止方法に関し,
パッドコロージョンを防止し,デバイスの信頼性を向上
させることを目的とする。 【構成】 1)半導体チップ上に形成されたアルミニウ
ム(Al)系金属膜からなるボンディングパッドの露出部分
を金(Au)膜で被覆する。 2)半導体チップ上に形成されたアルミニウム(Al)系金
属膜からなるボンディングパッドにワイヤボンディング
を行い,次いでボンディングパッドの露出部分に金(Au)
膜またはアルミナ(Al2O3) 膜を被覆するように構成す
る。
(57) [Summary] [Purpose] Regarding the method of preventing corrosion of aluminum pads,
The purpose is to prevent pad corrosion and improve device reliability. [Structure] 1) An exposed portion of a bonding pad made of an aluminum (Al) -based metal film formed on a semiconductor chip is covered with a gold (Au) film. 2) Wire bonding is performed on the bonding pad made of an aluminum (Al) -based metal film formed on the semiconductor chip, and then gold (Au) is applied to the exposed portion of the bonding pad.
It is configured to cover a film or an alumina (Al 2 O 3 ) film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
係り,アルミニウム(Al)パッドの腐食防止方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for preventing corrosion of aluminum (Al) pads.

【0002】一般的なプラスチックパッケージの半導体
装置においては,外気がパッケージを通して内部の半導
体チップ内に侵入することが知られている。このため,
湿度が原因のデバイス不良が発生し,中でもパッド部分
の金属配線が腐食するパッドコロージョンの現象があ
り,対策が要望されている。
In a general semiconductor device in a plastic package, it is known that outside air enters the internal semiconductor chip through the package. For this reason,
There is a phenomenon of pad corrosion, in which a device failure due to humidity occurs and metal wiring in the pad part corrodes, and countermeasures are required.

【0003】[0003]

【従来の技術】プラスチックパッケージの半導体装置あ
るいはパッケージを使用しないで直接基板やフイルム等
に実装する樹脂モールドによる封止方法においては,上
記のパッドコロージョンが発生していた。
2. Description of the Related Art The above-mentioned pad corrosion occurs in a sealing method using a resin mold which is directly mounted on a substrate, a film or the like without using a semiconductor device of a plastic package or a package.

【0004】この理由は,従来のパッドはその周縁部上
にカバー絶縁膜が被覆されており,金(Au)ワイヤのボー
ルボンディング等によりパッドから外部に導出されてい
るが,Alパッドの露出部分が存在するため, そこに外部
から侵入してきた湿気が作用ためである。
The reason for this is that the conventional pad has a cover insulating film coated on the periphery of the pad and is led out from the pad by ball bonding of a gold (Au) wire or the like. This is because the moisture that has entered from the outside acts on it.

【0005】パッドコロージョン防止のために,ワイヤ
ボンディングを上記のAuワイヤによるボールボンディン
グを用いると, ボンディングの際の加熱によるAuとAlの
合金化のためAlは腐食され難くなるが, その効果は充分
ではなかった。
When the above-mentioned ball bonding using Au wire is used to prevent pad corrosion, Al is less likely to be corroded due to the alloying of Au and Al due to heating during bonding, but the effect is not sufficient. Was not.

【0006】[0006]

【発明が解決しようとする課題】従来例においては,パ
ッドコロージョンにより断線不良を引起し,デバイスの
信頼性を低下させていた。
In the prior art example, pad corrosion causes a disconnection failure, which lowers the reliability of the device.

【0007】本発明はパッドコロージョンを防止し,デ
バイスの信頼性を向上させることを目的とする。
It is an object of the present invention to prevent pad corrosion and improve device reliability.

【0008】[0008]

【課題を解決するための手段】上記課題の解決は,1)
半導体チップ上に形成されたアルミニウム(Al)系金属膜
からなるボンディングパッドの露出部分を金(Au)膜で被
覆する半導体装置の製造方法,あるいは2)半導体チッ
プ上に形成されたアルミニウム(Al)系金属膜からなるボ
ンディングパッドにワイヤボンディングを行い,次いで
ボンディングパッドの露出部分に金(Au)膜またはアルミ
ナ(Al2O3) 膜を被覆する半導体装置の製造方法により達
成される。
[Means for Solving the Problems] 1)
A method of manufacturing a semiconductor device in which an exposed portion of a bonding pad made of an aluminum (Al) -based metal film formed on a semiconductor chip is covered with a gold (Au) film, or 2) aluminum (Al) formed on a semiconductor chip This is achieved by a method of manufacturing a semiconductor device in which wire bonding is performed on a bonding pad made of a system metal film and then an exposed portion of the bonding pad is covered with a gold (Au) film or an alumina (Al 2 O 3 ) film.

【0009】[0009]

【作用】本発明はAlの湿気による腐食を防止するため
に, パッドのコンタクト窓内にイオン化傾向の小さいAu
膜またはアルミナ(Al2O3) 膜で被覆することにより,耐
湿性を向上させたものである。
In order to prevent Al from being corroded by moisture, the present invention provides Au with a small ionization tendency in the contact window of the pad.
By coating with a film or an alumina (Al 2 O 3 ) film, the moisture resistance is improved.

【0010】そのための手段としては以下のようにす
る。 (1) 最上層の金属配線膜をAl+Auの2層構造とする。 (2) 最上層の金属配線膜をパターニング後,Auメッキを
する。 (3)パッドの窓開け後,Auメッキをする。 (4)パッド上にワイヤボンディング後,Auメッキをす
る。
The means for achieving this are as follows. (1) The uppermost metal wiring film has a two-layer structure of Al + Au. (2) After patterning the uppermost metal wiring film, Au plating is performed. (3) After opening the pad window, apply Au plating. (4) After wire bonding on the pad, apply Au plating.

【0011】なお,上記(2),(3),(4)のAuメッキの代わ
りに気相成長(CVD) による選択成長を行ってもよい。 (5) パッド上にワイヤボンディング後,パッド露出部に
陽極酸化法等によりAl2O3 膜を被覆する。
Instead of the Au plating described in (2), (3) and (4) above, selective growth by vapor phase epitaxy (CVD) may be performed. (5) After wire bonding on the pad, the exposed part of the pad is covered with an Al 2 O 3 film by an anodic oxidation method or the like.

【0012】[0012]

【実施例】図1 (A)〜(E) は本発明の実施例1を説明す
る断面図である。図1(A) において,シリコン(Si)基板
11上に,最上層の配線膜として厚さ1μmのAl膜1A, お
よびその上にスパッタまたは蒸着またはCVD 法により,
厚さ100〜5000ÅのAu膜1Bを被着する。
EXAMPLE 1 FIGS. 1A to 1E are sectional views for explaining Example 1 of the present invention. In Figure 1 (A), silicon (Si) substrate
11 Al film 1A having a thickness of 1 μm as the uppermost wiring film, and by sputtering or vapor deposition or the CVD method on it.
The Au film 1B having a thickness of 100 to 5000Å is applied.

【0013】図1(B) において,パッド部分を含んで配
線膜のパターニングをする。図1(C) において,CVD 法
によりカバー絶縁膜2として二酸化シリコン(SiO2)膜と
窒化シリコン(Si3N4) 膜の2層膜を被着する。
In FIG. 1B, the wiring film including the pad portion is patterned. In FIG. 1C, a two-layer film of a silicon dioxide (SiO 2 ) film and a silicon nitride (Si 3 N 4 ) film is deposited as the cover insulating film 2 by the CVD method.

【0014】図1(D) において,カバー絶縁膜2にボン
ディング用の窓開けを行う。図1(E) において,パッド
にワイヤボンディングを行う。このボンディング例はAu
ワイヤのボールボンディングである。図で, 3はAuボー
ル, 4はAuワイヤである。
In FIG. 1D, a window for bonding is opened in the cover insulating film 2. In Fig. 1 (E), wire bonding is performed on the pad. This bonding example is Au
It is ball bonding of wires. In the figure, 3 is an Au ball and 4 is an Au wire.

【0015】図2は本発明の実施例2を説明する断面図
である。この実施例は最上層の配線膜としてAl膜1Aのみ
を被着し,この膜をパターニング後,Al膜1A上にAuメッ
キまたはCVD Auの選択成長を行い, 厚さ 100〜5000Åの
Au膜1Bを形成する。
FIG. 2 is a sectional view for explaining the second embodiment of the present invention. In this embodiment, only the Al film 1A is deposited as the uppermost wiring film, and after this film is patterned, Au plating or CVD Au selective growth is performed on the Al film 1A to obtain a thickness of 100 to 5000Å.
The Au film 1B is formed.

【0016】ここで, CVD Auの選択成長条件の一例は次
の通りである。 反応ガス:(ジメチル 1,1,1トリフロロ 2,4ペンタジオ
ネード)ゴールド ガス圧力: 10 mTorr 基板温度: 150℃ RF 電力: 0.2 W/cm2 この後は図1 (C)〜(E) と同様である。
Here, an example of the selective growth condition of CVD Au is as follows. Reactive gas: (Dimethyl 1,1,1 trifluoro 2,4 pentadionade) Gold Gas pressure: 10 mTorr Substrate temperature: 150 ° C RF power: 0.2 W / cm 2 After this, see Figures 1 (C) to (E). It is the same.

【0017】図3は本発明の実施例3を説明する断面図
である。この実施例も最上層の配線膜としてAl膜1Aのみ
を被着し,この膜をパターニング後,カバー絶縁膜2を
被着し,コンタクト窓を開口後, Al膜1A上にAuメッキま
たはCVD Auの選択成長を行い, 厚さ 100〜5000ÅのAu膜
1Bを形成する。
FIG. 3 is a sectional view for explaining the third embodiment of the present invention. Also in this embodiment, only the Al film 1A is deposited as the uppermost wiring film, the insulating film 2 is deposited after patterning this film, the contact window is opened, and then Au plating or CVD Au is formed on the Al film 1A. By selective growth of 100-5000 Å thick Au film
Form 1B.

【0018】この後, ワイヤボンディングを行う。図4
(A)〜(E) は本発明の実施例4を説明する断面図であ
る。図4(A) において,Si基板11上に,最上層の配線膜
として厚さ1μmのAl膜1Aを被着する。
After that, wire bonding is performed. Figure 4
(A)-(E) is sectional drawing explaining Example 4 of this invention. In FIG. 4A, an Al film 1A having a thickness of 1 μm is deposited on the Si substrate 11 as the uppermost wiring film.

【0019】図4(B) において,パッド部分を含んで配
線膜のパターニングをする。図4(C) において,CVD 法
によりカバー絶縁膜2としてSiO2膜とSi3N4 膜の2層膜
を被着する。
In FIG. 4B, the wiring film including the pad portion is patterned. In FIG. 4 (C), a two-layer film of SiO 2 film and Si 3 N 4 film is deposited as the cover insulating film 2 by the CVD method.

【0020】次いで,カバー絶縁膜2にボンディング用
の窓開けを行う。図4(D) にパッドにワイヤボンディン
グを行う。このボンディング例は,Auのボールボンディ
ングで, 3はAuボール, 4はAuワイヤである。
Next, a window for bonding is opened in the cover insulating film 2. Wire bonding is performed on the pad as shown in FIG. This bonding example is Au ball bonding, 3 is an Au ball, and 4 is an Au wire.

【0021】図4(E) において,パッド上にAuメッキ膜
(またはCVD Au膜) 5を形成する。この際, Auメッキ膜
4により,Alパッドの露出部を被覆する。図5は本発明
の実施例5を説明する断面図である。
In FIG. 4 (E), an Au plating film (or CVD Au film) 5 is formed on the pad. At this time, the exposed portion of the Al pad is covered with the Au plating film 4. FIG. 5 is a sectional view illustrating a fifth embodiment of the present invention.

【0022】ワイヤボンディング終了後,Alパッドの露
出部を陽極酸化してAl表面にAl2O3膜6を形成する。陽
極酸化の条件の一例を次に示す。
After completion of wire bonding, the exposed portion of the Al pad is anodized to form an Al 2 O 3 film 6 on the Al surface. An example of anodizing conditions is shown below.

【0023】 電解液:シュウ酸水溶液 電圧: 20 V 陰極: 槽内壁(接地) 温度: 20℃ 実施例では,Auボールボンディングを使用しているが,
他のボンディングであってもよい。
Electrolyte: Aqueous oxalic acid solution Voltage: 20 V Cathode: Chamber inner wall (ground) Temperature: 20 ° C. In the embodiment, Au ball bonding is used.
Other bonding may be used.

【0024】また, チップ上にポリイミド被覆を行った
場合も本発明は適用可能である。
The present invention is also applicable when the chip is covered with polyimide.

【0025】[0025]

【発明の効果】本発明によれば,パッドコロージョンが
防止でき,デバイスの信頼性向上に寄与することができ
た。
According to the present invention, pad corrosion can be prevented and the device reliability can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例1を説明する断面図FIG. 1 is a sectional view illustrating a first embodiment of the present invention.

【図2】 本発明の実施例2を説明する断面図FIG. 2 is a sectional view illustrating a second embodiment of the present invention.

【図3】 本発明の実施例3を説明する断面図FIG. 3 is a sectional view illustrating a third embodiment of the present invention.

【図4】 本発明の実施例4を説明する断面図FIG. 4 is a sectional view illustrating a fourth embodiment of the present invention.

【図5】 本発明の実施例5を説明する断面図FIG. 5 is a sectional view illustrating a fifth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11 半導体基板でSi基板 1A 最上層の配線膜でAl膜 1B Al膜1Aを被覆するAu膜 2 カバー絶縁膜 3 Auボール 4 Auワイヤ 5 Auメッキ膜(またはCVD Au膜) 6 Al2O311 Semiconductor substrate Si substrate 1A Uppermost wiring film Al film 1B Al film 1A Au film covering 2 A Cover insulating film 3 Au ball 4 Au wire 5 Au plating film (or CVD Au film) 6 Al 2 O 3 film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップ上に形成されたアルミニウ
ム(Al)系金属膜からなるボンディングパッドの露出部分
を金(Au)膜で被覆することを特徴とする半導体装置の製
造方法。
1. A method of manufacturing a semiconductor device, wherein an exposed portion of a bonding pad made of an aluminum (Al) -based metal film formed on a semiconductor chip is covered with a gold (Au) film.
【請求項2】 半導体チップ上に形成されたアルミニウ
ム(Al)系金属膜からなるボンディングパッドにワイヤボ
ンディングを行い,次いでボンディングパッドの露出部
分に金(Au)膜またはアルミナ(Al2O3)膜を被覆すること
を特徴とする半導体装置の製造方法。
2. A wire bonding is performed on a bonding pad made of an aluminum (Al) -based metal film formed on a semiconductor chip, and then a gold (Au) film or an alumina (Al 2 O 3 ) film is formed on an exposed portion of the bonding pad. A method for manufacturing a semiconductor device, comprising:
JP3240950A 1991-09-20 1991-09-20 Manufacture of semiconductor device Withdrawn JPH0582581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3240950A JPH0582581A (en) 1991-09-20 1991-09-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3240950A JPH0582581A (en) 1991-09-20 1991-09-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0582581A true JPH0582581A (en) 1993-04-02

Family

ID=17067068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3240950A Withdrawn JPH0582581A (en) 1991-09-20 1991-09-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0582581A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2724489A1 (en) * 1994-08-19 1996-03-15 Fujitsu Ltd SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
KR100335514B1 (en) * 1993-12-29 2002-12-02 다우 코닝 코포레이션 Sealing method of integrated circuit assembly
JP2004128513A (en) * 2003-11-26 2004-04-22 Rohm Co Ltd Semiconductor device and method of manufacturing the same
US6890857B2 (en) 2000-01-12 2005-05-10 Renesas Technology Corp. Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion, and method for fabricating the same
JP2006203215A (en) * 2006-01-23 2006-08-03 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method thereof
JP2015144168A (en) * 2014-01-31 2015-08-06 三菱電機株式会社 semiconductor device
WO2019163484A1 (en) * 2018-02-22 2019-08-29 三菱電機株式会社 Semiconductor element and method of manufacturing same
US10879187B2 (en) 2017-06-14 2020-12-29 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
US11348876B2 (en) 2017-06-14 2022-05-31 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100335514B1 (en) * 1993-12-29 2002-12-02 다우 코닝 코포레이션 Sealing method of integrated circuit assembly
FR2724489A1 (en) * 1994-08-19 1996-03-15 Fujitsu Ltd SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
US6890857B2 (en) 2000-01-12 2005-05-10 Renesas Technology Corp. Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion, and method for fabricating the same
JP2004128513A (en) * 2003-11-26 2004-04-22 Rohm Co Ltd Semiconductor device and method of manufacturing the same
JP2006203215A (en) * 2006-01-23 2006-08-03 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method thereof
JP2015144168A (en) * 2014-01-31 2015-08-06 三菱電機株式会社 semiconductor device
US10879187B2 (en) 2017-06-14 2020-12-29 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
US11348876B2 (en) 2017-06-14 2022-05-31 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
WO2019163484A1 (en) * 2018-02-22 2019-08-29 三菱電機株式会社 Semiconductor element and method of manufacturing same
JPWO2019163484A1 (en) * 2018-02-22 2020-10-08 三菱電機株式会社 Semiconductor devices and their manufacturing methods

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