JPH0582702A - Semiconductor package - Google Patents

Abstract

PURPOSE:To make it possible to analyze easily the causes of bonding defects of an inner lead by indicating mark which includes a terminal identification number and characters and digits by means of printing and marking on the surface of the inner lead. CONSTITUTION:In the case of a flat package, for example, a mark 6 is indicated by numeric and alphabetical printing or marking or their combination at the tip of an inner lead 4 so that it is easy to discriminate the classification of each inner lead, especially in the case of multiple pin package. This construction makes it possible to clarify the correspondence between a terminal with defective electric properties and its corresponding inner lead 4 and bonding pad 2 in an attempt to analyze bonding failures and the like and investigate the defective spots with ease.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a multi-pin flat package having 100 pins or more and a TAB (Tape Automated Bondi).
ng) package.

[0002]

2. Description of the Related Art Semiconductor packages, especially surface mount type packages, have a marked tendency to have a large number of pins and fine pitch.
In addition to realizing 0 or more pins, TAB packages in which inner leads are formed on a tape film and connected to an LSI chip have begun to spread in earnest as a technique for facilitating the increase in the number of pins.

FIG. 3 is a partially enlarged plan view of an example of inner lead connection of a conventional flat package.

As shown in FIG. 3, in order to realize a large number of pins, the width and pitch of the inner leads 4 and the pitch of bonding are all becoming finer.

FIG. 4 is a partially enlarged plan view of an example of an inner lead connecting portion of a conventional TAB package.

Further, as shown in FIG. 4, in the TAB package in which the inner leads 4 are patterned on the tape film, as compared with the flat package shown in FIG.
Further, there is an advantage that the pitch of the inner leads 4 can be made finer.

[0007]

In these conventional multi-pin packages, it becomes difficult to distinguish individual inner leads from each other as the lead width and pitch are narrowed and the number of pins is increased.
In the analysis of bonding failure of the inner lead, there is a problem that it takes time to associate the electrically defective terminal number with the corresponding inner lead.

An object of the present invention is to provide a semiconductor package in which individual inner leads can be distinguished from each other, and by associating an electrically defective terminal number with a corresponding inner lead, it is possible to easily analyze a defective bonding of the inner leads. Especially.

[0009]

According to the semiconductor package of the present invention, a mark including a terminal identification number, a letter, a number and a symbol is displayed on the surface of the inner lead by either a stamp or an engraved mark.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a partially enlarged plan view of an inner lead connecting portion according to the first embodiment of the present invention.

The first embodiment, as shown in FIG. 1, is an embodiment of a flat package in which a mark 6 is displayed at the tip of the inner lead 4 by marking or engraving with numbers, alphabets or a combination thereof. There is.

FIG. 2 is a partially enlarged plan view of the inner lead connecting portion according to the second embodiment of the present invention.

In the second embodiment, as shown in FIG. 2, TA
In the embodiment of the B package, as in the first embodiment of FIG. 1, the inner lead 4 is marked with a numeral, an alphabet, or a combination thereof by marking or engraving.

[0015]

As described above, according to the present invention, since the terminal number and the terminal name are displayed on the surface of the inner lead, it is easy to distinguish the individual inner lead terminals, especially in the multi-pin package, and the bonding is facilitated. In the analysis of defects and the like, it has an effect of clarifying the correspondence between the electrical characteristic defective terminal and the corresponding inner lead and bonding pad, and facilitating the investigation of the defective portion.

[Brief description of drawings]

FIG. 1 is a partially enlarged plan view of an inner lead connecting portion according to a first embodiment of the present invention.

FIG. 2 is a partially enlarged plan view of an inner lead connecting portion according to a second embodiment of the present invention.

FIG. 3 is a partially enlarged plan view of an example of an inner lead connecting portion of a conventional flat package.

FIG. 4 is a partially enlarged plan view of an example of an inner lead connecting portion of a conventional TAB package.

[Explanation of symbols]

 1 semiconductor chip 2 bonding pad 3 bonding wire 4 inner lead 5 bonding bump 6 marking 7 tape film

Claims (1)

[Claims] 1. A semiconductor package, characterized in that a mark including a terminal identification number, a letter, a numeral and a symbol is displayed on the surface of the inner lead by one of a marking and a marking.