JPH0583014B2 - - Google Patents

Info

Publication number
JPH0583014B2
JPH0583014B2 JP61168117A JP16811786A JPH0583014B2 JP H0583014 B2 JPH0583014 B2 JP H0583014B2 JP 61168117 A JP61168117 A JP 61168117A JP 16811786 A JP16811786 A JP 16811786A JP H0583014 B2 JPH0583014 B2 JP H0583014B2
Authority
JP
Japan
Prior art keywords
order group
side circuit
group side
low
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61168117A
Other languages
Japanese (ja)
Other versions
JPS6326047A (en
Inventor
Kazue Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP61168117A priority Critical patent/JPS6326047A/en
Publication of JPS6326047A publication Critical patent/JPS6326047A/en
Publication of JPH0583014B2 publication Critical patent/JPH0583014B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は光フアイバケーブル等の有線伝送路に
おいて一対の伝送路に当初ある回線容量を伝送
し、後日その2倍および4倍の回線容量に増やす
場合に適用できる経済的な多重変換方式に関す
る。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention transmits the line capacity initially on a pair of transmission lines in a wired transmission line such as an optical fiber cable, and later increases the line capacity to double or quadruple the line capacity. This paper relates to an economical multiplex conversion method that can be applied when increasing the amount of data.

〔従来の技術〕[Conventional technology]

従来の多重変換装置においては、その最大容量
をさらに増加させる場合、同様の多重変換装置と
さらに高次の多重変換装置を追加するか、或いは
既存の多重変換装置を撤去してより大容量の多重
変換装置に置換える方法がとられていた。
In order to further increase the maximum capacity of a conventional multiplex converter, it is necessary to add a similar multiplex converter and a higher-order multiplex converter, or remove the existing multiplex converter and install a multiplexer with a larger capacity. The method used was to replace it with a conversion device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の増設方法では、変更が大がかり
となり、装置コストおよび設置コストが高くなる
という欠点がある。又、より高次の多重変換装置
へ接続する方法では、設置スペースの増加、消費
電力の増大も伴なう。更に、より大容量の多重変
換装置へ置換える方法では、既設の装置が使えな
くなる為、割高となる。
The above-described conventional expansion method has the drawback that the changes are extensive and the equipment cost and installation cost are high. Furthermore, the method of connecting to a higher-order multiplex converter also requires an increase in installation space and power consumption. Furthermore, the method of replacing the converter with a multiplex converter having a larger capacity is expensive because the existing device cannot be used.

〔問題点を解決するための手段〕[Means for solving problems]

本発明による多重変換方式は、低次群と高次群
間の中間信号の入出力端子を備えた同一構成の単
位ブロツクを複数台並列に並べ、高次群側回路を
特定のブロツクに置き、ブロツク間を中間信号レ
ベルで接続することにより、単位ブロツクの2倍
および4倍の容量に拡張できる構成としたもので
ある。各ブロツクは、ほぼ共通の低次群側回路と
内部接続を有し、高次群側回路部のみを多重形態
により変更できる様な構成になつている。
The multiplex conversion method according to the present invention consists of arranging a plurality of unit blocks of the same configuration in parallel and having input/output terminals for intermediate signals between the low-order group and the high-order group, placing the high-order group side circuit in a specific block, and using an intermediate signal between the blocks. By connecting at the signal level, the capacity can be expanded to twice or four times that of the unit block. Each block has a substantially common low-order group side circuit and internal connections, and is configured such that only the high-order group side circuit section can be changed by multiplexing.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して
詳細に説明する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図を参照すると、本発明の一実施例に用い
られる単位ブロツク(基本ブロツク)の構成がブ
ロツク図により示されている。図中、11は低次
群側回路、12は高次群側回路を示す。13は低
次群側回路11と高次群側回路12間の中間信号
の内部接続であり、そのうちの半分は、端子14
により任意に接続を変更できるようになつてい
る。又、端子15が、高次群側回路12に外部か
ら低次群・高次群間の中間信号を入出力できるよ
うに設けられている。
Referring to FIG. 1, a block diagram shows the structure of a unit block (basic block) used in one embodiment of the present invention. In the figure, 11 indicates a low-order group side circuit, and 12 indicates a high-order group side circuit. 13 is an internal connection for intermediate signals between the low-order group side circuit 11 and the high-order group side circuit 12, half of which is connected to the terminal 14.
This allows you to change the connection at will. Further, a terminal 15 is provided so that an intermediate signal between the low-order group and the high-order group can be inputted and outputted to the high-order group side circuit 12 from the outside.

第2図は第1図に示した基本ブロツク1台のみ
を使用する場合の構成を示す。図中、21は低次
群入出力信号、24は高次群入出力信号である。
中間信号のうち半分は信号線25により相互接続
されている。このため、低次群側回路22は高次
群側回路23と1対1に対応している。低次群側
回路22に多重変換回路が含まれている場合は、
高次群側回路23では多重/分離動作を行なわ
ず、高次群入出力信号24とのインタフエース処
理のみを行う。
FIG. 2 shows a configuration in which only one basic block shown in FIG. 1 is used. In the figure, 21 is a low-order group input/output signal, and 24 is a high-order group input/output signal.
Half of the intermediate signals are interconnected by signal lines 25. Therefore, the low-order group side circuit 22 has a one-to-one correspondence with the high-order group side circuit 23. If the low-order group side circuit 22 includes a multiple conversion circuit,
The higher-order group side circuit 23 does not perform multiplexing/demultiplexing operations, but performs only interface processing with the higher-order group input/output signal 24.

第3図は第1図に示した基本ブロツクを2台用
いて基本ブロツクの2倍の多重度を実現した例を
示すブロツク図である。低次群側回路32は第2
図の低次群側回路22と同一である。これに対
し、高次群側が多重処理部33と分離処理部35
に置換わつている。又、2台の基本ブロツクが信
号線36により相互接続されている。
FIG. 3 is a block diagram showing an example in which two basic blocks shown in FIG. 1 are used to realize twice the multiplicity of the basic blocks. The low-order group side circuit 32 is the second
This is the same as the low-order group side circuit 22 in the figure. On the other hand, on the higher order group side, the multiple processing unit 33 and the separation processing unit 35
It is being replaced by . Further, the two basic blocks are interconnected by a signal line 36.

第4図は第1図に示した基本ブロツクを4台用
いて基本ブロツクの4倍の多重度を実現した例を
示すブロツク図である。低次群側回路42は第2
図及び第3図の低次群側回路22及び32と同一
である。高次群側が、多重処理部43、分離処理
部45、および通過接続回路46に置換わつてい
る。又、4台の基本ブロツクは信号線47,48
により相互接続されている。
FIG. 4 is a block diagram showing an example in which four basic blocks shown in FIG. 1 are used to realize a multiplicity four times that of the basic blocks. The low-order group side circuit 42 is the second
This circuit is the same as the low-order group side circuits 22 and 32 shown in FIGS. The higher-order group side is replaced with a multiple processing section 43, a separation processing section 45, and a pass-through connection circuit 46. Also, the four basic blocks have signal lines 47 and 48.
are interconnected by

第5図は第1図に示した基本ブロツクを外部の
多重変換装置に縦続接続する場合の構成を示すブ
ロツク図である。低次群側回路52は第2図、第
3図、及び第4図の低次群側回路22,32、及
び42と同一である。高次群側をすべて通過接続
回路53に置換え、中間信号を外部で多重変換す
る。この構成は、基本ブロツクの5倍以上の多重
度が必要な時に使用される。
FIG. 5 is a block diagram showing a configuration in which the basic block shown in FIG. 1 is cascaded to an external multiplex converter. The low-order group side circuit 52 is the same as the low-order group side circuits 22, 32, and 42 of FIGS. 2, 3, and 4. All high-order groups are replaced with pass-through connection circuits 53, and intermediate signals are multiplexed and converted externally. This configuration is used when a multiplicity of 5 times or more than the basic block is required.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明による多重変換方
式は、初期投資を最少に押え、しかも将来の大容
量化に経済的に対応できるという利点がある。特
に、光フアイバケーブルを媒体とする伝送路にお
いては、伝送信号の多重度(伝送速度)が上がつ
ても中継器の間隔をほぼ一定にできるため、本発
明のような多重度を容易に上げられる多重変換装
置のメリツトが大きい。
As explained above, the multiplex conversion method according to the present invention has the advantage of minimizing initial investment and being able to economically cope with future increases in capacity. In particular, in transmission lines using optical fiber cables, the spacing between repeaters can be kept almost constant even when the multiplicity (transmission speed) of transmission signals increases, so it is easy to increase the multiplicity as in the present invention. The advantages of a multiplex converter that can be used are significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に用いられる基本ブ
ロツクの構成を示すブロツク図、第2図は第1図
の基本ブロツクを1台のみ使用する場合の構成を
示すブロツク図、第3図は第1図の基本ブロツク
を2台用いて基本ブロツクの2倍の多重度を実現
した例を示すブロツク図、第4図は第1図の基本
ブロツクを4台用いて基本ブロツクの4倍の多重
度を実現した例を示すブロツク図、第5図は第1
図の基本ブロツクを外部の多重変換装置に縦続接
続する場合の構成を示すブロツク図である。 11,22,32,42,52…低次群側回路
(低次群入出力又は多重/分離回路)、12,23
…高次群側回路(高次群入出力又は多重/分離回
路)、13…中間レベル信号線、14,15…中
間レベル信号接続端子、21,31,41,51
…低次群入出力信号、24,34,44,55…
高次群入出力信号、25,36,47,48,5
7,58…外部接続線、33,43,54…多重
および高次群出力回路、35,45,56…高次
群入力および分離回路、46,53…通過接続回
路。
FIG. 1 is a block diagram showing the configuration of a basic block used in one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration when only one basic block shown in FIG. 1 is used, and FIG. A block diagram showing an example in which two basic blocks in Fig. 1 are used to achieve twice the multiplicity of the basic blocks. A block diagram showing an example of achieving severe symptoms, Figure 5 is the first
FIG. 2 is a block diagram showing a configuration when the basic blocks shown in the figure are cascade-connected to an external multiplex converter. 11, 22, 32, 42, 52...low-order group side circuit (low-order group input/output or multiplexing/separating circuit), 12, 23
...High-order group side circuit (high-order group input/output or multiplexing/separation circuit), 13...Intermediate level signal line, 14, 15...Intermediate level signal connection terminal, 21, 31, 41, 51
...low-order group input/output signals, 24, 34, 44, 55...
High-order group input/output signal, 25, 36, 47, 48, 5
7, 58... External connection line, 33, 43, 54... Multiplex and higher order group output circuit, 35, 45, 56... Higher order group input and separation circuit, 46, 53... Pass-through connection circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 低次群入出力信号21,31,41,51を
送受信する低次群側回路11と、インターフエー
ス処理部23、多重処理部33,43、分離処理
部35,45、および通過接続回路46,53の
いずれか1つに取替え可能で、高次群入出力信号
24,34,44を送受信する高次群側回路12
と、前記低次群側回路と前記高次群側回路とを内
部接続する中間レベル信号線13と、前記低次群
側回路に接続され、高次群側回路との相互間の中
間信号の接続を変更可能な第1の中間レベル信号
接続端子14と、前記高次群側回路に接続され、
低次群側回路との相互間の中間信号の接続を変更
可能な第2の中間レベル信号接続端子14と、前
記高次群側回路に外部から低次群・高次群間の中
間信号を入出力可能な2個の第3の中間レベル信
号接続端子15とを備えた同一構成の基本ブロツ
クを、単独使用するか、2台もしくは4台並列に
並べ、前記中間信号の接続パスの変更と前記高次
群側回路12だけを取替えることにより、多重数
を基本ブロツク単体の場合に較べ、2倍もしくは
4倍に拡張できるようにしたことを特徴とする多
重変換方式。
1. A low-order group side circuit 11 that transmits and receives low-order group input/output signals 21, 31, 41, and 51, an interface processing section 23, multiple processing sections 33, 43, separation processing sections 35, 45, and a pass-through connection circuit 46 , 53, and transmits and receives high-order group input/output signals 24, 34, and 44.
, an intermediate level signal line 13 that internally connects the low-order group side circuit and the high-order group side circuit, and an intermediate level signal line 13 that is connected to the low-order group side circuit and can change the connection of the intermediate signal between the high-order group side circuit and the high-order group side circuit. connected to the first intermediate level signal connection terminal 14 and the higher-order group side circuit,
A second intermediate level signal connection terminal 14 that can change the connection of intermediate signals with the low-order group side circuit, and an intermediate signal between the low-order group and the high-order group can be input/output from the outside to the high-order group side circuit. A basic block having the same configuration and two third intermediate level signal connection terminals 15 can be used alone, or two or four units can be arranged in parallel to change the connection path of the intermediate signal and the higher-order group side circuit. This multiplex conversion method is characterized in that by replacing only 12 blocks, the number of multiplexes can be doubled or quadrupled compared to the case of a single basic block.
JP61168117A 1986-07-18 1986-07-18 Multiplexer system Granted JPS6326047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61168117A JPS6326047A (en) 1986-07-18 1986-07-18 Multiplexer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61168117A JPS6326047A (en) 1986-07-18 1986-07-18 Multiplexer system

Publications (2)

Publication Number Publication Date
JPS6326047A JPS6326047A (en) 1988-02-03
JPH0583014B2 true JPH0583014B2 (en) 1993-11-24

Family

ID=15862166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61168117A Granted JPS6326047A (en) 1986-07-18 1986-07-18 Multiplexer system

Country Status (1)

Country Link
JP (1) JPS6326047A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2606466B2 (en) * 1991-03-25 1997-05-07 三菱電機株式会社 Air conditioner wind direction control device

Also Published As

Publication number Publication date
JPS6326047A (en) 1988-02-03

Similar Documents

Publication Publication Date Title
JPH0583014B2 (en)
JPH02305132A (en) Flexible multiplexer
JPS61184997A (en) Light time switch
JPH06292246A (en) Optical cross connection system
JPS6196893A (en) Compound type light exchange device
EP1346515A2 (en) Ring network being installed as bus network
JP3476664B2 (en) ATM switch
JPS632369B2 (en)
JP2513931B2 (en) Line switching method
JPS59154895A (en) Synchronizing multiplex converter
JPS63207235A (en) Frame aligner circuit
JPH06105911B2 (en) Digital Cross Connect Network
JPS62163431A (en) Optical parallel transmission and reception circuit
JPS6387832A (en) Cross connection system for digital transmission
KR940017470A (en) Hybrid Interconnection Networks with Time Division and Space Division
JP2608733B2 (en) Switching network
SE9600825D0 (en) System, arrangement and method relating to protection in a communications system and a telecommunications system with a protection arrangement
JPS63190439A (en) Digital multiplex converter
JPH04373334A (en) Multiplexer
JPH01140828A (en) Digital multiplex conversion device
JPS62120192A (en) Digital signal distributor
JPH0517760B2 (en)
JPH01106106A (en) Data transfer method for sequencer transferring many data by small number of input/output lines
JPS60214699A (en) Inter-device interface installation system
JPS63209291A (en) Switch device for multi-stage switch frames in communication systems