JPH058516B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a state detection circuit for a FIFO circuit used in semiconductor logic circuits, particularly digital circuits.

Conventional technology Currently, in order to realize the method of outputting accumulated data in the order in which it is input (hereinafter referred to as the FIFO method),
When using shift registers and RAM
(Random Access Memory) may be used. In particular, a circuit that implements the FIFO method (hereinafter referred to as a domino FIFO circuit) consisting of a shift register controlled by a domino method using a shift clock with an analog delay generally has a high-speed shift operation. Widely used in circuits that require FIFO operation.

Conventionally, when detecting empty data areas in this type of domino-type FIFO circuit, it was common to create a signal based on information about the presence or absence of data indicated by control units in appropriate stages from the first stage to the final stage. be.

Figure 3 shows that in a domino-type FIFO circuit consisting of 10 stages, when there are 4 stages of empty data areas,
1 is a connection circuit diagram illustrating an example of a conventional circuit that generates a signal indicating that data can be input at least four times in succession; FIG.

This circuit consists of FIFO 1 at the first stage to FIFO 1 at the final stage.
The input is a domino-type FIFO circuit consisting of 10 and signals Q ₁ to _{Q 4} that become high level when data exists in the first to fourth stages of the FIFO circuit, and the output name is Q ₀ '. D-TYPE with 4-input NOR gate and 2-stage latch circuit with Q ₀ ' as input and system clock φ as clock.
It consists of a flip-flop.

FIG. 4 is a timing chart showing an example of the operation of each connection point in the connection circuit diagram shown in FIG. 3. This timing diagram uses the write signal WR synchronized with the system clock φ to write data to the first stage FIFO and the data empty area for 4 stages when the system clock φ is at high level. This figure shows part of the timing when detection of whether or not is performed alternately and continuously.

A conventional detection circuit for a data empty area in a domino-type FIFO circuit shown in FIG. 3 will be described below with reference to a timing diagram shown in FIG. 4.

If the FIFO circuit has data empty areas of five or more stages, the input data written by the write signal WR at timing T1 will be stored in the first to fourth stages, respectively.
As shown in the timing diagram of the signals Q ₁ to _{Q 4} indicating the presence or absence of data in the FIFO circuit, the signals are propagated from the first stage to the fourth stage. Since the D-TYPE flip-flop circuit is clocked by a signal synchronized with the system clock φ, Q ₀ ', which is the output of the 4-input NOR whose inputs are Q ₁ to Q ₄ , changes from low level to high level again. If the timing is before the end of timing T3, then D
The output E' of the -TYPE flip-flop is at a high level, that is, the information that there is a data empty area of 4 or more stages is output after timing T4.

This is a limitation when reducing the period of the system clock φ. In other words, the conventional data empty area detection circuit in the domino-type FIFO circuit shown in Figure 3 uses four inputs to determine the system clock cycle.
The pulse width cannot be made shorter than the pulse width T _W0 ' during the period when the output Q0' of the NOR gate _is at a low level.
In particular, as the number of stages of data empty areas to be detected increases, the pulse width T _W0 ' becomes longer, so it is clear that the restrictions on shortening the period of the system clock φ become more severe. It is possible to shorten the pulse width of the signals Q ₁ to _{Q 4} , but there is a limit to shortening the pulse width of Q ₁ to _{Q 4} , which is generally created by analog delay, while ensuring stable operation.

Problems to be Solved by the Invention As can be seen from the above explanation, in the conventional data empty area detection circuit, the period of the system clock is set to the pulse during the period when the output Q ₀ ' of the 4-input NOR gate is at a low level. Since the width cannot be made shorter than the width T _WO ', there is a drawback that high-speed writing cannot be performed. In particular, as the number of stages of data empty areas to be detected increases, the pulse width T _WO ' becomes longer, so the restrictions become tighter.

In order to eliminate this drawback, it is conceivable to shorten the pulse width of the signals _Q1 to _Q4 , but there is a limit to ensuring stable operation.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor logic circuit that can be configured with a relatively simple circuit and that can perform faster write operations.

Means for Solving the Problems In the data empty area detection circuit of the FIFO circuit of the present invention which solves the above problems, data exists in the FIFO circuit from the first stage to the FIFO circuit in one stage more than the data empty area to be detected. A combination of a logic circuit that generates a signal indicating that the data is not processed, and a control signal for writing data to the first-stage FIFO circuit, or a control signal for writing data to the first-stage FIFO circuit and any other signal. The signal thus created is used as a clock.
and a latch circuit whose input signal is the output of the logic circuit.

Operation The present invention has a hardware configuration that detects, at the time of data writing, that the number of stages (N+1), which is one stage more than the number of stages N of data empty areas to be detected by the FIFO circuit, is a data empty area.

Each stage outputs a high level signal when data exists, and a low level signal when data does not exist. These signals are (N+1) inputs
Since it is input to a NOR gate, by looking at the output of this NOR gate, it is possible to know whether there are at least N stages of empty areas. The output of the NOR gate is a D-type clocked by the write signal.
Since it is input to a flip-flop, the existence of empty space will continue to be indicated until the next data is written.

Therefore, along with performing data empty space detection,
Continuous high-speed data writing becomes possible.

Example The present invention will be described below with reference to the drawings.

Figure 1 shows the present invention in a domino system consisting of 10 stages.
FIG. 3 is a connection circuit diagram showing an embodiment of the present invention implemented in a four-stage data empty area detection circuit in a FIFO circuit. The circuit of this example is a domino-type FIFO consisting of FIFO 1 at the first stage to FIFO 10 at the final stage.
circuit and a signal that goes high when data exists in the 1st to 5th stages of the FIFO circuit.
5 inputs with inputs Q ₁ to Q ₅ and output name Q ₀
It is composed of a NOR gate and a D-type flip-flop, which is a two-stage latch circuit that uses _Q0 as an input and the write signal WR of the first stage FIFO circuit as a clock.

An example of the operation will be explained using the timing diagram shown in FIG. This timing diagram uses a write signal WR synchronized with the system clock φ to alternately write data and detect whether there is an empty data area for 4 stages when φ is high level. This shows part of the timing when it is executed continuously.

Q ₁ to _{Q 5} are signals that become high level when data exists in the first to fifth stage FIFO circuits, respectively. Therefore, when _Q0 , which is the output of the 5-input NOR circuit that receives _{Q1 to Q5} as inputs, is at a high level, it can be seen that there is no data in at least the first to fifth stage FIFO circuits.

In the circuit of this embodiment, by using the clock of the D-TYPE flip-flop as the write signal WR, the empty area for 5 stages (4 stages plus 1 stage) is cleared before the _Q1 signal goes high level. In order to latch the information that there is, that is, the high level of Q ₀ ,
It can be shown that there are at least four stages of empty areas in the entire FIFO circuit until the next data is written.

In the case of the conventional four-stage empty area detection circuit shown in FIG. 3, the D-TYPE flip-flop circuit uses a signal synchronized with the system clock φ as the clock, so Q ₀ ' shown in FIG. The timing at which the signal becomes high level must be at least before the end of timing T3. On the other hand, in the circuit of the embodiment of the present invention shown in FIG.
Since the TYPE flip-flop circuit uses a signal synchronized with the write signal WR as its clock, the timing at which _Q0 changes from low level to high level again must be at least before the end of timing T5. This indicates that it is possible to continuously write data at high speed to a domino-type FIFO circuit while detecting empty data areas.

FIG. 5 shows that in the circuit according to the embodiment of the present invention shown in FIG. 1, data exists from the 6th stage to the 10th stage of the FIFO circuit, so the data written at timing T1 is stored in the 5th stage. FIG. 4 is a timing diagram showing the timing when In this case timing T5
When further data is written, _Q5 is at high level, so the output _Q0 of the 5-input NOR circuit is at low level after data is written at timing T1. Therefore, the output signal E of the D-TYPE flip-flop shown in FIG. 1 remains at a low level even after timing T5, indicating that the FIFO circuit no longer has an empty area for four stages.

In the above embodiment, the first stage FIFO is used as a clock.
I used the write signal WR to the circuit, but this write signal
A signal created by a combination of WR and any other signal may be used as the clock.

Effects of the Invention As explained above, the domino method of the present invention
The empty area detection circuit of the FIFO circuit detects that if the number of empty area stages to be detected is N (N is a positive integer smaller than the total number of stages of the FIFO circuit), the N+1 stage is an empty area for data. A relatively simple hardware configuration that detects during writing has the effect of enabling continuous operations of high-speed data writing and data empty area detection. Number of empty regions to be detected N
Generally speaking, the larger the value, the longer it takes to detect the empty area, making it impossible to write at high speed.
In the present invention, which has sufficient time to detect the sky area, the effect is even more remarkable.

[Brief explanation of the drawing]

Figure 1 shows the present invention in a domino system consisting of 10 stages.
A connection circuit diagram showing an example of implementation in a four-stage data empty area detection circuit in a FIFO circuit,
Figure 2 is a timing diagram showing an example of the operation of each contact in the circuit shown in Figure 1.
A connection circuit diagram showing an example of a conventional detection circuit for a four-stage data empty area in a domino-type FIFO circuit consisting of stages. Figure 4 is an operation showing the movement of each contact in the circuit shown in Figure 3. A timing diagram showing an example of
FIG. 5 is a timing diagram showing an example of the operation showing the movement of each contact in the circuit shown in FIG. 1 when the data written at timing T1 is stored in the fifth stage FIFO circuit. . Main reference numbers, FIFO1 to FIFO10...Includes domino control section using analog delay
Each of the 1st to 10th stage circuits of the FIFO circuit, φ...
System clock, WR……System clock φ
FIFO circuit write control signal synchronized with Q ₁ to _{Q 5} …
...Signals that indicate the presence of data output from the control units of FIFO1 to FIFO5, respectively, _T1 to _T5 ...
...timing based on φ, Q ₀ ...output of a 5-input NOR circuit with Q ₁ to _{Q 5} as input, Q ₀ '...Q ₁
~ Output of 4-input NOR circuit with Q ₄ as input, T _W0
...Pulse width when Q ₀ is low level, T _W0 ′...
...Pulse width when Q ₀ ' is low level, E...Q ₀
D- with input as input and control signal WR as clock
TYPE flip-flop output, E′...Q ₀ ′ as input, and system clock φ as clock D
−TYPE flip-flop output.

Claims (1)

[Claims] 1 A data empty area detection circuit of a FIFO circuit,
From the first stage, 1 from the data empty area to be detected.
Up to the FIFO circuit with many stages, there is a logic circuit that creates a signal indicating that there is no data, and the first stage FIFO
A signal created by a combination of a control signal for writing data into the circuit or a control signal for writing data into the first-stage FIFO circuit and another signal is used as the clock, and the clock is used to control the logic circuit. 1. A data empty area detection circuit for a FIFO circuit, comprising a latch circuit that takes an output as an input.