JPH0586675B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating gate type semiconductor nonvolatile memory that can reduce current and area.

As shown in FIG. 1, a typical conventional floating gate type semiconductor nonvolatile memory is provided with two diffusion layers, a source 2 and a drain 3, each having a conductivity type different from that of the substrate, on the surface of a semiconductor substrate 1. The structure was such that an insulating film 4 was provided on the surface of the substrate 1 between the drain 3 and the insulating film 4, a floating gate electrode 5 was provided thereon, an insulating film 6 was provided thereon, and a control electrode 7 was provided thereon. By applying the voltage V _CG to the control gate electrode 7, the potential of the floating gate electrode 5 is controlled by capacitive coupling between the control gate electrode 7 and the floating gate electrode 5, and the conductance of the channel 8 at this time is It is a reading method. The conductance of the channel 8 is determined by the voltage V _CG of the control gate electrode and the charge stored in the floating gate electrode 5.
If V _CG is kept constant, the charge is given only by the charge on the floating gate electrode 5. This charge injection method involves applying a voltage V _CG that can form an inversion layer 8 on the substrate surface between the source 2 and drain 3 to the control gate electrode 7, and also applying a voltage V CG to the drain 3 in the opposite direction to the substrate 1. A voltage V _D is applied so that the channel is pinched off, and the electric field near the pinch-off point A accelerates the carrier flowing through the channel 8, and a part of it is injected into the floating gate electrode 5. This is called the channel injection method,
The disadvantage of this method is that the ratio of the current injected to the floating gate electrode to the channel current and the injection efficiency are low. It is impossible to write. Furthermore, with the structure shown in FIG. 1, it is extremely difficult to reduce the area due to problems such as punch-through.

The present invention overcomes the above two drawbacks of conventional nonvolatile memories, and makes it possible to significantly reduce the channel current during writing compared to the conventional method. Furthermore, since the structure of the nonvolatile memory according to the present invention has only one diffusion layer, it requires a small area and can be highly integrated.

Next, embodiments of the present invention will be described in detail based on the drawings. A sectional view of the first embodiment, which is the basic structure of the present invention, is shown in FIG. A diffusion layer 3 of a conductivity type different from the substrate conductivity type is provided on the surface of a semiconductor substrate 1. A first insulating film 4 is formed on the surfaces of the substrate 1 and the diffusion layer 2, and a floating gate electrode 5 and a second insulating film are formed on the surface of the substrate 1 and the diffusion layer 2. membrane 6,
Furthermore, a control gate 7 is provided. Reading is performed based on the amount of carriers generated by Zener breakdown within the channel 9 when a certain constant voltage V _CG is applied to the control gate electrode 7. The amount of carriers generated at this time is determined by the charges confined within the floating gate electrode 5. That is, when the electric field in the channel 9 is weak and the potential difference between the substrate surface and the inside of the substrate is small, and the charges are confined in the floating gate electrode 5,
The amount produced is lower than if they were not confined.

Next, the principle of the writing method will be explained. As mentioned earlier, the control gate electrode 7 and the floating gate electrode 5 are at almost the same potential due to strong capacitance coupling. A voltage V _CG is applied to the control gate electrode 7 such that the surface of the substrate 1 is reversed, and a voltage V CG is applied to the diffusion layer 3 with respect to the substrate 1, which is sufficiently low to the extent that avalanche breakdown does not occur at the junction between the diffusion layer 3 and the substrate 1. direction voltage
Apply _VD . In this state, on the surface of the substrate 1,
A depletion layer (hereinafter collectively referred to as channel 9) is formed by the inversion layer and the back gate.
FIG. 3 shows a potential diagram along line A-A' in FIG. 2 at this time. In Figure 3,
If the electric field of the channel 9 is strong enough to cause the Zener precipitation, the carriers generated by the Zener precipitation are accelerated by the electric field and pass through the potential barrier of the first insulating film 4 while repeating collisions several times, as shown in FIG. It is injected into the floating gate electrode as shown by arrow B. Therefore, in order to strengthen the electric field of the channel 9, it is necessary to increase the substrate concentration. Furthermore, in order to suppress the increase in V _CG caused by this, it is desirable to increase the capacitance per unit area of the first insulating film. In order to achieve these, (1) a diffusion layer is formed adjacent to the diffusion layer over the entire surface of the substrate under the floating gate and has the same conductivity type as the substrate and has a higher concentration than the substrate;

() Increase the concentration near the substrate surface under the floating gate by ion implantation.

() Make the first insulating film 4 thinner.

() A silicon nitride film with a relatively high dielectric constant is selected as the material for the first insulating film 4.

Possible measures include:

The first embodiment of the present invention has a complicated laminated structure, and therefore the manufacturing process is also complicated. Furthermore, two types of power supplies are required: a drain voltage V _D and a control gate electrode voltage V _CG . FIG. 4 shows a sectional view of a second embodiment in which these improvements have been made. In this structure, by increasing the overlapping area of the diffusion layer 2 and the floating gate electrode 5 and making the first insulating film thinner, the capacitive coupling between the diffusion layer 3 and the floating gate electrode is strengthened. The diffusion layer 3 also serves as a control gate,
That is, it is possible for the voltage V _D of the diffusion layer 3 to simultaneously play the role of V _CG . As described above, in the second embodiment, the control gate electrode is not necessary, and the second embodiment does not require the control gate electrode.
In principle, the insulating film may also be omitted. In the case of the second embodiment, the same measures as in the first embodiment (() to ()) are effective in order to strengthen the electric field of the channel 9 and increase the capacitance of the first insulating film 4. It is.

As described above, the semiconductor nonvolatile memory according to the present invention has the following features:
Compared to conventional memory, the writing current is much smaller and the area is smaller than conventional memory, making it one of the most suitable memories for the ever-evolving highly integrated semiconductor non-volatile memories. . Furthermore, compared to the method of causing avalanche breakdown at the junction between the drain and the substrate and injecting some of the hot electrons generated by this avalanche breakdown into the floating gate electrode, avalanche line injection (from above) (When viewed from above, electrons flow along lines). Because it is plane injection, the injection efficiency is better and the insulating film is less likely to deteriorate. Furthermore, since the write current is small, destruction due to heat generation is less likely to occur.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a typical conventional semiconductor nonvolatile memory, FIG. 2 is a sectional view of a first embodiment of the semiconductor nonvolatile memory according to the present invention, and FIG. 3 is a sectional view of the semiconductor nonvolatile memory shown in FIG. A potential diagram showing the principle of the memory, FIG. 4 is a sectional view of a second embodiment according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Source, 3... Drain, diffusion layer of a different conductivity type from the substrate, 4... First insulating film, 5... Floating gate electrode, 6... Second insulating film,
7... Control gate electrode, 8, 9... Channel.

Claims (1)

[Scope of Claims] 1. A first diffusion layer of a second conductivity type different from the first conductivity type provided on the surface portion of the semiconductor substrate of the first conductivity type, and on the surface of the semiconductor substrate and the surface of the diffusion layer. a first insulating film provided on the first insulating film, a floating gate electrode provided on the first insulating film, a second insulating film provided on the floating gate electrode, and a second insulating film provided on the second insulating film. a control gate electrode, and a second diffusion layer having the same first conductivity type as the semiconductor substrate and having a higher concentration than the semiconductor substrate, which is formed on the entire surface of the substrate under the floating gate electrode adjacent to the first diffusion layer. A first voltage is applied to the control electrode to form an inversion layer and a depletion layer on the substrate surface, and the first diffusion layer is applied to the semiconductor substrate at the junction between the first diffusion layer and the semiconductor substrate. By applying a second voltage in the opposite direction that is sufficiently low to not cause avalanche breakdown, the electric field of the depletion layer formed on the entire surface of the second diffusion layer under the floating gate electrode causes the electric field to move from the substrate toward the floating gate electrode. By generating carriers by Zener breakdown in the direction, the potential difference in the depletion layer is made sufficiently large so that the carriers are injected into the floating gate electrode over the potential barrier of the first insulating film. A semiconductor nonvolatile memory characterized by injecting carriers into a gate electrode. 2 consisting of the first insulating film provided on the semiconductor substrate surface and the diffusion layer surface, and the floating gate electrode provided on the first insulating film,
The semiconductor nonvolatile memory according to claim 1, wherein the diffusion layer also serves as the control gate electrode by increasing the capacitance junction between the diffusion layer and the floating gate electrode. . 3. The amount of charge in the floating gate is detected as the amount of carriers generated by the Zener breakdown by applying a third voltage to the control gate electrode. The semiconductor nonvolatile memory according to item 2.