JPH0589042A - Data processing system - Google Patents

Abstract

PURPOSE:To execute a high-speed processing by preventing an influence caused by the malfunction of a low-speed processor at a system provided with both high-speed processor, which is connected to a high-speed serial bus, and low- speed processor connected through a low-speed serial bus to this high-speed processor. CONSTITUTION:A bus controller 1 for serial bus and a high-speed processor 2 are connected to a high-speed serial bus 4. A low-speed processor 3 is connected through a low-speed serial bus 5 to the high-speed processor 2. The bus controller 1 is provided with a bus disconnecting/connecting circuit 11 to output a bus disconnecting/connecting signal through the high-speed serial bus 4 to the high-speed processor 2. The high-speed processor 2 is provided with a low-speed bus disconnecting/connecting means 20 to disconnect/connect the low-speed serial bus. The bus controller 1 outputs identification data for disconnecting/connecting the low-speed serial bus 5 to a data generating circuit 12, and the high-speed processor 2 analyzes the identification data and disconnects/connects the low-speed serial bus by the low-speed bus disconnecting/ connecting means 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system having a low speed serial bus and a high speed serial bus.

[0002]

2. Description of the Related Art A high-speed serial bus 4 in which a bus control device 1 and a plurality of high-speed processing devices 2 capable of processing with a high-speed clock are operated with a high-speed clock is shown in FIG.
Connected to any of the high-speed processing devices 2 via a low-speed serial bus 5 that can operate only with the low-speed clock, and a plurality of high-speed processing devices 2 connected with Recognizes that the output data is valid by the sample signal, the output data is taken in in synchronization with each clock. In order to capture this output data without error, the bus control device 1 uses the low-speed processing device 3
The sample signal and the output data were sent in accordance with the above.

[0003]

In such a conventional example, in order to prevent malfunction of the low-speed processing device, it was necessary to reduce the processing speed of the bus control device in accordance with the low-speed processing device and operate it. Therefore, even if only one low-speed processing device is connected to the low-speed serial bus, the high-speed serial bus needs to operate in accordance with the low-speed serial bus, which slows down the overall processing speed and reduces the processing time. It had the drawback of being long.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a data processing system having means capable of performing high-speed processing while preventing the influence of a malfunction of a low-speed processing device.

[0005]

According to a first aspect of the present invention, a bus control device and a plurality of high-speed processing devices capable of processing with a high-speed clock are connected to a high-speed serial bus operating with a high-speed clock, and processing is possible with a low-speed clock. In a data processing system in which a plurality of low-speed processing devices are connected to any of the high-speed processing devices via a low-speed serial bus capable of operating at a low-speed clock, the bus control device disconnects the low-speed serial bus. The high-speed processing device has a bus disconnection connection circuit for instructing, and the high-speed processing device has low-speed bus disconnection connection means for connecting or disconnecting the low-speed serial bus in response to an instruction from the bus disconnection connection circuit.

A second aspect of the invention is that a bus control device and a plurality of high-speed processing devices capable of processing with a high-speed clock are connected to a high-speed serial bus operating with a high-speed clock, and a plurality of low-speed processing devices capable of processing with a low-speed clock. In a data processing system in which the device is connected to any of the high-speed processing devices via a low-speed serial bus capable of operating only with a low-speed clock, the high-speed processing device takes in output data from the bus control device and outputs the data to the head. Data analysis means for analyzing the identification data attached to and low speed bus connection / disconnection means for connecting or disconnecting the low speed serial bus based on the analysis result of the data analysis means.

[0007]

In the first aspect of the present invention, when the bus connection disconnection signal is set to "1", the low speed bus disconnection connecting means of the high speed processing device disconnects the high speed serial bus and the low speed serial bus, and the high speed processing device is operated by the high speed clock. .. When the bus connection disconnection signal is set to "0", the high speed serial bus and the low speed serial bus are connected by the low speed bus disconnection connecting means of the high speed processing device, and the low speed processing device is operated by the low speed clock.

In the second invention, the data analysis means of the high speed processing device judges that the request is for the high speed processing device when the identification data attached to the head of the output data is "0", and the low speed bus is used. The disconnection connecting means is instructed to disconnect the high speed serial bus and the low speed serial bus, and the high speed processing device is operated by the high speed clock. Further, when the identification data attached to the head of the output data is "1", it is determined that the request is for the low-speed processing device, and the low-speed bus disconnection connection means is instructed to switch between the high-speed serial bus and the low-speed serial bus. Connect and operate the low speed processor with a low speed clock.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In this first embodiment, as shown in FIG. 1, a bus control device 1 and a plurality of high-speed processing devices 2 capable of processing with a high-speed clock are connected to a high-speed serial bus 4 which operates with a high-speed clock. A plurality of low-speed processing devices 3 that can process with a low-speed clock are connected to any of the high-speed processing devices 2 via a low-speed serial bus 5 that can operate with a low-speed clock. A sample signal generation circuit 13 that generates a plurality of sample signals that can be operated by the processing device 3, a reset control circuit 14 that initializes the high-speed serial bus 4, and a high-speed serial bus 4.
The bus control device 1 has a data generation circuit 12 for sending data to the computer and a data analysis circuit 10 for receiving data from the high-speed serial bus 4 and analyzing the data. Further, as a feature of the present invention, the bus controller 1 Is a low-speed serial bus 5
Has a bus disconnection connection circuit 11 for instructing connection disconnection and a sample signal selection circuit 15 for selecting the output of the sample signal generation circuit 13 and sending it to the high-speed serial bus 4. It has a low speed bus disconnection connection means 20 for connecting or disconnecting the low speed serial bus 5 in response to a command from the circuit 11.

Next, the operation of the first embodiment will be described.
The bus control device 1 outputs the sample signal a, the output data b and the reset signal d for controlling the high speed serial bus 1, and the high speed processing device 2 is connected to the high speed serial bus 4 and The sample signal a, the output data b, and the reset signal d are input to perform controlled processing, and the input data c is output. Further, the bus control device 1 outputs the bus disconnection connection signal e in order to prevent the malfunction of the low-speed processing device 3 when controlling the high-speed processing device 2. The bus disconnection connection signal e is input to the high speed processing device 2, and the low speed bus disconnection connection means 20 disconnects the low speed serial bus 5.

FIG. 3 shows a processing time chart of the bus controller according to the first embodiment. The high-speed clock and the low-speed clock are clocks used by the high-speed processing device 2 and the low-speed processing device 3, respectively, and perform processing in synchronization with this. The output data b, the reset signal d, the bus disconnection connection signal e, and the sample signal a are output from the bus control device 1, and the high speed processing device 2 inputs these signals.

First, the operation of the high speed processing device 2 will be described with reference to FIG. When the reset signal d becomes "1", the high-speed processing device 2 and the low-speed processing device 3 are initialized to prepare for the next transfer. At this time, the bus connection disconnection signal e is set to "1" when the next transfer is to the high-speed processing device 2. The high speed processor 2 receives this signal and disconnects the interface between the high speed serial bus 4 and the low speed serial bus 5. This prevents malfunction of the low-speed processing device 3 separated from the low-speed serial bus, and causes the high-speed processing device 2 to operate with a high-speed clock. On the other hand, when the next transfer is to the low-speed processing device 3, the bus connection disconnection signal is set to "0". In this case, the high speed processing device 2 connects the interfaces of the high speed serial bus 4 and the low speed serial bus 5. At this time, the low-speed processing device 3 is prevented from malfunctioning by operating with the low-speed clock.

FIG. 2 shows the structure of a low-speed processing apparatus according to the second embodiment of the present invention.

In the second embodiment, as shown in FIG. 2, a bus control device 1 and a plurality of high speed processing devices 2 capable of processing with a high speed clock are connected to a high speed serial bus 4 which operates with a high speed clock. A plurality of low-speed processing devices 3 that can process with a low-speed clock are connected to any of the high-speed processing devices 2 via a low-speed serial bus 5 that can operate only with a low-speed clock, and the bus control device 1 is A sample signal generation circuit 13 for generating a plurality of sample signals capable of operating the low-speed processing device 3, and a high-speed serial bus 4.
A reset control circuit 14 for initializing the data, a data generation circuit 12 for sending data to the high-speed serial bus 4, and a data analysis circuit 10 for receiving data from the high-speed serial bus 4 and analyzing the data. As a feature of the present invention, the high speed processing device 2 is a bus control device 1
Data analysis means 21 for capturing output data from the head and analyzing the identification data attached to the head, and low speed bus connection disconnection means 20 for connecting or disconnecting the low speed serial bus 5 based on the analysis result of the data analysis means 21. Have.

Next, the operation of the second embodiment will be described.
The high-speed serial bus 4 does not have a bus disconnection connection signal, and the data analysis means 21 in the high-speed processing device 2 analyzes the output data on the high-speed serial bus 4 to disconnect the low-speed serial bus. The bus controller 1 outputs a sample signal a, output data b, and a reset signal d to control the high speed serial bus 4. The high-speed processing device 2 is connected to the high-speed serial bus 4, receives the sample signal a, the output data b, and the reset signal d for performing processing under the control of the bus control device 1, and outputs the input data c. Further, the high-speed processing device 2 uses the data analysis means 21 to prevent the low-speed processing device 3 from malfunctioning by using the low-speed serial bus 5.
Disconnect. The data analysis means 21 controls disconnection / connection of the low-speed serial bus 5 based on the output data b of the bus control device 1.

FIG. 5 shows a time chart showing the operation of the second embodiment. The high-speed clock, the low-speed clock, the reset signal d, and the sample signal a each perform the same operation as the signal shown in FIG. 4, and only the output data is different from that in FIG. Here, if the first output data is defined as the identification data of the high speed processing device 2 or the low speed processing device 3, the data analysis means 21 can control the disconnection / connection of the low speed serial bus 5 by analyzing the 1-bit data. become.
That is, the data analysis unit 21 determines that the request is for the high-speed processing device 2 when the first output data is "0", and disconnects the low-speed serial bus 5. When the first output data is "1", the data analysis means 21 determines that the request is for the low-speed processing device 3 and connects the low-speed serial bus 5. This prevents malfunction of the low-speed processing device.

In the above, a system in which one high-speed processing device and one low-speed processing device are configured for a high-speed serial bus and a low-speed serial bus has been described for the sake of simplicity. It can be realized similarly.

[0019]

As described above, the present invention prevents the low-speed processing device from malfunctioning with respect to the high-speed processing device in operation, so that high-speed processing can be performed. Further, in the second embodiment, since the bus connection disconnection signal is not used on the high speed serial bus, there is an effect that the number of bus signal lines can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a block configuration diagram showing a configuration of a conventional example.

FIG. 4 is a time chart showing the operation of the first embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the second embodiment of the present invention.

[Explanation of symbols]

 1 bus control device 2 high speed processing device 3 low speed processing device 4 high speed serial bus 5 low speed serial bus 10 data analysis circuit 11 bus disconnection connection circuit 12 data generation circuit 13 sample signal generation circuit 14 reset control circuit 15 sample signal selection circuit 20 low speed bus Disconnecting connection means 21 Data analysis means

Claims (2)

[Claims] 1. A bus controller and a plurality of high-speed processing devices capable of processing with a high-speed clock are connected to a high-speed serial bus operating with a high-speed clock, and a plurality of low-speed processing devices capable of processing with a low-speed clock are low-speed clocks. In a data processing system connected to any of the high-speed processing devices via a low-speed serial bus operable in, the bus control device has a bus disconnection connection circuit for instructing disconnection of the low-speed serial bus, The high-speed processing device comprises a low-speed bus disconnection connection means for connecting or disconnecting the low-speed serial bus in response to a command from the bus disconnection connection circuit. 2. A bus controller and a plurality of high-speed processing devices capable of processing with a high-speed clock are connected to a high-speed serial bus operating with a high-speed clock, and a plurality of low-speed processing devices capable of processing with a low-speed clock are low-speed clocks. In a data processing system connected to any of the high-speed processing devices via a low-speed serial bus that can operate only in the above, the high-speed processing device takes in output data from the bus control device and attaches it to its head. A data processing method comprising: a data analysis means for analyzing identification data; and a low speed bus connection / disconnection means for connecting or disconnecting the low speed serial bus based on an analysis result of the data analysis means.