JPH0590220A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device manufacturing method with which a high coating rate can be obtained when wiring and manufacturing work can be done easily. CONSTITUTION:An organic substance layer 3, which can be easily removed relatively by dry etching using oxygen gas, is formed on a layer insulating layer 2. A resist pattern 4 is formed on the organic substance layer 3, and the layer 3 is almost vertically removed by dry etching with oxygen gas having intense anisotropy using the resist pattern 4 as a mask. After the layer insulating layer 2 has been subjected to dry etching preliminarily using the resist pattern 4 and the organic substance layer 3 as a mask, the aperture only of the organic substance layer 3 is mainly enlarged by dry etching using isotropic oxygen gas. A contact hole is formed by etching the layer insulating layer 2 using the resist pattern 4 and the enlarged organic substance layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for improving the film coverage of the wiring when wiring the semiconductor device.

[0002]

2. Description of the Related Art When a wiring is formed in a semiconductor device, the wiring must be connected to a wiring or an element formed thereunder via an insulating layer. In order to make such a connection, it is a general method to make a hole (contact hole) in the insulating layer and coat a wiring material on the hole to make a contact with a wiring or an element.

In recent years, semiconductor devices have been remarkably miniaturized, and both the device itself and the wiring have been miniaturized, and the contact hole diameter has been reduced. However, the thickness of the element or wiring does not change greatly, and the depth (aspect ratio) of the contact hole tends to increase with respect to its diameter. As a problem with such a large aspect ratio contact hole,
Even if the wiring material is deposited after opening the contact hole,
The wiring material does not reach the bottom of the contact hole, or the bottom surface and the surface are interrupted. That is, a decrease in coating rate occurs.

Several proposals have been made to solve such problems. One of them is to fill a contact hole with polysilicon or the like and then perform ion implantation to form a cylindrical conductor layer. However, this method is difficult to reduce the resistance at the connection surface,
In addition, it has drawbacks such as many processes and complexity, and it is still rarely applied.

Another method is to improve the cross-sectional shape of the contact hole to improve the coverage. FIG. 3 shows an example of a conventional method for manufacturing a semiconductor device.

As shown in FIG. 3, an insulating layer 22 is formed on a substrate 21 having an element or wiring. A resist pattern 23 having holes 24 at desired portions is formed on the insulating layer 22 by a photolithography process. The insulating layer 22 is dry-etched from the hole 24 to form a contact hole (FIG. 3A). In this state, the wall of the hole is vertical, so wet etching is performed to smooth the wall of the contact hole. Naturally, the contact hole diameter widens as shown in FIG.

After that, as shown in FIG. 3C, the resist layer 23 is removed.

Finally, as shown in FIG. 3D, wiring material 27 is deposited and patterned to form wiring.

In this method, it is difficult to form a sufficient film due to the step 28 generated during wet etching. In addition, wet etching has a drawback that the size and sectional shape of the bottom surface of the contact cannot be adjusted.

On the other hand, Japanese Patent Laid-Open No. 3-16217 (International Patent Classification H01L 21/3205) discloses a method for improving the film coverage by another method. This method aims to obtain a contact hole shape with good coverage by etching the insulating layer halfway according to the hole diameter of the resist pattern, then expanding the hole diameter of the resist pattern, and then etching the insulating layer. is there.

However, in the case of this method, if the hole diameter of the resist pattern is widened, the resist film thickness itself becomes thin, so that the sectional shape of the hole cannot be changed so much, and the bottom surface of the hole cannot be changed. There was a drawback that the diameter could not be adjusted.

Further, the method disclosed in Japanese Patent Laid-Open No. 3-3227 (International Patent Classification H01L 21/027) similarly improves the contact hole shape by the resist shape. In this method, the hole shape is formed in advance so that the resist cross-sectional shape has a thin peripheral portion, and the hole diameter of the resist naturally expands when the insulating layer is etched.

However, this method also has the drawback that it is difficult to align the patterns during the second exposure because the exposure must be performed twice during the patterning of the resist. Further, it is considered that it is difficult to adjust the hole diameter of the resist due to the double exposure. Further, the shape of the contact hole is determined by the cross-sectional shape of the resist, the etching rate thereof, and the etching rate of the insulating layer, and therefore its adjustment becomes considerably difficult.

Further, in the method disclosed in Japanese Patent Laid-Open No. 19223/1993 (International Patent Classification H01L 21/3205), the composition on the insulating layer side is changed between the upper layer portion and the lower layer portion so that the contact hole is naturally formed. It is intended to be tapered.

In this method, however, the silicon nitride film is used as the insulating film, but the range of application is limited because other materials may be used. In addition, since the characteristics and uniformity of the insulating layer itself are determined by the forming conditions, there is a problem in that there are many cases where the insulating layer cannot be applied.

[0016]

The above-mentioned conventional methods have the following problems. 1. The cross-sectional shape of the etched insulating layer does not have a gentle taper. 2. The diameter of the bottom of the contact hole cannot be controlled accurately. Especially when forming a fine pattern, the adjustment of the hole diameter is important. 3. The method is limited depending on the type and quality of the insulating layer. 4. The process becomes complicated.

An object of the present invention is to solve the above-mentioned conventional problems, and an object thereof is to provide a method of manufacturing a semiconductor device which has a high coverage at the time of wiring and is easy to manufacture.

[0018]

The present invention relates to a step of forming an organic material layer which is relatively easy to be removed by dry etching using oxygen gas on an interlayer insulating layer of a semiconductor device, and a step of forming the organic material layer on the organic material layer. In the process of forming a resist pattern on the, and dry etching of oxygen gas with strong anisotropy,
Mainly by isotropic oxygen gas dry etching, a step of etching and removing the organic material layer substantially vertically using the resist pattern as a mask, a step of preliminary dry etching of the interlayer insulating layer using the resist pattern and the organic material layer as a mask And a step of expanding only the opening of the organic material layer, and a step of etching the interlayer insulating layer using the resist pattern and the expanded organic material layer as a mask to form a contact hole.

[0019]

In the method of the present invention, the diameter of the bottom surface of the contact hole can be adjusted by the resist pattern and the diameter of the surface portion can be adjusted by the spread of the organic material layer, so that the degree of freedom in forming the contact hole is high. Since the hole etching and the etching of the organic material layer after the formation of the resist pattern are all dry etching, the resist pattern formation that can be performed in one batch is completed by one exposure, so the process is simple.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS.

As shown in FIGS. 1 and 2, an insulating layer 2 is formed on the surface of a substrate 1 which requires contact such as an element or wiring. An organic material layer 3 which is relatively easy to be etched by oxygen plasma is uniformly formed thereon. Further, a resist layer 4 is formed thereon (FIG. 1 (a)).

The resist layer 4 is patterned by a normal photolithography process, and a hole 5 in the resist layer is opened at a desired position (FIG. 1 (b)).

Then, using the resist 4 as a mask, the organic material layer 3 thereunder is dry-etched by oxygen plasma to form holes 6. At this time, dry etching enhances anisotropy to form holes vertically (see FIG. 1).
(C)).

Next, the insulating layer 2 is dry-etched through the holes 5 and 6. At this time, stop in the middle of the insulating layer,
A hole 7 having an appropriate depth is formed (FIG. 1 (d)).

In the next step, isotropic oxygen plasma is applied to etch and spread the organic layer 3 (see FIG. 2).
(E)).

After that, the contact hole 9 is formed by dry etching the insulating layer. In the dry etching at this time, an anisotropic edge and an isotropic etching are used in a timely manner to adjust the taper shape and the hole diameter (FIG. 2F). Then, the organic layer 3 and the resist layer 4 are removed (FIG. 2 (g)). After that, a wiring material is deposited and patterned to form the wiring 10 (FIG. 2).
(H)).

Next, a specific embodiment of the present invention will be further described with reference to FIGS. An inter-layer insulating image 2 is formed on the surface of the substrate 1 which requires contacts such as elements or wiring. This interlayer insulating layer 2 is formed by TEO using a low pressure CVD apparatus.
Substrate temperature 400 ° C, pressure 10 Tor using S type gas
Under the conditions of r and output power of 200 W, the BPSG film was 4000
Å Accumulate.

An organic material layer 3 is formed on this, and in this case, a positive resist AZ1350 (Seaplay) is used to spin coat it to a thickness of 3000 Å. Further thereon, as a resist layer 4 for patterning, as a negative resist, for example, OMR-85 (Tokyo Ohka Co., Ltd.) is used.
(Made by) is spin-coated to a thickness of 2000Å (Fig. 1
(A)).

Next, a desired place is patterned on the resist layer by a photolithography process to form an opening 5 (FIG. 1B).

Then, the organic layer 3 is removed from the opening 5 by dry etching using the resist layer 4 as a mask. The dry etching at this time uses oxygen gas,
By performing highly anisotropic RIE (reactive ion etching), vertical holes 6 are formed (FIG. 1C).

After that, the interlayer insulating layer 2 is etched by 1500 Å through the opening 6 using the resist layer 4 and the organic material layer 3 as a mask. This etching is a magnetron RIE
In the apparatus, CHF ₃ system gas is used. The etching at this time is for facilitating the control of the hole diameter later when forming a contact portion to the substrate 1, and the depth can be appropriately changed depending on the hole shape (see FIG. 1).
(D)).

Next, the organic material layer 3 is removed by isotropic etching using oxygen plasma to form the expanded and expanded organic material layer opening 8. At this time, it is possible to widen only the opening (b) of the organic material layer without expanding the opening (a) of the resist layer by selecting a material that is easily etched by oxygen plasma for the organic material layer (FIG. 2).
(E)).

The interlayer insulating layer is etched again to form the opening 9 in the substrate 1 (FIG. 2 (f)).

After that, the organic material layer 3 and the resist layer 4 are removed to form a contact hole having a gentle taper. Opening of this contact hole (c)
Can be adjusted by the opening (b) of the organic layer, and the opening (d) can be adjusted by the opening (a) of the resist layer (FIG. 2 (g)).

Thereafter, a wiring material such as aluminum is deposited,
The wiring 10 connected to the substrate 1 can be formed by performing desired patterning (FIG. 2H).

[0036]

As described above, according to the present invention, since the interlayer insulating layer has a taper, the coverage of the wiring layer can be improved, so that disconnection can be prevented.

Further, since the shape of the contact hole can be arbitrarily adjusted, the reproducibility can be easily coped with even if the material and film thickness of the interlayer insulating layer are changed.

Moreover, since the opening diameter of the contact hole can be adjusted accurately, the miniaturization of the semiconductor device can be coped with.

Further, in performing the process, the exposure for patterning only needs to be performed once, and the subsequent hole processing is all dry etching, so that continuous processing can be performed in one batch if the gas and conditions are changed. Therefore, the number of operations can be reduced and the time can be shortened.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention.

FIG. 3 is a process cross-sectional view showing a method of manufacturing a semiconductor device in an example of a conventional method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Interlayer insulating layer 3 Organic material layer 4 Resist layer 5 Resist layer opening 6 Organic material layer opening 7 Pre-etched hole 8 Expanded organic material layer opening 9 Contact hole 10 Wiring layer

Claims (1)

[Claims] 1. A step of forming an organic material layer on an interlayer insulating layer of a semiconductor device, which is relatively easy to be removed by dry etching using oxygen gas, and a step of forming a resist pattern on the organic material layer. , A step of etching and removing the organic material layer substantially vertically by using the resist pattern as a mask by dry etching with highly anisotropic oxygen gas, and a preliminary dry etching of the interlayer insulating layer by using the resist pattern and the organic material layer as a mask And a step of mainly expanding only the opening of the organic material layer by isotropic oxygen gas dry etching, and etching the interlayer insulating layer using the resist pattern and the expanded organic material layer as a mask to form a contact hole. A method of manufacturing a semiconductor device, which comprises: