JPH06295878A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for fabricating a semiconductor device in which a contact hole can be made easily with high filming rate of wiring material. CONSTITUTION:A contact hole hating substantially vertical wall face is made and then a resist 6 is filled therein. It is then exposed at an exposing amount substantially 80% of proper exposing amount and then the resist 6 is removed while leaving apart thereof. Furthermore, a layer insulation layer 2 on the upper wall face of the contact hole is removed by highly isotropic etching thus enlarging the diameter above the contact hole. Subsequently, the resists 3, 6 are removed thus obtaining a contact hole having a tapered wall face.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact hole when wiring.

[0002]

2. Description of the Related Art When a wiring is formed in a semiconductor device, the wiring is connected to a wiring or an element formed thereunder via an insulating layer. In order to make such a connection, a method is generally used in which a hole (contact hole) is opened in the insulating layer and a wiring material is coated on the hole to make the connection.
In recent years, semiconductor devices have been remarkably miniaturized, and accordingly, the elements and wirings have also been miniaturized. Therefore, it is necessary to reduce the contact hole diameter. However, since there is no large change in the thickness of the element and the wiring, the ratio of the depth to the diameter (aspect ratio) tends to increase. When the wiring material is deposited after forming a contact hole with a large aspect ratio, the wiring material does not reach the bottom of the hole, or it is interrupted between the bottom part and the surface part of the hole, reducing the coverage rate. I often did.

Various methods for solving such problems have been reported, and one of them is a method of filling a contact hole with, for example, polysilicon and then performing ion implantation to form a cylindrical conductor layer. is there. However, with this method, it is difficult to reduce the resistance of the connection surface, and the process is complicated, etc.
It is not applied very often due to many drawbacks.

Another method is to improve the sectional shape of the contact hole. FIG. 3 is an explanatory diagram showing this method. A resist 13 patterned into a desired shape by photolithography is formed on an insulating layer 12 formed on a substrate 11. Dry etching is performed using this resist 13 as a mask to form a contact hole 14 in the insulating layer 12.
Are formed (FIG. 2 (a)). Contact hole in this state
Since the walls of 14 are vertical, wet etching is performed to expand the diameter of the contact holes 14 and make the walls smooth.
At this time, the diameter of the bottom surface of the contact hole 14 is also enlarged (FIG. 2 (b)). Then, after removing the resist 13 (FIG. 2 (c)), the wiring material 16 is deposited and patterned to form wiring (FIG. 2 (d)).

In this method, a sufficient coating cannot be formed due to the step created during the wet etching, and it is very difficult to adjust the diameter and cross-sectional shape of the bottom surface of the contact hole 14 by the wet etching.

Therefore, Japanese Patent Laid-Open No. 3-16217 discloses another method for obtaining a contact hole shape having a high film coverage. In this method, the insulating layer is partially removed according to the hole diameter of the resist pattern, and then the hole diameter of the resist pattern is expanded and etching is performed again to obtain a contact hole shape having a high film coverage. However, in this method, the diameter of the resist pattern is expanded, so that it is necessary to reduce the film thickness of the resist. When a thin resist film is used, the effect as a mask is reduced, so the shape of the contact hole is not improved so much. Moreover, it is difficult to adjust the diameter of the bottom surface of the contact hole.

A method improved on this method is disclosed in JP-A-3-3227.
It is disclosed in the publication. In this method, the peripheral portion of the patterned hole of the resist is thinned in advance, and the hole diameter of the resist is gradually expanded at the stage of etching the insulating layer. However, in order to carry out this method, it is necessary to perform the exposure twice in the step of patterning the resist, and it is very difficult to match the patterns during the second exposure. Further, since the exposure is performed twice, it is difficult to adjust the hole diameter of the resist, and it is very difficult to adjust the contact hole shape determined by the hole diameter of the resist, the sectional shape, the etching rate and the etching rate of the insulating layer.

Further, Japanese Patent Laid-Open No. 3-19223 discloses a method in which the composition of the insulating layer is changed between the upper layer portion and the lower layer portion to naturally form a tapered shape at the time of forming a contact hole. This method uses an insulating material such as silicon nitride, but its application range is limited. Further, since the characteristics and uniformity of the insulating layer itself are determined by the forming conditions, the applicable range is further limited.

[0009]

As described above, according to the conventional method, it is very difficult to form the contact hole shape of the insulating layer obtained by etching into a gentle taper shape and to adjust the diameter of the bottom surface of the contact hole. Met. Moreover, when trying to make up for these problems, it is unavoidable that the process becomes very complicated. The present invention has been made in view of the above circumstances, and the etching is performed while leaving the resist on the bottom surface of the contact hole to expand the diameter of the upper portion of the contact hole, so that the film of the wiring material is held while maintaining the required diameter. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of increasing the rate.

[0010]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a contact hole in an interlayer insulating layer, wherein a first resist is formed on the interlayer insulating layer. A step of applying and patterning, a step of removing a required portion of the interlayer insulating layer by etching with high anisotropy using the first resist as a mask, and a step of filling the removed portion with a second resist, Exposing the second resist with an exposure amount smaller than the proper exposure amount, removing the second resist by developing, leaving a part of the lower part thereof, using the first and second resists as a mask, etc. The method is characterized by including a step of removing an upper portion of the interlayer insulating layer by etching having strong directionality and a step of removing the first and second resists.

[0011]

In the present invention, the diameter of the bottom surface of the contact hole is enlarged by the second etching by etching while leaving the second resist on the bottom portion of the contact hole to expand the diameter of the upper portion of the contact hole. In addition, the diameter of the upper portion can be increased, and the coverage of the wiring material can be increased while maintaining the required diameter in the connection portion. Moreover, since it is not necessary to pattern the resist twice, it is possible to avoid complication of the work.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is an explanatory view showing a method for manufacturing a semiconductor device according to the present invention. First, the interlayer insulating layer 2 is formed on the substrate 1 which requires connection of elements or wiring. The interlayer insulating layer 2 using a TEOS-based gas at low pressure CVD system, temperature 400 ° C., the pressure 10 Torr, the BPSG (B oron P hospho S ilicate G lass) under the conditions of a power of 200W
4000Å Deposit and form. Further, a positive resist AZ1350 (Seaplay), which is an organic substance, is spin-coated on the surface with 3000 Å to form a resist 3 (FIG. 1 (a)).

Next, the resist 3 is subjected to required patterning by photolithography to form the opening 4. The hole diameter of the opening 4 is a (FIG. 1 (b)). Then, in a magnetron RIE (R eactive I on E tching ) device, performs a strong etching anisotropy in the interlayer insulating layer 2 using the resist 3 using and CHF ₃ -based gas mask. By this etching, a contact hole 5 is formed which is opened in a substantially vertical direction to reach the substrate 1. The diameter b of the bottom surface of the contact hole 5 is determined only by the hole diameter a of the resist 3 and the conversion difference at the time of etching. The hole diameter b can be easily adjusted (Fig. 1 (c)).

After that, the positive resist A is again formed on the entire surface of the wafer.
Z1350 (Seaplay) is spin-coated with 3000Å to make resist 6. Here, it is easy to fill the bottom of the contact hole 5 with the resist 6 (FIG. 1 (d)). Then, the focus is set on the substrate 1 at an exposure amount of 80% of an appropriate exposure amount (the exposure amount capable of forming a pattern with a mask of 1: 1).
When the entire surface of the resist 6 is exposed at a position of 0.3 μm above (FIG. 2 (e)) and development is performed, the resist 6 remains only on the bottom surface of the contact hole 5 due to insufficient exposure. This is baked to cure the resist 6 (FIG. 2 (f)).

Then, the interlayer insulating layer 2 is further formed by the RIE apparatus.
Then, etching with high isotropicity is performed to expand the diameter of the upper portion of the contact hole 5 (the diameter c at the uppermost portion). At this time the resist 6
Due to the existence of the above, the diameter b of the bottom surface of the contact hole 5 is not affected (FIG. 2 (g)). Finally, the resist 3 and the resist 6 left on the bottom surface of the contact hole 5 are removed to obtain a contact hole 5 having a gently tapered shape with a bottom surface diameter b and a top diameter c. Two
(h)).

[0016]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the required diameter is increased by expanding the diameter of the upper portion of the contact hole by etching while leaving the second resist on the bottom portion of the contact hole. Since it is easy to increase the film coverage of the wiring material while maintaining the same, the connection state of the wiring is improved and the device characteristics are improved, and the present invention has excellent effects.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is an explanatory view showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is an explanatory diagram showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 substrate 2 interlayer insulating layer 3,6 resist 4 opening 5 contact hole

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, comprising a step of forming a contact hole in an interlayer insulating layer, a step of applying a first resist on the interlayer insulating layer and performing patterning, and a step of masking the first resist. As a step of removing a required portion of the interlayer insulating layer by etching having a strong anisotropy, a step of filling the removed portion with a second resist, and an exposure of the second resist with an exposure amount smaller than an appropriate exposure amount. And a step of removing the second resist leaving a part of the lower part thereof by development, and an upper part of the interlayer insulating layer is removed by highly isotropic etching using the first and second resists as a mask. A method of manufacturing a semiconductor device, comprising: a step; and a step of removing the first and second resists.