JPH0590421A - Method of manufacturing semiconductor device for forming multilayer wiring - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To eliminate the contamination of etching in the contact hole and the obstruction of W formation due to the adsorption of moisture in the atmosphere, and to embed the contact hole that maintains good contact with the upper layer wiring. According to the present invention, a refractory metal 8 is used for the uppermost layer of a lower layer wiring composed of multiple wirings or a lower layer wiring composed of a single layer, an amorphous silicon layer 2 is formed on the upper surface thereof, and then an interlayer insulating film 7 is formed. Then, the connection hole 3 is opened in this interlayer insulating film to expose the amorphous silicon at the bottom thereof, and then W of the exposed portion is formed by the amorphous silicon.
A reduction reaction of F ₆ gas is carried out to form a tungsten layer 4 on the bottom portion, and then a reduction reaction of WF ₆ gas is carried out by a reducing gas to further promote deposition 5 of tungsten on the tungsten layer to form a contact hole. Embedding is performed to form a semiconductor device in which the connection hole for multilayer wiring is embedded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel method of manufacturing a semiconductor device for forming a multi-layered wiring, and more particularly, a method of selecting a filling of a connection hole for interconnection in a multi-layered wiring with a tungsten CV.
The present invention relates to improvement of a technique performed using the D method.

[0002]

2. Description of the Related Art In recent years, wiring structures have been formed in multiple layers as the density of semiconductor integrated circuits has increased, and there is a tungsten CVD method as a technique for connecting the wirings.

The tungsten CVD method has a low contact resistance as a buried conductor in the technology of burying a connection hole, and has a physical expansion coefficient equivalent to that of silicon for preventing hillock generation. Moreover, it is used for reasons such as electromigration effect related to step coverage and low temperature process compatibility due to formation of shallow diffusion layer (shallow junction). This method further employs a selective tungsten CVD method that does not require an etch bag and mask alignment for that purpose and is effective for filling a substantially equal hole depth.

The selective tungsten CVD method utilizes a reduction reaction of a substance which reacts specifically (selectively) with WF ₆ (tungsten hexachloride) gas in a portion where tungsten is to be deposited. For example, Solid State Tech
nology (November 1986, pp. 117-126), tungsten C was added to the contact hole formed in the oxide film on the silicon substrate.
An example of carrying out the VD method is shown as follows.

First, the reaction (1): 2WF ₆ (g) + 3Si (s) → 2W (s) + 3SiF ₄ (g) is carried out at a temperature of about 300 ° C. and a pressure of 1 Torr or less, and 100Å
The thickness of the tungsten layer, which has reached the self-limiting limit, shows good adhesion and low contact resistance.

Then, the reaction (2): WF ₆ (g) + 3H ₂ (g) → W (s) + 6HF (g) is carried out at the same temperature and pressure, and tungsten is reacted (1).
It proceeds at a slower speed and has no particular formation limit.

The selectivity of this reaction (2) is attributed to the fact that the reducing gas H ₂ is dissociated by the catalytic action of pure and uncontaminated tungsten. It is stated that the formation limit and rate of reaction (1) and the rate of reaction (2) are controlled by temperature and pressure.

Further, Japanese Patent Laid-Open No. 64-55861 discloses that a tungsten layer is formed at the contact with the diffusion region by utilizing the reactions (1) and (2).

The above-mentioned selective tungsten CVD method is formed on the silicon diffusion region as the lower layer. However, not only for multilayer wiring but also for general wiring materials, alloys such as Al or AlSi are used because of their electrical conductivity and ease of handling. Is used, and various barrier materials are used for connection with the diffusion region, and these are often used as the lower layer substance (base).

When the substrate is Al or an alloy with Al, unlike the above reaction (1), reaction (3): 2Al (s) + WF ₆ (g) → 2Al F ₃ (s) + W (g) The problem is that F ₃ is formed at the interface between Al and W, which becomes a large resistance and also acts as a barrier of the reaction itself.

As a countermeasure against this, it has been attempted to provide a metal or a silicide on the upper layer of Al, which is also related to the hillock suppression of Al and the formation of an antireflection layer, but there are the following problems.

That is, when the underlayer is a tungsten W other than Al, molybdenum Mo, and their refractory metals such as silicide, titanium Ti, titanium nitride Ti N, and titanium tungsten, the same as in the above reaction (2). However, these metals are not pure W formed in the reaction (1) as in the case of the reaction (2). Due to the influence, there is a problem that uniform (smooth surface) W cannot be obtained and it is difficult to obtain good contact with the upper layer wiring.

In the case of the above reaction (1), of course, although silicon has the same contamination and adsorption as above, the silicon itself is consumed for the reduction of the WF ₆ gas and W is produced instead. Is ignored and is good.

[0014]

As described above, when the selective tungsten CVD method such as filling the connection holes for the multi-layer wiring is carried out, when the base is Al or its alloy, high resistance and reduction due to Al F ₃ generation are obtained. Even when the underlayer is a refractory metal, the reaction is inhibited, and there is a problem that the W formation is impaired by the contamination of the etching gas and the adsorption of moisture in the atmosphere.

In view of such circumstances, the present invention takes advantage of the unique advantages of the selective tungsten CVD method and adopts a technique that solves the above problems, and a novel method of manufacturing a semiconductor device in which a connection hole for multilayer wiring is buried. Is intended to provide.

[0016]

In order to achieve the above object, the present invention provides an interlayer insulating film by interposing amorphous silicon between an interlayer insulating film and a lower layer wiring in a portion which should be a connection hole for multilayer wiring. When etching a contact hole in the film, protect the lower layer wiring from the external contaminant gas, and cause the upper layer to form pure tungsten by the reaction (1), and the undesired formation of the reaction formula (3). In order to prevent the generation of matter, at least the wiring material immediately below the amorphous silicon is made of a high melting point metal.

To this end, the method of the present invention for forming a multi-layer wiring uses a refractory metal for the uppermost layer of the lower layer wiring composed of multiple wirings or the lower layer wiring composed of a single layer, and forming an amorphous silicon layer on the upper surface thereof. Then, an interlayer insulating film is formed, a connection hole is opened in the interlayer insulating film to expose amorphous silicon at the bottom of the interlayer insulating film, and then WF ₆ gas is reduced by the exposed portion of the amorphous silicon to form a thin film on the bottom. It is characterized in that a tungsten layer is formed, and then a reduction reaction of WF ₆ gas with a reducing gas is carried out to further promote the deposition of tungsten on the tungsten layer to fill the contact hole.

According to an embodiment of the present invention, is a double wire comprising multiple interconnection of a refractory metal and Al or an alloy thereof, and a reducing reaction of WF ₆ gas in accordance with yet amorphous silicon, WF ₆ gas by reducing gas The reduction reaction and the reduction reaction are performed in separate reaction chambers.

[0019]

According to the above structure, selective tungsten CVD
Since amorphous silicon is formed in the lower underground layer where tungsten should be deposited by the method, it is protected by this and the underlying layer is not subjected to gas contamination due to etching at the time of opening the contact hole, and pure tungsten is formed by the reaction (1). .. Further, since the base is a refractory metal that does not directly reduce WF ₆ gas, reaction (3) does not occur. As a result,
The formation of AlF ₃ and the resulting high contact resistance are eliminated, and good electrical continuity is provided to the connection hole for multilayer wiring.

[0020]

Embodiments of the present invention will be described with reference to the drawings.
Figure 1 shows the manufacturing process (a)
FIG. 3 is a cross-sectional view of the semiconductor device according to (d), and FIG. 2 is a plan layout view of a CVD reactor having a reaction chamber divided into two chambers.

FIG. 1 (a) shows an Al alloy (AlS having a thickness of 8000Å).
i) About 1000 Å of amorphous silicon 2 is deposited on the upper surface of the double wiring consisting of the layer 1 and the refractory metal titanium layer 8 having a film thickness of 200 Å by the sputtering method, and the oxide film 7 of about 7,000 Å is further laminated thereon by LPCVD. After that, an etching process is performed to open a connection hole 3 of 7,000 Å × 7,000 Å and the amorphous silicon is exposed at the bottom of the connection hole 3.

The wafer 9 at this stage is subjected to the CVD shown in FIG.
The WF ₆ / Ar gas is fed into the reaction chamber 12 from the load lock chamber 10 of the reactor via the transfer chamber 11, and the reaction (1) is performed at 300 ° C. with the partial pressure of the WF ₆ gas being 1 Torr. First, a tungsten layer 4 at an initial stage is formed on the bottom of the contact hole 3 as shown in FIG. 1 (b). At this time, if the titanium layer 8 does not exist, Al F ₃ is formed in the Al alloy layer 1 by the reaction (3), which is not preferable.

In FIG. 1 (c), the wafer 9 is loaded into the other reaction chamber 13 via the transfer chamber 11, and WF ₆ / H is fed into the reaction chamber 13.
_Two gases are supplied, and the reaction (2) is carried out at H ₂ partial pressure of 1 Torr and 300 ° C. to continue the formation of the tungsten layer 5 on the tungsten layer 4.

Next, as shown in FIG. 1 (d), the upper layer wiring 6 of the same Al alloy as the lower layer wiring is sputtered by 8000
Formed to a thickness of Å.

As described above, the upper and lower wirings were connected by the selective tungsten CVD method.
The electrical conductivity of the 1 alloy-W-Ti-Al alloy was good, and a stable contact resistance characteristic of about 1 ohm was obtained.

When the reaction of the reaction (2) is carried out in the reaction chamber 12 without using the reaction chamber 13, there is a variation in the stability of the electrical conduction state, especially over time, The reproducibility tended to be affected.

When the reactions (1) and (2) are repeated in the same reaction chamber, the reducing gas H ₂ , the reaction by-products SiF ₄ and HF are adsorbed on the inner wall of the reaction chamber, and each reaction is regarded as a reaction. Is due to the influence of foreign outgas. Therefore, it is desirable to carry out the reactions (1) and (2) in separate reaction chambers especially in the case of mass production in which a large number of wafers are processed.

Amorphous silicon on the upper surface of the lower wiring is
It is formed by a processing method such as CVD or PVD, and the thickness of the layer is about 50 to 3000Å, preferably about 1000Å. If the thickness is too thin, the formation of W by the reaction (1) will be insufficient, and it will be difficult to control the subsequent reaction (2) with good uniformity and reproducibility. On the contrary, if it is too thick, the formation of tungsten W at the initial stage reaches the self-limit,
This self-limit is affected by temperature, WF ₆ concentration, pressure and Si surface condition (thickness of natural oxide film, etc.),
The unreacted amorphous silicon remains.
The refractory metal has no particular upper or lower limit in terms of its effect of suppressing the reduction of WF ₆ gas to the reduction by only silicon.

Further, since the selective tungsten CVD method is used for filling the connection hole in the present invention, it is not necessary to provide the amorphous silicon over the entire surface of the lower layer wiring, and the amorphous silicon may be provided in the portion including the connection hole and the vicinity thereof. ..

In the present invention, the selective tungsten CVD method is applied to the filling of the contact hole, but not only in that case, when the by-product obtained when the underlayer reduces the WF ₆ gas becomes an undesirable substance. Alternatively, when a foreign substance (contamination) on the upper surface of the base interferes with the tungsten formation due to the reduction reaction of the WF ₆ gas, it can be applied to any area of the base.

[0031]

According to the present invention, the formation of a non-uniform surface of tungsten due to the contamination of the etching gas or the moisture in the atmosphere that adheres to the upper surface of the underlying wiring is prevented, so that the connection between the upper and lower wirings is made stable. Further, it is possible to eliminate the formation of AlF ₃ and the resulting high contact resistance, and to bury tungsten that provides good electrical conduction in the connection hole for multilayer wiring. As a result, it is possible to eliminate the steps such as HF cleaning for removing the contamination on the upper surface of the lower wiring and controlling it.

The selective tungsten CVD method used in the present invention is performed by using WF using amorphous silicon or a reducing gas.
_{Since 6} gases are reduced in separate reaction chambers, byproducts of other reactions are eliminated and tungsten is deposited, so that stability and reproducibility of the reaction can be easily ensured.

[Brief description of drawings]

1A to 1C are schematic cross-sectional views sequentially showing steps (a) to (c) of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a plan view for explaining the outline of the CVD reaction apparatus according to the present invention.

[Explanation of symbols]

 1 Lower layer wiring 2 Amorphous silicon 3 Connection hole 4 Tungsten layer 5 Tungsten connection line 6 Upper layer wiring 7 Interlayer insulation film 8 Refractory metal 10 Load lock chamber 11 Transfer chamber 12,13 Reaction chamber

Claims (3)

[Reference number] C900 [Claims] 1. Tungsten CV for selecting a connection hole for multilayer wiring
In a method of manufacturing a semiconductor device, in which a multi-layered wiring is formed by embedding by D method and connecting wirings, a refractory metal is used for the uppermost layer of a lower wiring layer of multiple wirings or a lower layer wiring of a single layer An amorphous silicon layer is formed, then an interlayer insulating film is formed, a connection hole is opened in this interlayer insulating film to expose amorphous silicon at the bottom, and then WF ₆ gas is reduced by the exposed amorphous silicon. A reaction is performed to form a tungsten layer on the bottom portion, and then a reduction reaction of WF ₆ gas is performed with a reducing gas to further promote deposition of tungsten on the tungsten layer to fill the connection hole. And a method for manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the multiple wiring is a double wiring made of a refractory metal and Al or an alloy thereof. 3. The semiconductor device according to claim 1, wherein the reduction reaction of WF ₆ gas by amorphous silicon and the reduction reaction of WF ₆ gas by the reducing gas are carried out in separate reaction chambers. Manufacturing method.