JPH0590460A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0590460A JPH0590460A JP3247371A JP24737191A JPH0590460A JP H0590460 A JPH0590460 A JP H0590460A JP 3247371 A JP3247371 A JP 3247371A JP 24737191 A JP24737191 A JP 24737191A JP H0590460 A JPH0590460 A JP H0590460A
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- semiconductor element
- semiconductor device
- insulating substrate
- metal insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/381—Auxiliary members
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】 電力半導体素子の熱ストレスを軽減し、金属
絶縁基板への接合を簡略にする。
【構成】 ヒートスプレッダ12の両面に半田クラッド
技術にて半田材14を圧着し、ヒートスプレッダ12を
金属絶縁基板13上に載置し、ヒートスプレッダ12上
に電力半導体素子11を載置する。これらを加熱工程に
投入し、電力半導体素子11、ヒートスプレッダ12お
よび金属絶縁基板13とを同時に半田付けする。
(57) [Abstract] [Purpose] To reduce the thermal stress of power semiconductor devices and simplify the bonding to metal insulating substrates. [Structure] A solder material 14 is pressure-bonded to both surfaces of the heat spreader 12 by a solder clad technique, the heat spreader 12 is mounted on a metal insulating substrate 13, and the power semiconductor element 11 is mounted on the heat spreader 12. These are put into a heating step, and the power semiconductor element 11, the heat spreader 12, and the metal insulating substrate 13 are soldered at the same time.
Description
【0001】[0001]
【産業上の利用分野】本発明は、電力半導体装置の製造
方法に関し、特に、電力半導体素子と放熱板との接合工
程および放熱板と金属絶縁基板との接合工程に係る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a power semiconductor device, and more particularly to a process for joining a power semiconductor element and a heat sink and a process for joining a heat sink and a metal insulating substrate.
【0002】[0002]
【従来の技術】図3は従来の半導体装置の工程フローチ
ャート、図4は従来の半導体装置の製造方法を示す概略
図、図5は半導体装置の断面図である。2. Description of the Related Art FIG. 3 is a process flow chart of a conventional semiconductor device, FIG. 4 is a schematic view showing a conventional semiconductor device manufacturing method, and FIG. 5 is a sectional view of the semiconductor device.
【0003】従来の樹脂封止型半導体装置の製造方法を
図3に沿つて説明する。A conventional method of manufacturing a resin-sealed semiconductor device will be described with reference to FIG.
【0004】[1]ダイボンド工程において、図4の如
く、Cu材からなるヒートスプレッダ1に、クリーム半
田2(Ag/Su/Pb)3をスクリーン印刷し、その
上にSi材からなる電力半導体素子3をセットする(S
01)。[1] In the die-bonding process, as shown in FIG. 4, a cream solder 2 (Ag / Su / Pb) 3 is screen-printed on a heat spreader 1 made of Cu material, and a power semiconductor element 3 made of Si material is formed thereon. Set (S
01).
【0005】[2]第一リフロー工程において、上記ダ
イボンド済みの各部材を、赤外線加熱式リフロー炉を通
し、半田付け接合を行う(S02)。[2] In the first reflow step, the die-bonded members are passed through an infrared heating type reflow furnace to be soldered and joined (S02).
【0006】[3]部品搭載工程において、金属絶縁基
板4上の電極5にクリーム半田6をスクリーン印刷し、
上記電力半導体素子3をマウントしたヒートスプレッダ
を搭載する(S03)。[3] In the component mounting step, cream solder 6 is screen-printed on the electrode 5 on the metal insulating substrate 4,
A heat spreader on which the power semiconductor element 3 is mounted is mounted (S03).
【0007】[4]第二リフロー工程において、上記ヒ
ートスプレッダ1をマウントした金属絶縁基板4を赤外
線加熱式リフロー炉を通し半田付け接合を行う(S0
4)。[4] In the second reflow step, the metal insulating substrate 4 on which the heat spreader 1 is mounted is soldered and bonded through an infrared heating type reflow furnace (S0).
4).
【0008】[5]清浄工程にて、上記工程通過物の洗
浄を行う。ここで、洗浄が必要となるのは、クリーム半
田2,6はロジン糸のフラツクスを使用しているためで
ある(S05)。[5] In the cleaning step, the material passed through the above steps is washed. Here, the reason why the cleaning is necessary is that the cream solders 2 and 6 use the flux of the rosin thread (S05).
【0009】[6]以後の工程では、図5の如く、ワイ
ヤーボンド工程で、電力半導体素子3と、金属絶縁基板
4上の電極5とを、アルミワイヤー7で配線を行い(S
06)、端子付け工程で、金属絶縁基板4上の電極5
に、タブ端子8をセットし、接合する(S07)。[6] In the subsequent steps, as shown in FIG. 5, the power semiconductor element 3 and the electrode 5 on the metal insulating substrate 4 are wired by the aluminum wire 7 in the wire bonding step (S).
06), the electrode 5 on the metal insulating substrate 4 in the terminal attaching step
Then, the tab terminal 8 is set and joined (S07).
【0010】[7]また、枠付け工程で、外枠ケース9
を金属絶縁基板4と接着し(S08)、その後、電力半
導体素子3および金属絶縁基板4上の電極5を保護する
ためのシリコーンゲル剤10を注入、熱硬化を行い(S
09)、次に半導体装置の内部と外部を遮断するための
エポキシ樹脂11を注入し、熱硬化を行い(S10)、
図5の如く、完成する。その後、検査を行い(S1
1)、出荷に供する(S12)。[7] Also, in the framing process, the outer frame case 9
Is bonded to the metal insulating substrate 4 (S08), and then the silicone gel agent 10 for protecting the power semiconductor element 3 and the electrode 5 on the metal insulating substrate 4 is injected and heat-cured (S8).
09), and then an epoxy resin 11 for isolating the inside and the outside of the semiconductor device is injected and heat curing is performed (S10),
Completed as shown in FIG. After that, an inspection is performed (S1
1) The product is shipped (S12).
【0011】[0011]
【発明が解決しようとする課題】図3の工程フローチャ
ートに示す製造方法において、ヒートスプレッダ1上
に、半田付け接合された電力半導体素子3に、もう一度
リフロー工程を通すため、電力半導体素子3に、熱スト
レスを加えることになる。In the manufacturing method shown in the process flow chart of FIG. 3, the power semiconductor element 3 is soldered and bonded on the heat spreader 1, so that the power semiconductor element 3 is subjected to the heat reflow process again. It will add stress.
【0012】このとき、ヒートスプレッダ材、ハンダ材
および電力半導体素子材の熱膨張係数が各々異なるた
め、電力半導体素子3にひずみが生じ、ときには破壊す
る例もあつて、高品質化、高信頼性の実現が困難であつ
た。At this time, since the heat spreader material, the solder material, and the power semiconductor element material have different thermal expansion coefficients, the power semiconductor element 3 is distorted and sometimes destroyed, which results in high quality and high reliability. It was difficult to realize.
【0013】また、工程も複雑になつており、製造コス
トの低減の障害になつている。Further, the process is complicated, which is an obstacle to the reduction of manufacturing cost.
【0014】本発明は、上記課題に鑑み、電力半導体素
子の熱ストレスを軽減して各部材間の応力を軽減し、か
つ、これらの接合工程を簡素化し得る半導体装置の製造
方法の提供を目的とする。In view of the above problems, the present invention aims to provide a method of manufacturing a semiconductor device which can reduce the thermal stress of a power semiconductor element to reduce the stress between members and simplify the joining process thereof. And
【0015】[0015]
【課題を解決するための手段】本発明による課題解決手
段は、図1,2の如く、電力半導体素子11と、該電力
半導体素子11を冷却する放熱板12と、該放熱板12
を冷却する金属絶縁基板13とを互いに接合する半導体
装置の製造方法において、これらの接合前に、放熱板1
2の両面を半田材14を接合し、片側の半田材14に電
力半導体素子11を、他側の半田材14に金属絶縁基板
13を接触させ、これらを加熱して同時に半田付け接合
することを特徴とするものである。As shown in FIGS. 1 and 2, a means for solving the problems according to the present invention is a power semiconductor element 11, a heat radiating plate 12 for cooling the power semiconductor element 11, and a heat radiating plate 12.
In a method for manufacturing a semiconductor device, in which a metal insulating substrate 13 for cooling a semiconductor is bonded to each other, before the bonding, the heat sink 1
The soldering material 14 is joined to both surfaces of the two, the power semiconductor element 11 is brought into contact with the soldering material 14 on one side, and the metal insulating substrate 13 is brought into contact with the soldering material 14 on the other side, and these are heated and simultaneously soldered and joined. It is a feature.
【0016】[0016]
【作用】上記課題解決手段において、放熱板12の両面
に半田クラッド技術にて半田材14を圧着し、放熱板1
2を金属絶縁基板13上に載置し、放熱板12上に電力
半導体素子11を載置する。これらを加熱工程に投入
し、電力半導体素子11、放熱板12および金属絶縁基
板13とを同時に半田付けする。In the means for solving the above problems, the solder material 14 is pressure-bonded to both surfaces of the heat dissipation plate 12 by the solder clad technique to form the heat dissipation plate 1.
2 is mounted on the metal insulating substrate 13, and the power semiconductor element 11 is mounted on the heat dissipation plate 12. These are put into a heating step, and the power semiconductor element 11, the heat sink 12 and the metal insulating substrate 13 are soldered at the same time.
【0017】[0017]
【実施例】図1は本発明の一実施例を示す半導体装置の
製造方法の動作を示す概略図、図2は同じくその工程フ
ローチャートである。1 is a schematic diagram showing the operation of a method of manufacturing a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a process flow chart thereof.
【0018】図示の如く、本実施例の半導体装置は、電
力半導体素子11と、該電力半導体素子11を冷却する
放熱板12(以下、ヒートスプレッダという)と、該ヒ
ートスプレッダ12を冷却する金属絶縁基板13とが、
半田材14を介して互いに接合されたものである。As shown in the figure, the semiconductor device of this embodiment includes a power semiconductor element 11, a heat radiating plate 12 for cooling the power semiconductor element 11 (hereinafter referred to as a heat spreader), and a metal insulating substrate 13 for cooling the heat spreader 12. And
They are joined to each other via the solder material 14.
【0019】前記電力半導体素子11はSi材、前記ヒ
ートスプレッダ12はCu材、前記半田材14はAg/
Su/Pb材等が夫々使用された従来例と同様のもので
ある。The power semiconductor element 11 is a Si material, the heat spreader 12 is a Cu material, and the solder material 14 is Ag /
This is the same as the conventional example in which the Su / Pb material or the like is used.
【0020】図1中、15は金属絶縁基板13の金属ベ
ース、16は絶縁層、17は銅箔による電極パターンで
ある。In FIG. 1, 15 is a metal base of the metal insulating substrate 13, 16 is an insulating layer, and 17 is an electrode pattern made of copper foil.
【0021】次に、上記半導体装置の製造方法について
図2に沿つて説明する。Next, a method of manufacturing the above semiconductor device will be described with reference to FIG.
【0022】まず、準備段階として、ヒートスプレッダ
12の両面の全領域に、半田材14を、既存のクラッド
技術、ここでは特に冷間圧延圧接法を用いて圧接を行な
う。First, as a preparatory step, the solder material 14 is pressure-welded to the entire regions of both surfaces of the heat spreader 12 by using an existing clad technique, in particular, a cold rolling pressure welding method.
【0023】そして、ダイボンド工程において、両面に
半田材14を被装したヒートスプレッダ12を金属絶縁
基板13上の電極パターン17へ載置する。また、ヒー
トスプレッダ12上へ、電力半導体素子11を載置する
(S21)。Then, in the die bonding process, the heat spreader 12 having the solder material 14 on both sides is placed on the electrode pattern 17 on the metal insulating substrate 13. Further, the power semiconductor element 11 is placed on the heat spreader 12 (S21).
【0024】次に、リフロー工程において、上記の半導
体装置を赤外線加熱式リフロー炉へ通し、半田付け接合
を行う。ただし、半田材14はヒートスプレッダ12の
全領域に形成されているため、リフロー時に半田自体を
フラツクスにて溶かして延ばす必要がなく、故にフラツ
クスが不要となる。そのため、炉中が還元雰囲気に限ら
れ、ここでは従来あつた洗浄工程は省略されている(S
22)。Next, in the reflow step, the above semiconductor device is passed through an infrared heating type reflow furnace and soldering is performed. However, since the solder material 14 is formed in the entire region of the heat spreader 12, it is not necessary to melt and spread the solder itself by the flux at the time of reflow, and thus the flux is unnecessary. Therefore, the inside of the furnace is limited to the reducing atmosphere, and the conventional cleaning process is omitted here (S
22).
【0025】以下は、従来工程と同一で、ワイヤーボン
ド工程で電力半導体素子11と金属絶縁基板13上の電
極パターン17とをアルミワイヤにて結線し(S2
3)、端子付け工程で金属絶縁基板13上の電極17に
タブ端子をセットし接合する(S24)。枠付け工程
で、外枠ケースを金属絶縁基板13に接着し(S2
5)、ゲル注入工程で、電力半導体素子11および金属
絶縁基板13上の電極17を保護するためのシリコーン
ゲル剤を注入、熱硬化を行い(S26)、エポキシ注入
工程で、半導体装置の内部と外部とを遮断するためにエ
ポキシ樹脂9を注入し熱硬化を行い(S27)、半導体
装置は完成する。その後、半導体装置は検査工程を経て
(S28)、出荷される(S29)。The following is the same as the conventional process, and the power semiconductor element 11 and the electrode pattern 17 on the metal insulating substrate 13 are connected by an aluminum wire in the wire bonding process (S2).
3) In the terminal attaching step, tab terminals are set and bonded to the electrodes 17 on the metal insulating substrate 13 (S24). In the framing process, the outer frame case is bonded to the metal insulating substrate 13 (S2
5) In the gel injection step, a silicone gel agent for protecting the power semiconductor element 11 and the electrode 17 on the metal insulating substrate 13 is injected and heat-cured (S26). Epoxy resin 9 is injected to shield the semiconductor device from the outside and heat-cured (S27) to complete the semiconductor device. Then, the semiconductor device goes through an inspection process (S28) and is shipped (S29).
【0026】以上の製造方法により、従来では二工程で
あつたリフロー工程を同時に行うとともに、加熱工程が
一回ですみ、ヒートスプレッダ12の酸化防止および電
力半導体素子11に加わる熱ストレスの低減ができ、電
力半導体素子11自身の信頼性の向上、および電力半導
体装置の品質、性能向上を図り得る。By the above manufacturing method, the reflow process, which has been conventionally two steps, is performed simultaneously, and the heating process is only required once, so that the heat spreader 12 can be prevented from being oxidized and the thermal stress applied to the power semiconductor element 11 can be reduced. The reliability of the power semiconductor element 11 itself can be improved, and the quality and performance of the power semiconductor device can be improved.
【0027】なお、本発明は、上記実施例に限定される
ものではなく、本発明の範囲内で上記実施例に多くの修
正および変更を加え得ることは勿論である。The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.
【0028】[0028]
【発明の効果】以上の説明から明らかな通り、本発明に
よると、従来では二工程あつたリフロー工程を一工程で
すまし、工程の簡素化とコストダウンを同時に行い得
る。As is apparent from the above description, according to the present invention, conventionally, only two reflow steps are required, and the steps can be simplified and the cost can be reduced at the same time.
【0029】また、リフロー工程での加熱回数が減るた
め、電力半導体素子に加わる熱ストレスが低減され、加
熱による素子破壊不良が軽減し、製造歩留が向上し、し
かも、高品質、高信頼性の半導体装置の供給が可能とな
るといつた優れた効果がある。Further, since the number of times of heating in the reflow step is reduced, the thermal stress applied to the power semiconductor element is reduced, the element destruction failure due to heating is reduced, the manufacturing yield is improved, and the quality and reliability are high. If it becomes possible to supply the above semiconductor device, there will be an excellent effect.
【図1】図1は本発明の一実施例を示す半導体装置の製
造方法の動作を示す概略図である。FIG. 1 is a schematic diagram showing an operation of a method of manufacturing a semiconductor device showing an embodiment of the present invention.
【図2】図2は同じくその工程フローチャートである。FIG. 2 is a process flow chart of the same.
【図3】図3は従来の半導体装置の製造方法を示す工程
フローチャートである。FIG. 3 is a process flow chart showing a conventional method for manufacturing a semiconductor device.
【図4】図4は同じくその動作を示す概略図である。FIG. 4 is a schematic view showing the same operation.
【図5】図5は一般的な半導体装置の完成図である。FIG. 5 is a completed view of a general semiconductor device.
11 電力半導体素子 12 放熱板 13 金属絶縁基板 14 半田材 11 power semiconductor element 12 heat sink 13 metal insulating substrate 14 solder material
Claims (1)
冷却する放熱板と、該放熱板を冷却する金属絶縁基板と
を互いに接合する半導体装置の製造方法において、これ
らの接合前に、放熱板の両面に半田材を接合し、片側の
半田材に電力半導体素子を、他側の半田材に金属絶縁基
板を接触させ、これらを加熱して同時に半田付け接合す
ることを特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device in which a power semiconductor element, a heat dissipation plate for cooling the power semiconductor element, and a metal insulating substrate for cooling the heat dissipation plate are bonded to each other, and before the bonding, the heat dissipation plate is provided. Of the semiconductor device, wherein the solder material is joined to both surfaces of the power semiconductor element, the solder material on one side is brought into contact with the metal insulating substrate on the solder material on the other side, and these are heated and soldered at the same time. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3247371A JPH0590460A (en) | 1991-09-26 | 1991-09-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3247371A JPH0590460A (en) | 1991-09-26 | 1991-09-26 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0590460A true JPH0590460A (en) | 1993-04-09 |
Family
ID=17162438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3247371A Pending JPH0590460A (en) | 1991-09-26 | 1991-09-26 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0590460A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000228491A (en) * | 1999-02-09 | 2000-08-15 | Toshiba Corp | Semiconductor module and power converter |
| CN1297046C (en) * | 2003-05-20 | 2007-01-24 | 夏普株式会社 | Semiconductor light emitting device and its manufacturing method |
| KR100727728B1 (en) * | 2006-05-29 | 2007-06-13 | 에스티에스반도체통신 주식회사 | Semiconductor package |
-
1991
- 1991-09-26 JP JP3247371A patent/JPH0590460A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000228491A (en) * | 1999-02-09 | 2000-08-15 | Toshiba Corp | Semiconductor module and power converter |
| CN1297046C (en) * | 2003-05-20 | 2007-01-24 | 夏普株式会社 | Semiconductor light emitting device and its manufacturing method |
| KR100727728B1 (en) * | 2006-05-29 | 2007-06-13 | 에스티에스반도체통신 주식회사 | Semiconductor package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2929273B2 (en) | Ball grid array semiconductor package unit PCB carrier frame and method of manufacturing ball grid array semiconductor package using the same | |
| JPH10303473A (en) | Multi-stage electronic cooling device and its manufacturing method | |
| KR960000706B1 (en) | Plastic package structure for power device and manufacturing method | |
| JPH08191114A (en) | Resin-sealed semiconductor device and manufacturing method thereof | |
| US6064112A (en) | Resin-molded semiconductor device having a lead on chip structure | |
| JPS62202548A (en) | Semiconductor device | |
| JP3705159B2 (en) | Manufacturing method of semiconductor device | |
| JPH01303730A (en) | Mounting structure of semiconductor element and manufacture thereof | |
| JPH0590460A (en) | Method for manufacturing semiconductor device | |
| JP2851779B2 (en) | Electronic component mounting method | |
| JP2798040B2 (en) | Method for manufacturing semiconductor device | |
| JPH09102514A (en) | Bump bonding method and bump bonding structure | |
| JP3233022B2 (en) | Electronic component joining method | |
| JP2986661B2 (en) | Method for manufacturing semiconductor device | |
| JP2975783B2 (en) | Lead frame and semiconductor device | |
| JPH07201894A (en) | Method for manufacturing electronic component mounting device | |
| JPS5943534A (en) | Manufacture of semiconductor device | |
| JPH05144989A (en) | Production of lead frame and method for bonding semiconductor element using the frame | |
| JP2918676B2 (en) | Manufacturing method of stem for hermetic sealing | |
| JPH07147292A (en) | Method for manufacturing semiconductor device | |
| JPS624331A (en) | Wire bonding method | |
| JP2007059712A (en) | Implementation method | |
| JPH0794674A (en) | Semiconductor device and manufacturing method thereof | |
| JPH0513061U (en) | Power semiconductor device | |
| JP3166752B2 (en) | Bare chip mounting system |