JPS624331A - Wire bonding method - Google Patents

Wire bonding method

Info

Publication number
JPS624331A
JPS624331A JP60143662A JP14366285A JPS624331A JP S624331 A JPS624331 A JP S624331A JP 60143662 A JP60143662 A JP 60143662A JP 14366285 A JP14366285 A JP 14366285A JP S624331 A JPS624331 A JP S624331A
Authority
JP
Japan
Prior art keywords
bonding
pad
wire
solder
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60143662A
Other languages
Japanese (ja)
Inventor
Yasuto Saito
康人 斉藤
Masao Segawa
雅雄 瀬川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba Audio Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Audio Video Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP60143662A priority Critical patent/JPS624331A/en
Publication of JPS624331A publication Critical patent/JPS624331A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by welding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • H10W72/01515Forming coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • H10W72/01551Changing the shapes of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07531Techniques
    • H10W72/07532Compression bonding, e.g. thermocompression bonding
    • H10W72/07533Ultrasonic bonding, e.g. thermosonic bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/581Auxiliary members, e.g. flow barriers
    • H10W72/583Reinforcing structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve junction strength by covering the bonding wire junction part on a substrate side with solder. CONSTITUTION:Solder paste is applied to a conductor pad 2 formed on an insulating substrate 1 out of gold, Ag/Pd, copper or the like except a bonding wire junction part. After a semiconductor chip 5 is die-bonded on a die-bonding pad 4, ends of a bonding wire 7, made of solderable metal such as gold, are brought into contact with the bonding pad 6 on the chip 5 and the corresponding conductor pad 2 and contact bonding is carried out by applying heat or ultrasonic wave. Then solder 8 on the pad 2 is heated to melt so as to cover the junction part of the pad 2 and the wire 7.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は導体パッドとボンディングワイヤの接合強度を
向上させたワイヤボンディング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a wire bonding method that improves the bonding strength between a conductor pad and a bonding wire.

[発明の技術的背景] 近年、電子機器の小型、軽量化を図るため混成集積回路
が多用されつつある。この混成集積回路においてICを
実装する方法としては、プラスチックパッケージを用い
た実装方法と、回路基板上に半導体チップをボンディン
グワイヤを用いて実装するワイヤボンディング方法とが
ある。
[Technical Background of the Invention] In recent years, hybrid integrated circuits have been increasingly used to make electronic devices smaller and lighter. Methods for mounting ICs in this hybrid integrated circuit include a mounting method using a plastic package and a wire bonding method in which a semiconductor chip is mounted on a circuit board using bonding wires.

このうちワイヤボンディング方法は従来から以下に示す
ような手順で行なわれている。
Among these methods, the wire bonding method has conventionally been carried out using the following procedure.

すなわち第4図に示すように、絶縁基板1上に金、銀−
パラジウム(A!II /Pd ) 、銅等からなる導
体回路および導体パッド2をそれぞれ形成してなる回路
基板3上のダイボンドパッド4上に、導電性接着剤等を
用いて半導体チップ5を接着した後、この半導体チップ
5上のボンディングパッド6とこれと対応する導体パッ
ド2とをボンディングワイヤ7を用いこれに熱あるいは
超音波を加えて相間の同相拡散を生起することにより、
電気的に接続することが行なわれている。
That is, as shown in FIG. 4, gold and silver are deposited on the insulating substrate 1.
A semiconductor chip 5 is bonded using a conductive adhesive or the like onto a die bond pad 4 on a circuit board 3 formed with a conductor circuit and a conductor pad 2 made of palladium (A!II/Pd), copper, etc., respectively. After that, the bonding pads 6 on the semiconductor chip 5 and the corresponding conductor pads 2 are bonded using the bonding wire 7 and heat or ultrasonic waves are applied thereto to cause in-phase diffusion between the phases.
An electrical connection is being made.

そして、第5r!11に示すように、回路基板3上に半
導体チップ5と共にコンデンサや抵抗のような能動電子
部品8を実装して混成集積回路を製作する。図中符号9
は電子部品7の固定半田、10は封止樹脂である。この
混成集積回路の製造方法は第6図のフローチャートに示
ずように回路基板上の所定の部分に半田ペーストを印刷
塗布し、能動電子部品をマウントしてこれをリフロー半
田付けにより接合した後、ダイボンドパッド上に導電性
接着剤を塗って半導体チップをダイボンドし、次いで前
記ボンディングワイヤを接続してワイヤボンディングを
行なってから最後に半導体チップの外側を封止樹脂で封
止する。
And the 5th r! As shown in 11, active electronic components 8 such as capacitors and resistors are mounted on a circuit board 3 together with a semiconductor chip 5 to produce a hybrid integrated circuit. Code 9 in the figure
1 is a fixed solder for the electronic component 7, and 10 is a sealing resin. The method for manufacturing this hybrid integrated circuit is as shown in the flowchart of FIG. 6. After printing and applying solder paste to a predetermined portion of a circuit board, mounting active electronic components and joining them by reflow soldering, The semiconductor chip is die-bonded by applying a conductive adhesive onto the die-bonding pad, then the bonding wire is connected to perform wire bonding, and finally the outside of the semiconductor chip is sealed with a sealing resin.

[背景技術の問題点] しかしながら従来のワイヤボンディング方法においては
、通常ボンディングワイヤ7として金線が用いられるた
め導体バッド2を金で構成した場合にボンディングの信
頼性は高いがコストが高くなるという欠点があった。
[Problems with the Background Art] However, in conventional wire bonding methods, gold wire is usually used as the bonding wire 7, so if the conductor pad 2 is made of gold, the bonding reliability is high but the cost is high. was there.

また、導体バッド2をAa /Pdあるいは銅等の低価
格の材料で構成した場合には、熱あるいは超音波による
二相間の固相拡散が充分に生起せず、ボンディングワイ
ヤ7の接合強度が低いという問題があった。
Furthermore, when the conductor pad 2 is made of a low-cost material such as Aa/Pd or copper, solid phase diffusion between the two phases due to heat or ultrasonic waves does not occur sufficiently, and the bonding strength of the bonding wire 7 is low. There was a problem.

〔発明の目的] 本発明はこのような問題を解決するためになされたもの
で、材料コストが安くしかもボンディングワイヤの電気
的に接続の信頼性が高いワイヤボンディング方法を提供
することを目的とする。
[Object of the Invention] The present invention was made to solve such problems, and an object of the present invention is to provide a wire bonding method that is low in material cost and has high reliability in electrical connection of bonding wires. .

[発明のII要] すなわち本発明のワイヤボンディング方法は、回路基板
上の所定の位置に半導体チップをダイボンドし、この半
導体チップ上のボンディングパッドと前記回路基板上の
対応する導体バッドとをボンディングワイヤにより電気
的に接続する方法において、前記導体バッドのボンディ
ングワイヤ接合部を除く表面に半田を塗布した模、半田
付は可能なボンディングワイヤの端部を、前記ボンディ
ングパッドおよび導体バッドの接合部上にそれぞれ熱あ
るいは超音波をかけて接合し、しかる後前記半田を加熱
溶融させることにより、導体バッドとボンディングワイ
ヤの接合強度を向上させたものである。
[Summary of the Invention] That is, the wire bonding method of the present invention involves die-bonding a semiconductor chip to a predetermined position on a circuit board, and connecting bonding pads on the semiconductor chip and corresponding conductor pads on the circuit board with bonding wires. In this method, solder is applied to the surface of the conductor pad except for the bonding wire joint, and the end of the bonding wire that can be soldered is placed on the joint of the bonding pad and the conductor pad. The bonding strength between the conductor pad and the bonding wire is improved by applying heat or ultrasonic waves to each, and then heating and melting the solder.

[発明の実施例] 以下本発明を第1vAに示す一実施例について説明する
。、第1図において第4図と共通する部分には同一符号
を付して説明を省略する。
[Embodiment of the Invention] An embodiment of the present invention shown in the first vA will be described below. In FIG. 1, parts common to those in FIG. 4 are designated by the same reference numerals, and their explanations will be omitted.

まず第1図(alに示すように、絶縁基板1上に形成さ
れた金、AQ /Pd 、または銅等からなる導体バッ
ド2上のボンディングワイヤ接合部を除く部分に半田8
ペーストを塗布しておき、ダイボンドバット4上に半導
体チップ5をダイボンドした後、この半導体チップ5上
のボンディングパッド6と対応する導体バッド2とに、
それぞれ金等の半田付は可能な金属からなるボンディン
グワイヤ7の端部を当接させ、これに熱あるいは超音波
をかけて圧着する。
First, as shown in FIG.
After applying the paste and die-bonding the semiconductor chip 5 onto the die-bonding bat 4, the bonding pads 6 on the semiconductor chip 5 and the corresponding conductor pads 2 are bonded.
The end portions of bonding wires 7 made of metals that can be soldered, such as gold, are brought into contact with each other, and heat or ultrasonic waves are applied thereto to compress them.

次いで第1図(b)に示すように、導体バッド2上の半
田8を加熱して溶融させこの半田8で導体バッド2とボ
ンディングワイヤ7との接合部を覆わせる。
Next, as shown in FIG. 1(b), the solder 8 on the conductor pad 2 is heated and melted, and the joint between the conductor pad 2 and the bonding wire 7 is covered with the solder 8.

このように本発明方法によれば、導体バッド2とボンデ
ィングワイヤ7との接合部が半田8で覆われ、この半田
8で接合が補強されるので、導体バッド2の構成材料と
してA!II /Pdや銅を用いた場合でも電気的接続
の信頼性が高い。また第2図に示すように本願発明方法
でワイヤボンディングを行なった場合と、従来からの熱
あるいは超音波のみを用いたボンディング方法を採った
場合の両者の接合強度は強度分布の比較からも明らかな
ように本発明方法が優れている。
As described above, according to the method of the present invention, the joint between the conductor pad 2 and the bonding wire 7 is covered with the solder 8, and the joint is reinforced with the solder 8, so that A! Even when using II/Pd or copper, the electrical connection is highly reliable. Furthermore, as shown in Figure 2, the bonding strength between wire bonding using the method of the present invention and conventional bonding methods using only heat or ultrasonic waves is clear from a comparison of the strength distribution. In this way, the method of the present invention is superior.

また、一般的に熱によりボンディングワイヤ7を圧着さ
せる場合には予め回路基板3を予備加熱することが必要
だが、本発明方法においてはこの加熱温度を150℃以
下の半田8が溶融しない温度に設定し、この加熱に半導
体チップ5以外の能動電子部品の半田付けの際の予備加
熱を兼ねさせることにより、工程の短縮化を図ることが
できる。
Furthermore, in general, when crimping the bonding wire 7 using heat, it is necessary to preheat the circuit board 3 in advance, but in the method of the present invention, this heating temperature is set to a temperature of 150° C. or lower at which the solder 8 does not melt. However, by making this heating also serve as preheating during soldering of active electronic components other than the semiconductor chip 5, the process can be shortened.

実施例の方法により、半導体チップ5を実装すると同時
に回路基板3上に能動電子部品を実装して混成集積回路
を製作するプロセスを第3図に示す。
FIG. 3 shows a process of fabricating a hybrid integrated circuit by mounting the semiconductor chip 5 and simultaneously mounting active electronic components on the circuit board 3 according to the method of the embodiment.

[発明の効果] 以上の説明から明らかなように、本発明のワイヤボンデ
ィング方法によれば、基板側のボンディングワイヤ接合
部を半田で覆うことにより、接合強度を向上させること
ができる。また、混成集積回路の製作においては、余分
の工程を付は加えることなく最も短縮された工程でコン
デンサや抵抗のような能動電子部品を実装することがで
きる。
[Effects of the Invention] As is clear from the above description, according to the wire bonding method of the present invention, bonding strength can be improved by covering the bonding wire bonding portion on the substrate side with solder. Furthermore, in the fabrication of hybrid integrated circuits, active electronic components such as capacitors and resistors can be mounted in the shortest process steps without adding any extra steps.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のワイヤボンディング方法の一実施例を
示す断面図、第2図は本発明のワイヤボンディング方法
と従来からのワイヤボンディング方法によりそれぞれ得
られた接合部の引張強度分布を比較して示すグラフ、第
3図は本発明のワイヤボンディング方法を用いて混成集
積回路の製作を行なう場合のプロセスを示すフローチャ
ート、第4図は従来のワイヤボンディング方法を示す断
面図、第5図は従来のワイヤボンディング方法の断面図
、第6図は従来の混成集積回路製作のプロセスを示すフ
ローチャートである。 1・・・・・・・・・・・・絶縁基板 2・・・・・・・・・・・・導体パッド4・・・・・・
・・・・・・ダイボンドパッド5・・・・・・・・・・
・・半導体チップ7・・・・・・・・・・・・ボンディ
ングワイヤ8・・・・・・・・・・・・半田 出 願 人  株式会社 東芝
FIG. 1 is a cross-sectional view showing an example of the wire bonding method of the present invention, and FIG. 2 is a comparison of the tensile strength distributions of joints obtained by the wire bonding method of the present invention and the conventional wire bonding method. 3 is a flowchart showing the process of manufacturing a hybrid integrated circuit using the wire bonding method of the present invention, FIG. 4 is a cross-sectional view showing the conventional wire bonding method, and FIG. FIG. 6 is a cross-sectional view of the wire bonding method of FIG. 1......Insulating board 2...Conductor pad 4...
・・・・・・Die bond pad 5・・・・・・・・・・・・
...Semiconductor chip 7...Bonding wire 8...Solder applicant Toshiba Corporation

Claims (1)

【特許請求の範囲】[Claims] (1)回路基板上の所定の位置に半導体チップをダイボ
ンドし、この半導体チップ上のボンディングパッドと前
記回路基板上の対応する導体パッドとをボンディングワ
イヤにより電気的に接続する方法において、前記導体パ
ッドのボンディングワイヤ接合部を除く表面に半田を塗
布した後、半田付け可能なボンディングワイヤの端部を
、前記ボンディングパッドおよび導体パッドの接合部上
にそれぞれ熱あるいは超音波をかけて接合し、しかる後
前記半田を加熱溶融させて導体パッドとボンディングワ
イヤを接合して両者の接合強度を向上させたことを特徴
とするワイヤボンディング方法。
(1) In a method in which a semiconductor chip is die-bonded to a predetermined position on a circuit board, and a bonding pad on the semiconductor chip and a corresponding conductor pad on the circuit board are electrically connected by a bonding wire, the conductor pad After applying solder to the surface of the bonding wire except for the joint part thereof, the ends of the solderable bonding wire are bonded by applying heat or ultrasonic waves to the joint part of the bonding pad and the conductor pad, respectively, and then A wire bonding method characterized in that the solder is heated and melted to bond the conductive pad and the bonding wire to improve the bonding strength between the two.
JP60143662A 1985-06-30 1985-06-30 Wire bonding method Pending JPS624331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60143662A JPS624331A (en) 1985-06-30 1985-06-30 Wire bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60143662A JPS624331A (en) 1985-06-30 1985-06-30 Wire bonding method

Publications (1)

Publication Number Publication Date
JPS624331A true JPS624331A (en) 1987-01-10

Family

ID=15344011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60143662A Pending JPS624331A (en) 1985-06-30 1985-06-30 Wire bonding method

Country Status (1)

Country Link
JP (1) JPS624331A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008277825A (en) * 2007-04-26 2008-11-13 Infineon Technologies Ag Chip module and manufacturing method thereof
US20110303341A1 (en) * 2008-12-09 2011-12-15 Thorsten Meiss Method for the miniaturizable contacting of insulated wires
JP2024500580A (en) * 2020-12-28 2024-01-09 チップモア テクノロジー コーポレーション リミテッド Chip packaging structure and chip packaging method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008277825A (en) * 2007-04-26 2008-11-13 Infineon Technologies Ag Chip module and manufacturing method thereof
US20110303341A1 (en) * 2008-12-09 2011-12-15 Thorsten Meiss Method for the miniaturizable contacting of insulated wires
US8418911B2 (en) * 2008-12-09 2013-04-16 Roland Werthschutzky Method for the miniaturizable contacting of insulated wires
JP2024500580A (en) * 2020-12-28 2024-01-09 チップモア テクノロジー コーポレーション リミテッド Chip packaging structure and chip packaging method

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