JPH0595026A - Method of applying voltage to continuous film mounting type semiconductor device - Google Patents

Method of applying voltage to continuous film mounting type semiconductor device

Info

Publication number
JPH0595026A
JPH0595026A JP3255442A JP25544291A JPH0595026A JP H0595026 A JPH0595026 A JP H0595026A JP 3255442 A JP3255442 A JP 3255442A JP 25544291 A JP25544291 A JP 25544291A JP H0595026 A JPH0595026 A JP H0595026A
Authority
JP
Japan
Prior art keywords
voltage
continuous film
semiconductor device
mounting type
applying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3255442A
Other languages
Japanese (ja)
Inventor
Tomoyasu Hirano
伴安 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3255442A priority Critical patent/JPH0595026A/en
Publication of JPH0595026A publication Critical patent/JPH0595026A/en
Pending legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

(57)【要約】 【目的】絶縁性フィルムテープ上に同一金属配線パター
ンを繰り返し設け、同一パターン毎に同一半導体チップ
を実装された連続フィルム実装型半導体装置のバーンイ
ンを行う場合において、低コストでしかも工程の縮小化
をはかることができる電圧印加方法を提供する。 【構成】TABによって製造された連続フィルム実装型
半導体装置の中に、各半導体装置毎に電圧印加用接続端
子4、4’を設ける。外付け接続治具5を電圧印加用接
続端子4、4’間に取り付ける事により、隣接する半導
体チップ1と1’の金属配線パターンが接続される。こ
れを連続フィルム上の全ての端子間に行い、末端の電圧
印加用接続端子7へ電圧印加用電源aを接続する事によ
りフィルム上の全ての半導体チップに電圧印加が行われ
る。この方法により連続フィルム状態にて恒温槽に入れ
る事ができる。
(57) [Abstract] [Purpose] Low cost when performing burn-in of continuous film mounting type semiconductor device in which the same metal wiring pattern is repeatedly provided on the insulating film tape and the same semiconductor chip is mounted for each same pattern. Moreover, the present invention provides a voltage application method capable of reducing the number of steps. [Structure] In a continuous film mounting type semiconductor device manufactured by TAB, connection terminals 4, 4'for voltage application are provided for each semiconductor device. By mounting the external connection jig 5 between the voltage application connection terminals 4 and 4 ′, the metal wiring patterns of the adjacent semiconductor chips 1 and 1 ′ are connected. This is performed between all the terminals on the continuous film, and the voltage is applied to all the semiconductor chips on the film by connecting the voltage applying power supply a to the terminal 7 for applying the voltage. By this method, it can be placed in a constant temperature bath in a continuous film state.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップをTAB
(Tape Automated Bonding)方
式によって、フィルム上に実装した半導体チップのバー
ンインを行う場合に於いて、連続フィルム状態のままで
一ヶ所へ電圧をかける事により同一フィルム上に実装さ
れた全ての半導体チップのバーンインを行うための金属
配線パターンの構造及び、電圧印加方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention
When performing the burn-in of the semiconductor chips mounted on the film by the (Tape Automated Bonding) method, by applying a voltage to one place in the continuous film state, all the semiconductor chips mounted on the same film are The present invention relates to a structure of a metal wiring pattern for performing burn-in and a voltage applying method.

【0002】[0002]

【従来の技術】従来のTAB方式によって、フィルム上
に実装された半導体チップのバーンインを行う場合に
は、単一チップが実装された半導体装置毎にフィルムを
切断し、バーンイン用基板のソケットにセットし、基板
に電圧をかける事によりバーンインを実施していた。
又、場合によっては、一端切断した単一チップが実装さ
れた半導体装置をバーンイン後再び継ぎ合わせ、連続し
たフィルム状態にして出荷している事もあった。
2. Description of the Related Art When a semiconductor chip mounted on a film is burned in by a conventional TAB method, the film is cut for each semiconductor device mounted with a single chip and set in a socket of a burn-in board. Then, burn-in was performed by applying a voltage to the substrate.
In some cases, a semiconductor device mounted with a single chip, which has been cut off at one end, is re-joined after burn-in and shipped in a continuous film state.

【0003】[0003]

【発明が解決しようとする課題】つまり、前述の従来技
術では、バーンイン用ソケット及びバーンインを行うた
めの回路基板を作製しなければならず、又バーンインを
行う為に単一チップが実装された半導体装置毎フィルム
を切断する作業及び、その後再び継ぎ合わせる作業が生
じ、TAB方式によってフィルム上に実装された半導体
チップのバーンインを行う場合の期間、工程の増加及び
コストのアップを余儀なくされてしまう問題点を有して
いる。
That is, in the above-mentioned conventional technique, a burn-in socket and a circuit board for performing burn-in must be manufactured, and a semiconductor in which a single chip is mounted for performing burn-in is required. There is a problem in that the work of cutting the film for each device and the work of rejoining the device thereafter occur, and the period, the process, and the cost are increased when the burn-in of the semiconductor chip mounted on the film by the TAB method is performed. have.

【0004】そこで本発明は、このような問題点を解決
するもので、その目的は低コストにより、そして工程の
縮小化をはかる事を目的とした、連続フィルム実装型半
導体装置への電圧印加方法を提供するところにある。
Therefore, the present invention solves such a problem, and its purpose is to reduce the cost and to reduce the number of steps, and a method for applying a voltage to a continuous film mounting type semiconductor device. Is in the place of providing.

【0005】[0005]

【課題を解決するための手段】本発明の連続フィルム実
装型半導体装置への電圧印加方式は、フィルム上に金属
配線パターンにて電圧印加用接続端子を半導体装置毎に
設置し、外付け接続治具を隣接する半導体装置端子間に
取付ける事により端子間配線の接続を計り、最終的に一
ヶ所へ電圧を印加するのみで、連続フィルム状態にて実
装された全ての半導体チップへの電圧印加を可能にさせ
るものである。
According to the method of applying a voltage to a continuous film mounting type semiconductor device of the present invention, a connection terminal for voltage application is installed on the film by a metal wiring pattern for each semiconductor device, and an external connection fixing device is provided. By connecting the tool between the adjacent semiconductor device terminals, the connection between the terminals is measured, and the voltage is applied to all the semiconductor chips mounted in the continuous film state only by finally applying the voltage to one place. It makes it possible.

【0006】[0006]

【実施例】図1及び図2は、本発明の実施例を説明する
為の要部簡略の図である。図1は、従来のTAB方式に
よって製造された連続フィルム実装型半導体装置の中
に、各半導体装置毎に電圧印加用接続端子を設けた図で
あり、図2は図1の電圧印加用接続端子間に外付け接続
治具を取り付けた状態を表わす図である。1は連続フィ
ルム実装された末端の半導体チップであり、1’は1に
隣接する半導体チップ、2は絶縁性フィルムテープ、3
は電圧印加用接続端子を有する金属配線パターン、4と
4’は隣接する電圧印加用接続端子、5は電圧印加用接
続端子間を接続する外付け接続治具、6はフィルムを巻
き取るリール、7は末端の電圧印加用接続端子である。
ここで、外付け接続治具5を電圧印加用接続端子4、
4’間に取り付ける事により、隣接する半導体チップ1
と1’の金属配線パターンが接続される。、これを連続
フィルム上の全ての端子間に行い、末端の電圧印加用接
続端子7へ電圧印加用電源aを接続する事によりフィル
ム上の全ての半導体チップに電圧印加が行われる。。又
図3は、その電気的配線図を簡略化して書いたものであ
る。この中で5’は電圧印加用接続端子間を接続する外
付け接続治具を表した記号である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 and FIG. 2 are schematic views of the essential parts for explaining an embodiment of the present invention. FIG. 1 is a diagram in which a connection terminal for voltage application is provided for each semiconductor device in a continuous film mounting type semiconductor device manufactured by a conventional TAB method, and FIG. 2 is a connection terminal for voltage application of FIG. It is a figure showing the state which attached the external connection jig between them. Reference numeral 1 is a terminal semiconductor chip mounted on a continuous film, 1'is a semiconductor chip adjacent to 1, 2 is an insulating film tape, 3
Is a metal wiring pattern having connection terminals for voltage application, 4 and 4'are adjacent connection terminals for voltage application, 5 is an external connection jig for connecting the connection terminals for voltage application, 6 is a reel for winding a film, Reference numeral 7 is a terminal for voltage application.
Here, the external connection jig 5 is connected to the voltage application connection terminal 4,
By attaching between 4 ', adjacent semiconductor chips 1
And 1'of the metal wiring pattern are connected. This is performed between all terminals on the continuous film, and the voltage application power source a is connected to the terminal 7 for voltage application at the end so that the voltage is applied to all the semiconductor chips on the film. .. Further, FIG. 3 is a simplified version of the electrical wiring diagram. Among them, 5'is a symbol representing an external connection jig for connecting between the voltage application connection terminals.

【0007】この方法により連続フィルム実装型半導体
装置を巻いた状態にて恒温槽に入れる事ができ、又フィ
ルム上末端の電圧印加用接続端子7に電圧をかけるのみ
で、フィルム上の全ての半導体チップに電圧が印加でき
るので、低コストで簡単にバーンインを実施できる。
By this method, the continuous film mounting type semiconductor device can be put in a thermostatic chamber in a rolled state, and all the semiconductors on the film can be put into the constant temperature bath by simply applying a voltage to the voltage applying connection terminal 7. Since voltage can be applied to the chip, burn-in can be easily performed at low cost.

【0008】[0008]

【発明の効果】以上述べたように、本発明によれば、連
続フィルム実装型半導体装置のバーンインをフイルムを
切断する事なく又、バーンインソケット及びバーンイン
基板の製作をする事なく、バーンインを可能にする事が
できる。このように、本発明の実用的効果は極めて大き
い。
As described above, according to the present invention, the burn-in of the continuous film mounting type semiconductor device can be performed without cutting the film and without manufacturing the burn-in socket and the burn-in substrate. You can do it. Thus, the practical effect of the present invention is extremely large.

【図面の簡単な説明】[Brief description of drawings]

【図1】連続フィルム実装型半導体装置に電圧印加用接
続端子を設けた実施例を示す図である。
FIG. 1 is a diagram showing an example in which a continuous film mounting type semiconductor device is provided with a connection terminal for voltage application.

【図2】図1の図に於て電圧印加用接続端子間を接続す
る外付け接続治具を取付けた実施例を示す図である。
FIG. 2 is a diagram showing an embodiment in which an external connection jig for connecting between the voltage application connection terminals is attached in the view of FIG.

【図3】図2の実施例による電気的配線の簡略図であ
る。
3 is a simplified diagram of electrical wiring according to the embodiment of FIG.

【符号の説明】[Explanation of symbols]

1 −−− 実装された半導体チップ(末端側半導体チ
ップ) 1’−−− 実装された半導体チップ(末端側ICと隣
接する半導体チップ) 2 −−− 同一の金属配線パターンを設けた絶縁性フ
ィルム 3 −−− 電圧印加端子を有する金属配線パターン 4 −−− 接続端子(末端側半導体チップ) 4’−−− 接続端子(末端側半導体チップと隣接する
半導体チップ) 5 −−− 接続治具 5’−−− 接続治具の記号 6 −−− フィルムリール 7 −−− 電圧印加する末端側ICの端子 a −−− 電圧印加用電源記号
1 ----- Mounted semiconductor chip (terminal semiconductor chip) 1 '--- Mounted semiconductor chip (semiconductor chip adjacent to terminal IC) 2 --- Insulating film provided with the same metal wiring pattern 3 --- Metal wiring pattern having voltage application terminal 4 --- Connection terminal (terminal semiconductor chip) 4 '--- Connection terminal (semiconductor chip adjacent to terminal semiconductor chip) 5 --- Connection jig 5 '−−− Symbol of connection jig 6 −−− Film reel 7 −−− Terminal of IC on the terminal side to which voltage is applied a −−− Power supply symbol for voltage application

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁性フィルムテープ上に同一金属配線パ
ターンを繰り返し設け、同一パターン毎に同一半導体チ
ップを実装された連続フィルム実装型半導体装置に於
て、同一金属配線パターンを繰り返し設ける中で、電圧
印加用接続端子を有する事を特徴とする連続フィルム実
装型半導体装置への電圧印加方法。
1. In a continuous film mounting type semiconductor device in which the same metal wiring pattern is repeatedly provided on an insulating film tape, and the same semiconductor chip is mounted for each same pattern, while the same metal wiring pattern is repeatedly provided, A method for applying a voltage to a continuous film-mounted semiconductor device, which has a connection terminal for applying a voltage.
【請求項2】請求項1に記載の電圧印加用接続端子に外
付け接続治具を用いて隣接する半導体チップ間の接続を
行い、一ヶ所へ電圧をかける事により、実装された複数
個の半導体チップへ同時に電圧がかけれる事を特徴とす
る連続フィルム実装型半導体装置への電圧印加方法。
2. The voltage applying connection terminal according to claim 1 is connected between adjacent semiconductor chips by using an external connecting jig, and a voltage is applied to one place to mount a plurality of mounted semiconductor chips. A method for applying a voltage to a continuous film-mounted semiconductor device, which is characterized in that a voltage can be applied simultaneously to a semiconductor chip.
JP3255442A 1991-10-02 1991-10-02 Method of applying voltage to continuous film mounting type semiconductor device Pending JPH0595026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3255442A JPH0595026A (en) 1991-10-02 1991-10-02 Method of applying voltage to continuous film mounting type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3255442A JPH0595026A (en) 1991-10-02 1991-10-02 Method of applying voltage to continuous film mounting type semiconductor device

Publications (1)

Publication Number Publication Date
JPH0595026A true JPH0595026A (en) 1993-04-16

Family

ID=17278830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3255442A Pending JPH0595026A (en) 1991-10-02 1991-10-02 Method of applying voltage to continuous film mounting type semiconductor device

Country Status (1)

Country Link
JP (1) JPH0595026A (en)

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