JPH06109794A - Open detecting circuit for load - Google Patents

Abstract

PURPOSE:To provide a detecting circuit where an input frequency is not limited with a coil, by detecting the load condition of the coil irrespective of the value of the load, though an input frequency range is limited with a load acting on the coil in a conventional load detecting circuit for the read and write IC of a hard disk drive. CONSTITUTION:Transistors Q1 to Q4 with input terminals 2, 3, 7 and 8 connected to the bases thereof are provided, and the collectors of the transistors Q1 and Q3 are connected to a VCC terminal 1. In addition, the emitter of the transistor Q1 is connected to the collector of the transistor Q2. Also, the emitter of the transistor Q3 is connected to the collector of the transistor Q4. In this case, the emitters of the transistors Q2 and Q4 are used in common, and a steady current source 9 is connected to the common connection point thereof. Also, an exclusive OR gate 10 and a set/reset latch 12 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load open detection circuit, and more particularly to a read / write IC L of a hard disk device.
The present invention relates to a load open detection circuit.

[0002]

2. Description of the Related Art A conventional load open detection circuit is shown in FIG. In FIG. 4, the conventional load open detection circuit is
It is provided with NPN transistors Q1 to Q4 connected to the input terminals (1) 2 to (4) 8 as a base. Of these, the collectors of the transistors Q1 and Q3 are connected to the VCC terminal 1, and the emitter of the transistor Q1 is connected to the transistor Q2. Connected to the collector, the emitter of the transistor Q3 is connected to the collector of the transistor Q4, the emitters of the transistors Q2 and Q4 are common, the constant current (I0) source 9 is connected to the intersection of the emitters of the transistors Q2 and Q4, and the transistor Q1 is connected. , Q3 in the H-bridge type L load drive circuit in which the emitters of X terminal 4 and Y terminal 6 are respectively connected, the above-mentioned X terminal 4 is connected to the clamp circuit 14 for applying a clamp when the voltage becomes a certain value or more, With its output, the collector is connected to the VCC terminal 1 and the emitter is the capacitor 15
Connected to the base of an NPN transistor Q7, which is grounded via
A constant current (I1) source 16 is connected to a common connection point with and, the emitter of the transistor Q7 is connected to the inverting input (-) terminal of the comparison circuit 18, and the non-inverting input (+) of the comparison circuit 18 is connected.
The reference voltage VREF17 is connected to the terminal, and the comparison circuit 18
The output of was connected to the output terminal 13.
There is a coil LH and a resistor RH between the X and Y terminals 4 and 6, and a current Iw flows. Inverted input (-) of the comparison circuit 18
The signal, that is, the voltage of the capacitor 15 is VC1. The collector currents of the transistors Q1 and Q4 are IC1 and IC4. The capacitance value of the capacitor 15 is C1.

[0003]

Next, the circuit operation of the prior art will be described with reference to FIGS. 4, 5, and 6. First, the operation of the normal load will be described with reference to FIGS.

Until the input signal is input to the input terminals 2, 3, 7, and 8, the voltage of the condenser 15 is L (low level), and the voltage VC1 of the capacitor 15 and the reference voltage V
The relationship with REF is VC1 <VREF, and the output of the comparison circuit 18 is L, so that the output terminal 1
3 is also L.

Next, at time t1, the input terminals 2 and 8 become H (high level), so that the transistors Q1 and Q are connected.
4 is turned on, and collector currents IC1 and IC4 respectively flow. The relationship between IC1 and IC4 is IC1 = IC4 = I
It becomes 0. Next, at time t2, the input terminal 3 and the input terminal 7
Becomes H, the transistors Q2 and Q3 are turned on and I2 and I3 respectively flow. The relationship between IC2 and IC3 is I
C2 = IC3 = I0. Therefore, the current Iw flowing through the coil LH is as shown in FIG.

At time t0, when the current Iw flows through the coil LH, the counter electromotive voltage VX such as VH is applied to the X terminal 4.
Occurs. The value of this VH is shown by the following equation.

[0007]

In the equation (1), RH = 10Δ, LH = 5μ
If H, Iw ′ = 1 mA and t = 1 ns, then VH = 5.
It becomes 0V.

This VH is input to the clamp circuit 14. This circuit is a clamp circuit for voltages above the set voltage VCL, and its output waveform is similar to the output waveform of the clamp circuit 14. Since the output of the clamp circuit 14 is applied to the base of the transistor Q7, the voltage VC1 of the capacitor 15 becomes VCL 'at time t1.

VCL ′ = VCL−VBEQ7 (2) (VBEQ7: forward-direction voltage drop between base and emitter)
Since VBEQ7 is constant, the amount of change in the voltage VC1 applied to the capacitor 15 is VCL '. When VH starts falling and VH <VCL, VC1> VCL, and the transistor Q7 turns off. The constant current source 16 is connected to VC1 and the time t is expressed by the following equation (3).
To go down.

T = C1 × (VCL′−VREF) / I1 (3) Here, VREF: reference voltage of the comparison circuit 18, I1: constant current value of the constant current source 16.

At time t1, the comparator circuit 17 has VC1> VREF due to VCC, so that the comparator circuit output 18
Output is L. Therefore, the voltage of the output terminal 13 also becomes L.

When an input signal is input to the input terminals 2, 3, 7, and 8, the output voltage of the output terminal 13 changes from H to L, so that the load connected to the X terminal 4 and the Y terminal 6 is increased. Can be judged to be normal.

Next, the operation when the load is open will be described with reference to FIGS. At time t1, the input terminal 2 and the input terminal 8 become H, so that the transistors Q1 and Q4 are
Turns on, but since the load is open, the collector current IC
1 becomes 0. However, the collect current IC4 flows through the transistor Q4 through the transistor Q3. I
The relationship between C4 and I0 is IC4 = I0. Since the load is open, IC1 does not flow, so the current Iw flowing through the coil LH becomes 0, as shown by Iw in FIG.

At time t2, since the input terminals 3 and 7 become H, the transistors Q2 and Q3 are turned on, but IC3 becomes 0 because the load is open and therefore Iw
Also becomes 0. From the above, when the load is open, I
Since the current w does not flow, the counter electromotive voltage VH does not occur even at time t1. Therefore, the base voltage of the transistor Q7 remains L, the voltage is not applied to the capacitor 15, the state of V1 <VREF remains, and the output of the comparison circuit 18 remains H. Therefore, time t1
Even if an input signal is input to input terminals 2, 3, 7, and 8 with,
Since the voltage of the output terminal voltage 13 also remains at L, it can be determined that the load connected to the X terminal 4 and the Y terminal 6 is open.

Next, the drawbacks of the conventional circuit will be described.
In order for the load detection circuit to operate normally, the synchronization T between the input signal of the input terminals 7 and 4 and t shown in the equation (3) is t>
It must be in a T relationship. If this t is small,
Between t0 and t2 in FIG. 5, VCL '<VREF,
At that time, the output of the comparison circuit 18 becomes L, and the output voltage of the output terminal voltage 13 also becomes L, which is the same as the output when the load is open. From time (t), the time t is C
If 1, VREF, I1 are constant values, they are influenced by VCL ', and VCL' is determined by VCL according to the equation (2). VH is a counter electromotive voltage generated in the coil LH, and is represented by the equation (1). Where VH is R
If H, Iw, and t are constant, it is determined by the value of LH.

L of load connected to X terminal 4 and Y terminal 6
When H is changed from 5 μH to 1 μH, the above (1)
From the formula, RH = 10Ω, LH = 1 μH, Iw ′ = 1 m
If A and t = 1 ns, then VH = 1 V.

The clamp voltage VL of the clamp circuit 14 is
If it is set according to VH when LH = 5 μH and VL = 3 V, it is not clamped in the case of LH of 1 μH, so that VCL ′ = VH−VBEQ7. Since VBEQ7 is constant, the amount of change in the voltage applied to the capacitor 15 is VCL '= VH = 1V.

From the above, when t is expressed by the equation (3) when LH = 5 μH and LH = 1 μH, C1 = 10 pF, I1
= 20 μA, VREF = 0.5 V, VCC ′ = 3 V, the following equation is obtained.

T (LH = 5 μH) = C1 × (VCL′−VREF) / I1 = 10 pF × (3V−0.5 V) / 20 μA = 1.25 μs t (LH = 1 μH) = C1 × (VCL′−VREF) ) / I1 = 10 pF × (10−0.5 V) / 20 μA = 0.25 μs In order for the load detection circuit to operate normally, it is necessary that t> T. Therefore, at LH = 5 μH, the input terminals 2, 3, The frequency f of the signal applied to 7 and 8 is f> t (LH = 5 μH)
= 800 kHz or higher, LH = 1μ
In H, it is necessary that f> t (1 μH) = 4 MHz or more. As described above, the conventional circuit has a drawback that the frequency range of the signals input to the input terminals 2, 3, 7, and 8 changes depending on the value of LH.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a load open detection circuit in which the frequency range of a signal input to an input terminal is not changed.

[0022]

According to the present invention, there is provided a load open detection circuit comprising: a first series body of first and second transistors having first and second input terminals connected to respective bases; And a second series body of third and fourth transistors each having a third and a fourth input terminal connected to their bases, and a common connection point of each of the first and second series bodies is defined as X, Y.
In an H-bridge type load open detection circuit serving as a terminal, a base is connected to the base of the first transistor, a collector is connected to the collector via a resistor, and an emitter is connected to the emitter via a resistor. A sixth transistor having a base connected to the base of the fourth transistor, a collector connected to the collector via the third transistor and a resistor, and an emitter connected to the emitter via a resistor, and a fifth transistor A logic gate for inputting a collector and a collector of the sixth transistor, and a set-reset latch in which an output of the logic gate is connected to a reset input and an external signal input is connected to a set input are provided. .

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a load open detection circuit according to an embodiment of the present invention. FIG. 2 is a waveform diagram showing operation waveforms of each part in the circuit of FIG. 1 under normal load. FIG. 3 is a waveform diagram showing operation waveforms of each part when the load is open in the circuit of FIG.

Referring to FIG. 1, this embodiment shows NPN transistors Q5, Q6, an exclusive OR gate 10,
RS type flip-flop (set / reset / latch) 1
2, the point having the R / W terminal 11 and the like is different from the conventional FIG. As two inputs of exclusive OR gate 10,
There are VR1 and VR3, the collector of the transistor Q5,
The resistors R1 and R2 are connected to the emitters, respectively, and the resistors R3 and R4 are connected to the collector and the emitter of the transistor Q6, respectively. The output of the gate 10 is connected to the reset (R) input of the latch 12, and the R / W terminal 11 is connected to the set (S) input.

That is, the load open detection circuit of this embodiment is provided with NPN transistors Q1 to Q4 whose input terminals 2, 3, 7 and 8 are respectively connected to the bases, of which the collectors of the transistors Q1 and Q3 are the VCC terminal 1 respectively. The emitter of the transistor Q1 is connected to the collector of the transistor Q2, the emitter of the transistor Q3 is connected to the collector of the transistor Q4, the emitters of the transistors Q2 and Q4 are made common, and the emitter of the transistor Q2 and the emitter of the transistor Q4 are connected to each other. Connect the current source 9 to the transistor Q
In an H-bridge type L load drive circuit in which the emitters of 1 and Q3 are respectively the X terminal 4 and the Y terminal 6, the base of the transistor Q1 is common and the collector is the resistor R1
To the VCC terminal 1 through the transistor Q and the emitter connected to the emitter of the transistor Q1 through the resistor R2.
5 and the base of the transistor Q4 are common,
The collector is provided with the resistor R3 to the VCC terminal 1, and the emitter is provided with the transistor Q6 connected to the emitter of the transistor Q4 via the resistor R4. The intersections of the transistor Q5 and the resistor R1 and the transistor Q6 and the resistor R3 are respectively exclusive. The input of the OR circuit 10 and the output of the exclusive OR circuit 10 are set / reset latch 1
2 is connected to the reset terminal of the reset circuit, the set terminal is connected to the R / W terminal 11, and the output Q of the set / reset latch 12 is connected to the input terminal 13. Exclusive OR is generally called EX-OR.

As shown in FIG. 2, the R / W terminal 11 is H (high level) until the time t0, and the set / reset latch 12 is set. Therefore, the Q output of the latch 12 is set. Is also H, and the output terminal 13 is also H.

Next, at time t1, when an input signal is applied to the input terminals 2 and 8, the transistors Q1 and Q4 are turned on.
Then, collector currents IC1 and IC4 respectively flow. The relationship of currents is IC1 = IC4 = I0 = Iw.

Next, at time t2, when an input signal is applied to the input terminals 3 and 7, the transistors Q2 and Q3 are turned off.
N, and collector currents IC2 and IC3 respectively flow.
The current relationship is IC2 = IC3 = I0 = -Iw,
Therefore, the current waveform of Iw flowing through the coil LH is as shown in FIG.

At time t1, the transistors Q1 and Q
When collector currents IC1 and IC4 flow in transistor 4, collector currents IC5 and IC6 also flow in transistors Q5 and Q6. The collector currents IC5 and IC6 are expressed by the following equations.

[0030]

However, IS1, IS5, IS4, IS6
Are the base-emitter forward saturation currents of the transistors Q1, Q5, Q4, Q6, respectively. K is the Boltzmann constant, q is the electron charge, and T is the absolute temperature.

Next, the resistance R is changed by the currents IC5 and IC6.
A voltage drop consisting of VR1 and VR3 occurs in 1 and R2.

VR1 = VCC-R1 × IC5 [V] (6) VR3 = VCC-R3 × IC6 [V] (7) where IS1 = IS4, IS5 = IS6, R1 = R
If R3 = 3 and R2 = R4, then VR1 = VR3.

While IC1 and IC4 are flowing, I
Since C5 and IC6 are also flowing, the waveforms of inputs VR1 and VR3 are as shown in FIG. The inputs VR1 and VR3 are input to the exclusive OR gate 10, but since the VR1 and VR3 have the same waveform, the output of the exclusive OR gate 10 remains at L (low) level. Therefore, the set / reset latch 12 is not reset, its output Q remains H, and the output terminal 13 also remains H.

Next, the operation when the load is open will be described with reference to FIGS. R / W terminal 11 is at time t0
Up to H and the set / reset latch 12 is set, so its Q output is also H and the output terminal 13 is also H.

Next, at time t1, when an input signal is applied to the input terminals 2 and 8, the transistors Q1 and Q4 are turned off.
However, since the load is open, IC1 becomes 0. However, IC4 flows through the transistor Q4 through the transistor Q3. The relationship between IC4 and I0 is IC4 = I
It becomes 0. From the equations (4) and (5), the transistor Q
IC6 flows through 6, but transistor Q5 has IC5
Does not flow. Therefore, VR1 and VR3 are (6),
From expression (7), VR1 = VCC, VR3 = VCC-R3
X IC6.

From the above, at the time t1, the input of the exclusive OR gate 10 becomes H and L, so that the output of the exclusive OR gate 10 becomes H. Therefore,
At time t0, since the set / reset latch 12 is reset, its Q output becomes L and the output terminal 13 also becomes L.

As described above, since the output terminal 13 is H when the load is normal and the output terminal 13 is L when the load is open, it can be determined whether the load condition is normal or open.

[0039]

As described above, the load open detection circuit of the present invention detects the load state by detecting the current flowing through the transistors Q1 and Q4, especially by the transistors Q5 and Q6. There is an effect that the input frequencies of the signals applied to the four input terminals can be selected without being affected by the value of LH.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a load open detection circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing operation waveforms of respective parts of FIG. 1 under a normal load.

FIG. 3 is a waveform diagram showing operation waveforms of FIG. 1 when a load is open.

FIG. 4 is a circuit diagram showing a conventional load open detection circuit.

FIG. 5 is a waveform diagram showing operation waveforms of each part of FIG. 4 under a normal load.

FIG. 6 is a waveform diagram showing the operation waveforms of FIG. 4 when the load is open.

[Explanation of symbols]

 Q1 to Q7 NPN transistor LH Load inductance RH Load resistance 1 VCC terminal 2, 3, 7, 8 Input terminal 4, 6 X, Y terminal 9, 16 Constant current source 10 Exclusive OR gate 11 R / W terminal 12 Set reset・ Latch 13 Output terminal 14 Clamp circuit 15 Capacitor 17 Reference voltage 18 Comparison circuit

Claims (2)

[Claims] 1. A first series body of first and second transistors having first and second input terminals connected to respective bases, and a third series body having third and fourth input terminals connected to respective bases. , A second series body of a fourth transistor, and X and Y are common connection points of the first and second series bodies, respectively.
In an H-bridge type load open detection circuit serving as a terminal, a base is connected to the base of the first transistor, a collector is connected to the collector via a resistor, and an emitter is connected to the emitter via a resistor. A sixth transistor having a base connected to the base of the fourth transistor, a collector connected to the collector via the third transistor and a resistor, and an emitter connected to the emitter via a resistor, and a fifth transistor A logic gate for inputting a collector and a collector of the sixth transistor, and a set-reset latch in which an output of the logic gate is connected to a reset input and an external signal input is connected to a set input are provided. Load open detection circuit. 2. The load open detection circuit according to claim 1, wherein the logic gate is an exclusive OR gate.