JPH0773404A - Load open detection circuit - Google Patents

Abstract

PURPOSE:To surely stabilize the value of the terminal voltage by giving an inclination to the rise of the collector current of an NPN transistor TR. CONSTITUTION:First to third constant current sources 3, 20, and 24, first and second NPN TRs 14 and 16, a resistance 15, a PNP TR 17, first and second constant voltage sources 18 and 19, etc., are provided. Before data input, a write head 6 connects the input of a delay circuit 10 to the inverted output of a one shot multivibrator 25, and a capacitor 21 is connected between the base of the NPN TR 14 and the ground terminal for the purpose of giving a time constant to the collector current of the NPN TR 14. The capacitor 21 is connected to a charging current source 20 and a discharging current source 24 by switches 26 and 27 respectively, and the switch 26 is turned on when the inverted terminal voltage of the multivibrator 25 is in the high level, and the switch 26 is turned off when it is in the low level. The switch 27 is turned off when the inverted terminal voltage of the multivibrator 25 is in the high level, and the switch 27 is turned on when it is in the low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load open detection circuit, and more particularly to a load open detection circuit for a hard disk write circuit.

[0002]

2. Description of the Related Art Referring to FIG. 7 showing a conventional circuit of this type, this circuit connects a write head 6 for writing a signal to a magnetic disk and a damping resistor 7 (hereinafter referred to as RD) to both ends of an output terminal. , A write current source 3 that causes a current to flow in the write head 6 bidirectionally according to the logic of the signal at the input terminal 1.
The output terminal of the write circuit 2 to the inverting (-) terminal, the reference voltage 9 connected to the non-inverting (+) terminal, and the output of the comparator 8 to the data (D) terminal. The clock (C) terminal is connected to the delay circuit 10 which delays the signal applied to the input terminal 1 of the writing circuit 2 for a predetermined time and is output, and the reset (R) terminal is connected to the mode switching terminal 13. Delay flip-flop (F /
F) 11 and.

Next, the operation of the conventional circuit will be described with reference to FIGS.

Referring to FIG. 8 which shows the operation waveform of each part of the write head in the normal state, when the level of the mode switching terminal 13 is switched from the H level to the L level at time t0, the mode of the write circuit 2 is switched to the write mode. Instead, the current IW 'of the write current source 3 becomes a write current (hereinafter referred to as IW) in the write head 6, and flows in one direction.

Next, at time t1, the input of the input terminal 1 to the write circuit 2 changes from the H level to the L level, so that the direction of the write current IW flowing through the write head 6 also changes in the opposite direction.

One of the two output terminals of the writing circuit 2 is connected to X.
Assuming that the terminals 4 and the other terminal are the Y terminals 5, the direction in which the write current IW flows at time t1 is from the X terminals 4 to Y to Y.
When changing from the terminal 5 to the X terminal 4, a counter electromotive voltage is generated by the inductance of the write head 6, and the waveform of the X terminal 4 becomes as shown in FIG. When the back electromotive force is VL, VL is expressed by the following equation (1).

[0007]

However, RZ: DC resistance of inductance of the write head 6, RD: value of damping resistance 7, VX
(T0 ′): voltage of X terminal 4 at t0, IW: write current, τ: time constant = LH / (RZ + RD) (LH:
Inductance value of the write head 6).

In the above formula (1), the counter electromotive voltage VL at t = t1 is given by the following formula (2) by substituting t = 0 into the formula (1).

The counter electromotive voltage VL (t1) is V due to the time constant τ.
Ascends to L '. VL 'is shown by the following equation (3).

[0011]

The comparator 8 has an inverting input terminal connected to the X terminal 4
Since the non-inverting input terminal is connected to the reference voltage 9 (hereinafter, the voltage value of the reference voltage is VREF), the counter electromotive voltage VL and the VREF of the reference voltage 9 are VL <VRE from time t1.
During the period of F, the output of the comparator 8 becomes H level.

Next, the delay circuit 10 outputs the signal applied to the input terminal 1 with a certain time delay (delay time is td), and inputs the signal to the clock terminal of the delay flip-flop 11. .

When tH is the time during which the output of the comparator 8 outputs the H level, when td is set so that td> tH, the delay flip-flop 11 supplies the signal applied to the clock terminal. The output Q of the delay flip-flop 11 maintains the L level at the time t3 after the delay time td of the delay circuit 10 from the time t1.
2 also becomes L level.

Next, the operation of the write head 6 when the inductance is open will be described with reference to FIG.

When the level of the mode switching terminal 13 is switched from the H level to the L level at time t0, the mode of the write circuit 2 is switched to the write mode and the write head 6 is set.
The write current IW is about to flow to the write head 6
Since the inductance of is open, write current IW
All flow to the damping resistor 7 (hereinafter RD).

Next, when the input to the write circuit 2 changes from the H level to the L level at time t1, the direction of the write current IW flowing through the damping resistor (RD) also changes from the X terminal to the Y terminal as described above. It changes in reverse from Y terminal to X terminal.

When the write head 6 is normal, a counter electromotive voltage is generated at t1, but no counter electromotive voltage is generated when the inductance is open. Therefore, the voltage VL at the X terminal at time t1 is as shown in the following equation (4). Become.

VL = VX (t0) −RD · IW (4) where VX (t0): X terminal voltage at t0, R0: damping resistance.

Since the write head 6 has an open inductance and has no inductance, the value of the voltage VL at the X terminal 4 is different from the normal value, and the voltage applied to the input terminal 1 changes from the L level to the H level, that is, t1. Up to t4 V
The value of X is constant at VL.

However, t4 is the time when the input signal of the input terminal 1 becomes L level at time t1 and then becomes H level.

Therefore, the reference voltage VREF is changed to VREF <
When it is set to VL, the output of the comparator 8 becomes H level from t1 to t4.

The output of the comparator 8 is input to the data terminal of the delay flip-flop 11, and the clock terminal of the delay flip-flop 11 receives the signal applied to the input terminal 1 delayed by the delay circuit 10 for a predetermined time td. Since the delay flip-flop 11 is applied and operates at the falling edge of this signal, the output Q of the delay flip-flop 11 becomes H level at time t3.

Therefore, the voltage of the output terminal 12 also becomes the H level, and the inductance open state of the write head 6 can be detected.

However, the delay time td of the delay circuit 10 is set to be shorter than the time of the pulse width t4-t1 of the input signal applied to the input terminal 1.

[0026]

The drawbacks of the conventional circuit will be described with reference to FIG.

In FIG. 10, the value VL of the voltage of the X terminal 4 at time t1 is expressed by the equation (2) as described above. This value changes depending on the magnitude of the write current IW,
When IW is large, the counter electromotive voltage VL at the X terminal is small (increases in the negative direction).

Further, in FIG. 10, the counter electromotive voltage VL of the X terminal 4 is as follows depending on the time constant.

[0029]

Although it changes to VL 'shown in the equation (5), the time t2' from when the counter electromotive voltage VL at the X terminal becomes equal to the reference voltage 9 of the comparator 8 is shown by the following equation.

[0031]

Further, VL of the expression (6) changes according to the inductance of the write head 6 (hereinafter referred to as LH) according to the expression (1).

From the above, the value of the time t2 'changes by changing the write current IW or the inductance LH of the write head 6, so that the counter electromotive voltage VX of the X terminal becomes the value VREF of the reference voltage 9 of the comparator 8. For VREF ≧
The time tH during which the comparator 8 outputs the H level until it becomes VX depends on the write current IW or the inductance LH of the write head 6.

The delay circuit 10 is a circuit which delays the input signal applied to the input terminal 1 by a fixed time td and outputs it, and the time td is constant.

Therefore, as described above, the write current IW,
Alternatively, when the value of the inductance LH of the write head 6 becomes large and the time tH during which the output of the comparator 8 outputs the H level becomes tH> td, the data terminal of the delay flip-flop 11 has the data terminal of the comparator 8 at time t3.
H level is input and the Q output becomes H level.

This is the same state as when the inductance of the write head 6 is open, and there is a drawback that the state of the write head 6 cannot be normally grasped.

[0037]

SUMMARY OF THE INVENTION According to the present invention, there is provided a magnetic disk having a first write constant current source, an input terminal and two output terminals, and an inductance load and a resistance connected in parallel between the output terminals. A write circuit, a comparator in which one end of the two outputs is connected to an inverting input terminal and a reference voltage is connected to a non-inverting input terminal, and a delay circuit for delaying a signal applied to the input terminal of the write circuit of the magnetic disk In the load open detection circuit, the output of the comparator is connected to the data terminal, the output of the delay circuit is connected to the clock terminal, the mode switching terminal is connected to the reset terminal, and the output terminal is connected to the Q output. Input the one-shot multi-vibrator that takes as input and the inverted output of this one-shot multi-vibrator. And by providing a delay circuit for input to the clock terminal of the delay flip-flop, the first
The write constant current source is connected to the magnetic disk write circuit via a first switch that is turned on at the H level of the non-inverting output of the one-shot multivibrator and turned off at the L level, and the collector is an inverting input terminal of the comparator. A first transistor connected to the second power supply terminal through a resistor; a collector connected to the first power supply terminal; a base connected to a first constant voltage source; and an emitter connected to the first constant voltage source. A second transistor connected to the base of the first transistor; a collector connected to the second power supply terminal; a base connected to a second constant voltage source; and an emitter connected to the base of the first transistor. And a third transistor having a conductivity type different from those of the first and second transistors, and one end thereof connected to the first power supply terminal,
The other end is turned on at the H level of the output voltage of the inverting terminal of the one-shot multivibrator and turned off at the L level.
A second constant current source connected to the base of the first transistor through a switch, and one end connected to the second power supply terminal and the other end H of the output voltage of the inverting terminal of the one-shot multivibrator. A third constant current source connected to the base of the first transistor through a third switch that obtains a control signal from an output of the one-shot multivibrator via an inverter so as to turn off at a level and turn on at an L level. And a capacitor having one end connected to the base of the first transistor and the other end connected to the second power supply terminal.

[0038]

EXAMPLE An example of the present invention will be described below with reference to FIGS.

1 and 2 showing a circuit of an embodiment of the present invention.
In this embodiment, the same numerals and symbols as those in FIG. 7 indicate the same things.

Arrows A, B and C in FIG. 1 indicate A and B in FIG.
B and C are respectively connected, and by combining FIG. 1 and FIG. 2, an entire load open detection circuit is formed.

In FIGS. 1 and 2, the second embodiment is such that the first, second, and third constant current sources 3, 20, and 24, the first and second NPN transistors 14 and 16, and the resistor 15 are provided. And P
The NP transistor 17, the first and second constant voltage sources 18,
19, a capacitor 21, an inverter 23, a one-shot multivibrator 25, first, second and third switches 30, 26, 27, an input terminal 1, an output terminal 4,5, a write head 6, a damping. The write circuit 2 including the resistor 7, the power supply terminal 28, the ground terminal 29, the comparator 8, the source of the reference voltage (VREF) 9, the delay circuit 10, the delay F / F 11, the output terminal 12, and the mode. And a switching terminal 13.

In order to detect the state of the write head 6 before the data is input, the input of the delay circuit 10 is connected to the inverting output of the one-shot multivibrator 25 as seen in FIGS.

A capacitor 21 is connected between the base of the NPN transistor 14 and the ground terminal so that the collector current of the NPN transistor 14 (hereinafter abbreviated as Icheck) has a time constant.

Further, the capacitor 21 is connected to the charging current source 20 by the switch 26 and to the discharging current source 24 by the switch 27. The switch 26 is turned on when the inverting terminal voltage of the one-shot multivibrator 25 is at H level and turned off when it is at L level.

The switch 27 is turned off when the inverting terminal voltage of the one-shot multivibrator 25 is at H level and is turned on when it is at L level. The control voltage of the switch 27 is the output of the inverter 23.

In order to clamp the base voltage of the NPN transistor 14, the emitter of the NPN transistor 16 having the bias power supply 18 connected to the base and the emitter of the PNP transistor 17 having the bias power supply 19 connected to the base are connected to the NPN transistor. A resistor 15 which is commonly connected to the base of 14 and sets the current value of the write circuit 2 is N
It is connected between the emitter of the PN transistor 14 and the ground terminal.

First, the operation when the write head is normal will be described with reference to FIGS.

The operation waveforms of the respective parts when the write head in the circuits of FIGS. 1 and 2 is normal are shown in FIGS. 3 and 4, and some of the waveforms (VR) are shown in duplicate to clarify the relationship. ing.

At time t0 in FIGS. 3 and 4, when the signal level of the mode switching terminal 13 is switched from the H level to the L level, the inverted output of the one-shot multivibrator 25 becomes the H level and the pulse is output for a certain period of time. .

One-shot multivibrator 25
The write current (hereinafter IW) of the write current source 3 does not flow through the write head 6 after the time t0 due to the switch 30 that is turned on (ON) at the H level and turned off (OFF) at the L level.

Further, one-shot multivibrator 25
The switch 26 receiving the output voltage from the inverting terminal of the switch is turned on because the inverting terminal voltage of the one-shot multivibrator becomes H level. On the contrary, the control voltage of the switch 27, which is receiving the inversion of the output voltage of the inversion terminal of the one-shot multivibrator 25, becomes L level, and is turned off.

Therefore, the current source 20 causes the capacitor 21
Is charged, the base voltage of the NPN transistor 14 rises to a value obtained by adding the voltage VB2 of the bias power supply 19 and the base-emitter voltage VBEQ17 of the PNP transistor 17.

Further, the time t2 "until the rise is completed is set to be shorter than the time t3" until the output of the delay circuit 10 becomes H level.

Further, at this time, the NPN transistor 16
The voltage VB1 of the bias power supply 18 is set to be higher than the base-emitter voltage VBEQ16. Here, the time t2 ″ required to rise completely is given by the following expression (7).

T2 ″ = C (V2-V1) / I = VR / I (7) where C: capacitance of the capacitor 21, I: current value of the current source 20, VR: base voltage of the NPN transistor 14, V
I = VB1-VBEQ16, V2 = VB2 + VBEQ1
7.

Assuming that the voltage of the two terminals of the writing circuit 2, the X terminal, is VS and the voltage of the Y terminal is VY, the following (8)
It becomes an expression.

[0057]

However, RZ: write head inductance DC resistance, Icheck: collector current of NPN transistor 14.

Although the collector current Icheck of the NPN transistor 14 flowing through the write head 6 gradually increases until time t2 ", the voltage values VREF and X of the reference voltage 9 connected to the non-inverting input terminal of the comparator 8 After time t1 ″ when the terminal voltages VS become equal, the voltage VS at the X terminal becomes VS> VREF, and at time t1 ″, the output of the comparator 8 becomes L level.

This output is the delay flip-flop 11
Input to the data terminal of the delay flip-flop 1
Since the output of the delay circuit 10 that delays the inverted output of the one-shot multivibrator 25 by a fixed time td and is output is connected to the clock terminal of 1, the delay flip-flop at t2 when the output of the delay circuit changes from L level to H level. The Q output of the amplifier 11 becomes L level, and therefore the output terminal 12 also becomes L level.

Next, at t4 ″, after a certain time from t0 to t4 ″, when the output of the inverting terminal of the one-shot multivibrator 25 becomes L level, the switch 26 is turned off and the switch 27 is turned on. Capacitor 2
The charge of 1 is removed to lower the base voltage of the NPN transistor 14 to turn it off.

Therefore, the collector current Icheck of the NPN transistor 14 is cut off. At this time, the voltage of the bias power supply 18 is determined so that the NPN transistor 16 is turned on.

The one-shot multivibrator 25
Since the output of the non-inverting terminal of H becomes H level and the switch 30 is turned on, the writing circuit 2 causes the writing current IW to flow to the writing head 6 by the writing current source 3.

Next, at time t5 ", the signal applied to the input terminal 1 changes from H level to L level.
The direction of the write current IW flowing through the write head 6 also changes in the opposite direction.

Next, the operation when the write head inductance is open will be described with reference to FIGS. 1, 2, 5 and 6.

The operation waveforms of the respective parts of the circuits of FIGS. 1 and 2 when the write head inductance is open are shown separately in FIGS. 5 and 6, and some of the waveforms are duplicated to clarify the relationship. There is.

The operation from time t0 to time t2 "in FIGS. 5 and 6 is the same as in the normal head state, but the collector current Icheck of the NPN transistor 14 is the write head 6
When the inductance of the write head 6 is open, the X-side output terminal voltage VS ′ at time t2 ″ is given by the following expression (9).

VS ′ = VY−RD · Icheck (9) VS ′ is RZ // RD in the equation (8) and RD in the equation (8) with respect to VS given by the above equation (8). Therefore, VS> VS '.

Therefore, VREF is set so that the relationship between the voltage VREF of the reference voltage 9 and the X-side output terminal voltage VS 'when the write head inductance is open is VREF>VS'.
Is set, the output of the comparator 8 at time t2 ″ is H level, and at t3 ″ when the output of the delay circuit 10 changes from L level to H level, the Q output of the delay flip-flop 11 becomes H level and the output terminal 12 Also becomes H level.

Therefore, the inductance open of the write head 6 can be detected.

Further, since the collector current Icheck of the NPN transistor 14 rises with an inclination, the counter electromotive voltage is not generated in the voltage of the X side output terminal 4.

Therefore, at the same time that the collector current Icheck of the NPN transistor 14 becomes stable, the voltage of the X terminal 4 also becomes a stable value, and the X terminal voltage is surely a stable value until the output of the delay circuit 10 becomes H level. Therefore, the state of the write head 6 can be accurately detected.

[0073]

As described above, the present invention is not affected by the back electromotive voltage VL which changes depending on the value of the write current IW or the inductance and the time tS from the charging to the discharging of the capacitor 21. It is possible to accurately detect the state of the write head.

In particular, by making the rising of the collector current Icheck of the NPN transistor 14 have a slope, the counter electromotive voltage does not occur when the X terminal voltage rises, and the value of the X terminal voltage is surely stable when the head state is detected. Has the effect of becoming.

In the case of the conventional circuit, when the write current IW becomes large or the inductance of the write head 6 becomes large, the time tH at which the comparator 8 outputs the H level becomes large and tH>
When td (delay time of the delay circuit 10) is reached, when the accurate state of the write head 6 is to be detected, the delay time td of the delay circuit 10 is varied according to the write current IW or the value of the inductance of the write head 6. There is a need.

Therefore, when the conventional circuit is manufactured by a semiconductor integrated circuit, it is necessary to make a semiconductor integrated circuit having several kinds of delay times td of the delay circuit 10 or change the value of the delay time td in the manufacturing process of wiring or the like. However, according to the present invention,
Since it does not depend on the write current IW or the value of the inductance of the write head 6, only one type of semiconductor integrated circuit needs to be created, and there is no need to change the value of the delay time td in the process of wiring or the like. It is suitable for semiconductor integrated circuits.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first portion of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second part of the embodiment of the present invention.

FIG. 3 is a waveform chart showing a first portion of operation waveforms of respective portions when the write head of the present embodiment is normal.

FIG. 4 is a waveform diagram showing a second portion of FIG.

FIG. 5 is a waveform diagram showing a first part of operation waveforms of respective parts when the write head inductance is open in the present embodiment.

FIG. 6 is a waveform diagram showing a second portion of FIG.

FIG. 7 is a circuit diagram showing a conventional load open detection circuit.

FIG. 8 is a waveform diagram showing operation waveforms of respective parts when a write head is normal according to a conventional circuit.

FIG. 9 is a waveform diagram showing operation waveforms of respective parts when the write head inductance is open in the conventional circuit.

FIG. 10 is a waveform diagram showing operation waveforms of respective parts when the write current is large or the write head inductance is large in the conventional circuit.

[Explanation of symbols]

 1 Input Terminal 2 Writing Circuit 3 Writing Current Source 4 X Side Output Terminal 5 Y Side Output Terminal 6 Writing Head 7 Damping Resistor 8 Comparator 9 Reference Voltage 10 Delay Circuit 11 Delay Flip-Flop 12 Output Terminal 13 Mode Switching Terminal 14, 16 NPN Transistor 15 resistance 17 PNP transistor 18, 19 bias power supply 20, 24 current source 21 capacitor 23 inverter 25 one-shot multivibrator 26, 27, 30 switch 28 power supply terminal 29 ground terminal

Claims (1)

[Claims] 1. A first write constant current source, an input terminal and 2
A magnetic disk write circuit having two output terminals and an inductance load and a resistor connected in parallel between the output terminals, and one end of the two outputs is connected to an inverting input terminal and a reference voltage is connected to a non-inverting input terminal. A comparator,
A delay circuit for delaying a signal applied to the input terminal of the write circuit of the magnetic disk, an output of the comparator to a data terminal, an output of the delay circuit to a clock terminal, a mode switching terminal to a reset terminal, and an output terminal to Q output. In a load open detection circuit including delay flip-flops respectively connected to a one-shot multivibrator having the mode switching terminal as an input, and an inverted output of the one-shot multivibrator as an input to the clock terminal of the delay flip-flop. And a delay circuit for connecting the first write constant current source to the magnetic disk write circuit via a first switch that turns on at the H level of the non-inverting output of the one-shot multivibrator and turns off at the L level. The collector is the inverting input terminal of the comparator Connected emitter of the first transistor connected to the second power supply terminal via a resistor, the base is connected to the collector to the first power supply terminal first
A second transistor whose emitter is connected to the constant voltage source of which the emitter is connected to the base of the first transistor, and whose collector is connected to the second power supply terminal and whose base is connected to the second constant voltage source. Is connected to the base of the first transistor and has a conductivity type third transistor different from those of the first and second transistors; one end is connected to the first power supply terminal; Turned on at the H level of the output voltage of the inverting terminal of the vibrator,
A second constant current source connected to the base of the first transistor through a second switch that turns off at the L level, and one end of the second constant current source connected to the second power supply terminal and the other end of the one-shot multivibrator. H of the output voltage of the inverting terminal
A third constant current source connected to the base of the first transistor through a third switch that obtains a control signal from the output of the one-shot multivibrator through an inverter so that the third transistor is turned off at the level and turned on at the L level. When,
A load open detection circuit comprising: a capacitor having one end connected to the base of the first transistor and the other end connected to the second power supply terminal.