JPH06120830A - AD converter - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a follow-up comparison type AD conversion device in which a minimum value bit of a digital value of an AD conversion result of an input analog signal of a constant voltage does not change. [Structure] Offset values are added by adders 8 and 11 to the digital value of the AD conversion result appearing at output terminal 6, and converted into analog voltage by DA converters 9 and 12, respectively. This D
The output voltage of the A converters 9 and 12 follows the voltage of the analog signal input to the input terminal 1. As a result, when the voltage of the input analog signal enters between the output voltages of the DA converters 9 and 12, the up / down counter 5 is in a count stop operation state and the digital value of the AD conversion result does not change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a follow-up comparison type AD converter.

[0002]

2. Description of the Related Art At present, several types of AD converters have been put into practical use, and one of them is called a follow-up comparison type. A follow-up comparison type AD conversion device according to this conventional technique will be described below with reference to the drawings. FIG. 3 is a block diagram of an example of the follow-up comparison type AD converter. In the figure, 101 is an input terminal for inputting an analog signal to be AD converted, 102 is a non-inverting input for the analog signal input to the input terminal 101 and an inverting input for an output voltage from a DA converter 107 described later. 103 is a voltage comparator for
Is a voltage comparator that uses an analog signal input to the input as an inverting input and an output voltage from a DA converter 107 described later as a non-inverting input, 104 is a clock signal generator that generates a clock signal, and 105 is a clock. Signal generator 1
04 is a clock signal source and is an up / down counter controlled to count up, count down, or stop counting by the voltage comparators 102 and 103.
6 is the digital output value of the up / down counter 105
Reference numeral 107 denotes an output terminal for outputting as an AD conversion result of the analog signal input to 01, and DA 107 which converts the digital output value of the up / down counter 105 into an analog value again and uses it as the reference voltage of the voltage comparators 102 and 103. It is a converter.

Next, FIG. 4 shows operation waveforms of the AD converter. In the figure, 201 is a voltage waveform of an analog signal input to the input terminal 101,
02 is an output voltage waveform of the DA converter 107,
Is the output voltage waveform of the clock signal generator 104,
Reference numerals 03 and 204 respectively represent the output logic levels of the voltage comparators 102 and 103 in positive logic.

The operation of the AD converter configured as above will be described below. The analog signal input to the input terminal 101 is input to the voltage comparators 102 and 103. The digital output value of the up / down counter 105 converted into an analog voltage value by the DA converter 107 is fed back to the voltage comparators 102 and 103 as a reference voltage. The voltage comparator 102 compares the voltage of the input analog signal with the output value of the DA converter 107 that has been fed back, and as shown by the waveforms 201, 202, and 203 in FIG. D has been returned
If it is larger than the output value of the A converter 107, the logic level "
1 ", and if smaller, outputs logic level" 0 ".
The voltage comparator 103 has the waveforms 201, 202, 20 shown in FIG.
As shown in 4, if the voltage of the input analog signal is larger than the output value of the DA converter 107 that has been fed back, the logic level "0" is output, and if it is smaller, the logic level "1" is output. The up / down counter 105 performs a count operation by the clock signal from the clock signal generator 104, and the count up, count down, and count stop operations are performed by the voltage comparators 102, 10 according to the logic shown in FIG.
3 output.

That is, the digital output value of the up / down counter 105 output as the AD conversion result is converted into an analog voltage value, and this is compared with the voltage of the input analog signal by a voltage comparator, and then input. The negative feedback loop is configured so that both voltages are always equal by performing up-counting if the voltage of the generated analog signal is large and performing down-counting if the voltage is small. As a result, the digital output value of the up / down counter follows the voltage of the input analog signal, and the AD conversion result appears at the output terminal 106.

[0006]

However, in the above configuration, as shown in the period TS of FIG. 4, even when the voltage of the input analog signal is constant, the output voltage of the DA converter 107, that is, AD appearing at output terminal 106
There is a problem that the minimum value bit (LSB) of the digital value of the conversion result changes in the clock cycle. This is because the negative feedback loop becomes unstable due to the quantization of the up / down counter 105 and the DA converter 107.
That is, the up-down counter 105 down-counts by one step in a state in which the output voltage of the DA converter 107 is slightly higher than the input analog signal voltage, and thus the output voltage of the DA converter 107 is input by the analog signal voltage. Will be slightly below. Therefore, the up / down counter 105 is up-counted by one step in the next clock cycle, returns to the previous state, and repeats thereafter.

Therefore, this fluctuation is eliminated and stable A
In order to perform the D conversion, it is necessary to provide a logic circuit for giving a hysteresis characteristic or averaging the output in the subsequent stage of the AD converter, which causes an increase in cost and an increase in mounting area. The present invention has been made in view of the above problems, and an object thereof is to provide an AD conversion apparatus that can perform stable AD conversion while being a follow-up comparison type.

[0008]

In order to achieve the above object, in the invention of claim 1, a comparator compares an analog signal input from the outside and an analog value obtained by DA converting a digital value output to the outside. In the AD converter that operates so as to minimize the difference between the two, the comparator has a dead zone when outputting the comparison of the difference between the two.

According to another aspect of the present invention, the input terminal for the analog signal from the outside, the output terminal for the digital signal of the AD conversion result to the outside, and the voltage of the analog signal input from the input terminal First and second voltage comparators respectively comparing with a second reference voltage, a clock signal generator for generating a clock signal, and operating in response to a clock signal from the clock signal generator, and the first voltage comparator.
And the count is controlled by a predetermined logic procedure by the input from the second voltage comparator, and finally the analog signal value input from the outside is output to the output terminal as the digital signal value of the AD conversion result. And an up / down counter for outputting a digital value output from the up / down counter, and a value obtained by adding a first offset value determined in consideration of a dead band input separately from an external analog signal. First adder and a digital value output from the first adder are converted into analog values and are supplied to the first voltage comparator as the first reference voltage.
A second value that outputs a value obtained by adding a second offset value that is determined in consideration of a dead band that is input separately from an analog signal from the outside to the digital value output from the A converter and the up / down counter. A second D that converts the digital value output from the adder and the second adder into an analog value and supplies the analog value to the second voltage comparator as the second reference voltage.
An AD converter having an A converter.

According to the invention of claim 3, at least one of the first offset value and the second offset value is variable, and the AD converter according to claim 2 is characterized.

[0011]

With the above structure, in the invention of claim 1,
A comparator for comparing an analog signal input from the outside and a digital value output to the outside with a D / A converted analog value has a dead zone in outputting a difference between the two. In the invention of claim 2, the first and second voltage comparators respectively apply the analog signal voltage input from the outside to the first
And a second reference voltage. The clock signal generator generates a clock signal. The up-down counter operates according to the clock, and the outputs of the first and second voltage comparators control the counting in accordance with a predetermined logic procedure, which allows the analog signal value input from the outside to be controlled. The signal value of the AD conversion result is output to the outside. The first adder adds a digital value output from the up / down counter with a first offset value determined in consideration of a dead band input separately from an external analog signal and outputs the result. The second adder adds a second offset value determined in consideration of a dead band inputted separately from an analog signal from the outside to the digital value output from the up / down counter and outputs the digital value. First DA
The converter converts the digital value output from the first adder into an analog value, and then uses this as a first reference voltage for the first reference voltage.
Supply to the voltage comparator of. The second DA converter converts the digital value output from the second adder into an analog value and then supplies this to the second voltage comparator as a second reference voltage.

In the third aspect of the invention, at least one of the first offset value and the second offset value is variable.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An AD converter according to the first and second aspects of the present invention will now be described based on an embodiment with reference to the drawings. FIG. 1 is a block diagram of an embodiment of an AD converter according to the present invention. In this figure, 1 is AD
Reference numeral 2 is an input terminal for inputting an analog signal to be converted. Reference numeral 2 is a first input terminal for inputting an analog signal input to the input terminal 1 as a non-inverting input and an output voltage from a first DA converter 9 described later as an inverting input. Reference numeral 3 is a voltage comparator, and 3 is a second voltage comparator having an analog signal input to the input terminal 1 as an inverting input and an output voltage from a second DA converter 12 described later as a non-inverting input, Reference numeral 5 designates the clock signal generator 4 as a clock signal source, and the first and second voltage comparators 2, 3
Is an up / down counter whose count up, count down, and count stop are controlled by, and 6 is an output terminal for outputting the digital output value of the up / down counter 5 as an AD conversion result of the analog signal input to the input terminal 1, Reference numeral 7 is an input terminal for inputting a first offset value determined to obtain a predetermined dead band separately from an external analog signal, and 8 is an up-down counter 5
Is a first adder for adding and outputting the first offset value input to the input terminal 7 for the first offset value to the digital output value of, and 9 is a digital output value from the adder 8 to an analog voltage value. Reference numeral 10 denotes a first DA converter which is converted and supplies the inverted voltage as a reference voltage of the first voltage comparator 2 to the analog input signal from the outside. Reference numeral 11 is a separate input terminal for inputting the second output value of the digital output value of the up / down counter 5 to the input terminal 10 of the second offset value.
Is a second adder that adds and outputs the offset value of
Reference numeral 12 is a second DA converter that converts the digital output value from the adder 11 into an analog voltage value and supplies the analog voltage value to the non-inverting input as the reference voltage of the second voltage comparator 3. The input terminal 1, the voltage comparators 2 and 3, the clock signal generator 4, the up / down counter 5, and the output terminal 6 are the same as those of the AD converter according to the above-mentioned conventional technique, and therefore, their constituent functions. The explanation of the action and the like for exhibiting is omitted.

Next, FIG. 2 shows operation waveforms of this AD converter. In the figure, 21 is a voltage waveform of the analog signal input to the input terminal 1, and 25,
Reference numeral 26 is the output voltage waveforms of the first and second DA converters 9 and 12, 27 is the output voltage waveform of the clock signal generator 4, and 23 and 24 are the first and second voltage comparators, respectively. The output logic levels of 2 and 3 are expressed in positive logic. In addition, 22 is an output voltage waveform of the first and second DA converters 9 and 12 when 0 is given as an offset value to the first and second offset value input terminals 7 and 10 (output to the output terminal 6). 3 is an analog output voltage waveform when the digital output value of the AD conversion result is directly input to the first and second DA converters 9 and 12. That is, FIG.
The voltage V _T1 showing an offset voltage of the first offset value given to the input terminal 7 of the first offset value, the voltage V _T2 second supplied to the input terminal 10 of the second offset value It is an offset voltage depending on the offset value. In the figure, the first offset value is a positive value and the second offset value is a negative value.

The operation of the AD converter configured as above will be described below. When the analog signal shown by the waveform 21 in FIG. 2 is input to the input terminal 1, this becomes the non-inverting input of the voltage comparator 2 and the inverting input of the voltage comparator 3. Further, the first and second offset values are added to the digital output value of the up / down counter 5 and converted into the analog voltage waveforms 25 and 26 shown in FIG. 2 by the first and second DA converters 9 and 12, respectively. Voltage comparator 2,
Returned to 3.

Here, as shown in the periods T ₁ , T ₂ , and T ₃ of FIG. 2, the voltage of the input analog signal is the first DA signal.
When it becomes higher than the output voltage of the converter 9, the voltage comparator 2 outputs the logic level "1" as shown by the waveform 23 in FIG.
As a result, the up / down counter 5 is up-counted in the next clock cycle, and as a result, the first and second D
The output voltage of the A converters 9 and 12 rises by being up-counted. On the contrary, the periods T4, T5, T6 in FIG.
2, when the voltage of the input analog signal becomes lower than the output voltage of the DA converter 12, the voltage comparator 3 outputs the logic level "1" as shown by the waveform 24 in FIG.
As a result, the up / down counter 5 is down-counted in the next clock cycle, and as a result, the first and second D
The output voltage of the A converters 9 and 12 drops as much as it is down-counted.

By the up-counting or down-counting of the above-mentioned up-down counter 5, as shown in the period T _{A of} FIG. 2, the input analog voltage is changed to the first D
The second DA converter 1 that is lower than the output voltage of the A converter 9 and
In the range higher than the output voltage of 2, that is, in the dead zone of the first and second voltage comparators 2 and 3, both the first and second voltage comparators 2 and 3 output the logic level "0". To do. As a result, the up / down counter 5 is brought into an operation state of counting stop, and the digital value of the AD conversion result appearing at the output terminal 6 does not change.

That is, the offset value to be input to the input terminals 7 and 10 should be set so that the digital output value of the first adder 8 becomes larger than the digital output value of the second adder 11 by 1 or more. For example, when the voltage of the input analog signal is constant, the fluctuation of the digital value of the AD conversion result appearing at the output terminal 6 in the clock cycle is eliminated. In addition, since the first and second offset values that set this dead zone are digital values, the offset voltages V _T1 and V _T2 due to this are stable with respect to temperature changes, and also do not easily change over time.

The offset voltages V _T1 and V _T2 are
The relationship is not limited to that shown in FIG. 2, and any one may be used as long as the above conditions are satisfied unless the dead band is unnecessarily widened in order to prevent the accuracy of AD conversion from deteriorating. (Second Embodiment) The invention of claim 3 will be described below based on an embodiment.

Since the basic structure of this embodiment is similar to that of the first embodiment, the drawing thereof, that is, FIG. 1 will be used for explanation. In this embodiment, the first and second offset values given to the input terminals 7 and 10 of the first and second offset values in FIG. 1 are variable. In terms of hardware, this is the first and second offset value input terminals 7,
It can be easily realized by using or connecting to a DIP switch, a rotary switch, or an output port of a CPU.

In the present embodiment, it goes without saying that the effects described in the above-mentioned first embodiment are obtained, but in addition to that, when noise is added to the input analog signal,
This removal is possible. That is, if the first and second offset values are set so that the dead band range is larger than the peak voltage of noise of the analog signal input to the input terminal 1 of FIG. 1, the first and second offset values are set by noise. The voltage comparators 2 and 3 do not output a signal of logic level "1". Therefore, the up / down counter 5 does not operate with the input noise, and the noise-removed AD conversion result digital value is output to the output terminal 6.
Further, it is also possible to give an arbitrary offset to the AD conversion result output to the output terminal 6 by relatively increasing / decreasing the first and second offset values.

Although the present invention has been described based on the embodiments, it goes without saying that the present invention is not limited to the above embodiments. That is, for example, in the embodiment of the invention of claim 2, the effect of the invention of claim 3 may be obtained by adding a capacitor to the input terminal side depending on the nature of noise. In the embodiment of the invention of claim 3, both of the offset values are variable, but only one of them may be used depending on the nature of noise.

Similarly, "variable" means changeable, and it does not matter what the content is, analog type, digital type, or the number of stages is limited.

[0024]

As described above, according to the first, second and third aspects of the invention, in the AD converter of the tracking comparison type, the input analog signal and the digital value of the output AD conversion result are DA-converted. Since a hysteresis characteristic is added to the comparator that compares with the analog value, A that appears at the output terminal even when the voltage of the input analog signal is constant.
The problem that the digital value of the D conversion result fluctuates in the clock cycle is solved. For this reason, a logic circuit for realizing the hysteresis characteristic addition or averaging in the latter stage is unnecessary.

In the invention of claim 2, since the offset value for setting the dead zone of the comparator is given by a digital value,
It is possible to obtain extremely stable hysteresis characteristics with respect to temperature changes and changes over time. According to the third aspect of the invention, when the analog signal added with noise is AD-converted, this noise can be removed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an AD converter according to the first and second aspects of the invention.

FIG. 2 is an operation waveform diagram of the above embodiment.

FIG. 3 is a block diagram of an AD conversion device according to a conventional technique.

FIG. 4 is an operation waveform diagram of the AD conversion device according to the conventional art.

FIG. 5 is a logical operation diagram of an up / down counter in the AD conversion device according to the conventional art.

[Explanation of symbols]

1 Input Terminal 2 1st Voltage Comparator 3 2nd Voltage Comparator 4 Clock Signal Generator 5 Up / Down Counter 6 Output Terminal 7 Input Terminal for 1st Offset Value 8 1st Adder 9 1st DA Conversion Device 10 Input terminal for second offset value 11 Second adder 12 Second DA converter 21 Voltage waveform of analog signal input to input terminal 1 22 DA converters 9 and 12 when offset value is 0
Output voltage waveform of 23 Output logic level of voltage comparator 2 24 Output logic level of voltage comparator 3 25 Output voltage waveform of DA converter 9 26 Output voltage waveform of DA converter 12 27 Output voltage waveform of clock signal generator 4 V _T1 first offset voltage equivalent value V _T2 second offset voltage equivalent value 101 input terminal 102 first voltage comparator 103 second voltage comparator 104 clock signal generator 105 up / down counter 106 output terminal 107 DA conversion 201 Voltage waveform of analog signal input to input terminal 101 202 Output voltage waveform of DA converter 107 203 Output logic level of voltage comparator 102 204 Output logic level 207 of voltage comparator 103 207 Output voltage of clock signal generator 104 Waveform

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiro Tatsuda 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yasuo Nagaishi 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. An analog-to-digital converter input from the outside and an analog value obtained by DA-converting a digital value to be output to the outside are compared by a comparator, and an AD converter that operates so as to minimize the difference between them. The AD conversion device, wherein the comparator has a dead zone when outputting the comparison of the difference between the two. 2. An input terminal for an analog signal from the outside, an output terminal for outputting a digital signal of an AD conversion result to the outside, and a voltage of the analog signal input from the input terminal
First and second voltage comparators for respectively comparing the first and second reference voltages; a clock signal generator for generating a clock signal; and a first signal comparator for operating in response to a clock signal from the clock signal generator, And the count is controlled by a predetermined logic procedure by the input from the second voltage comparator, and finally the analog signal value input from the outside is
An up / down counter which is output to the output terminal as a digital signal value of the D conversion result, and a dead band which is input to the digital value output from the up / down counter separately from an analog signal from the outside. A first adder that outputs a value obtained by adding an offset value of 1; and a digital value output from the first adder that is converted into an analog value to the first voltage comparator as the first reference voltage. A first DA converter to be supplied, and a value obtained by adding a second offset value determined in consideration of a dead band input separately from an analog signal from the outside to the digital value output from the up / down counter. A second adder for outputting, and a second adder for converting the digital value output from the second adder into an analog value and supplying the analog value to the second voltage comparator as the second reference voltage. AD converter having the DA converter of. 3. The AD converter according to claim 2, wherein at least one of the first offset value and the second offset value is variable.