JPH0612367A - Information processor - Google Patents

Abstract

PURPOSE:To provide the information processor which performs efficient interrupt processing by uniformizing interrupts which are biased in interrupt requesting devices close to an interrupt controller. CONSTITUTION:This information processor consists of the interrupt controller 1 which performs interrupt control and plural interrupt requesting devices 7a, 7b, and 7c which are cascaded in order to the interrupt controller 1 through an interrupt request line 3 and interrupt permission lines 5a, 5b, and 5c, and the respective interrupt requesting devices 7a, 7b, and 7c are connected by interrupt display lines 9b and 9c. Further, the respective interrupt requesting devices 7a, 7b, and 7c are equipped with means which preferentially perform interrupt processing of their devices if their devices hold interrupts above a certain frequency even when sending interruption indications to the interrupt request line 3 and then detecting interruption permissions from the interrupt permission lines 5a, 5b, and 5c, and give priority to interrupts of low-order interrupt requesting devices when their devices hold the interrupts below the certain frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus having an efficient interrupt processing.

[0002]

2. Description of the Related Art An information processing apparatus of this type is generally composed of an interrupt control device for processing an interrupt and a plurality of interrupt request devices which are sequentially connected to the interrupt control device. In such an information processing apparatus, when there are interrupt requests from a plurality of interrupt requesting devices at the same time, if an interrupt request is issued from the interrupt controlling device, the interrupt requesting device closest to this interrupt controlling device starts an interrupt. Was becoming. Therefore, the interrupt request device connected farther than the interrupt request device closest to this interrupt control device is made to wait for the interrupt.

Such a state becomes more frequent because more interrupt requests are generated as the operating rate of the information processing apparatus increases. Therefore, the farther the interrupt requesting device is from an interrupt requesting device, the more the interrupt requesting device waits for an interrupt request, and the interrupt requesting device waiting for an interrupt request interrupts only when an interrupt requesting device closer to it is not interrupted. Was able to be executed.

[0004]

As described above, in the conventional information processing apparatus, the farther the interrupt requesting device is from the generating interrupt control device, the more the interrupt is waited, and the interrupt processing is performed by the interrupt control device. There is a drawback in that the efficiency of interrupt processing is low because it is biased toward the interrupt requesting device.

Therefore, the present invention solves the above-mentioned drawbacks and provides an information processing apparatus capable of equalizing interrupts biased to interrupt requesting devices close to an interrupt control device and performing efficient interrupt processing. With the goal.

[0006]

In order to achieve the above-mentioned object, an information processing apparatus of the present invention provides an interrupt control device for interrupt control, and an interrupt request line and an interrupt permission line for this interrupt control device. It is an information processing device that is composed of a plurality of interrupt request devices connected in sequence and that connects each interrupt request device with an interrupt display line, and each interrupt request device sends an interrupt instruction to the interrupt request line. Even if the interrupt permission is detected from the interrupt permission line, the priority is given to the interrupt processing of the own device when the own device holds the interrupt for a certain number of times or more, and the lower interrupt request is issued when the interrupt is held for the certain number of times or less. It is characterized in that a means for prioritizing the interruption of the device is provided.

Each interrupt request device includes an interrupt request circuit, an interrupt status display circuit, an interrupt permission detection circuit,
It has an interrupt state detection circuit, an interrupt pending count storage circuit, an interrupt determination circuit, and an interrupt instruction circuit. The interrupt instruction circuit issues an interrupt instruction, and the interrupt permission detection circuit detects interrupt permission from the interrupt permission line. However, when the number of interrupts from the interrupt pending count storage circuit is a certain number or more,
It is characterized in that the interrupt processing of its own device is prioritized regardless of the state of the interrupt display line.

Further, the interrupt judgment circuit gives priority to the interrupt processing of the lower interrupt request device when the number of times of holding from the interrupt holding number storage circuit is 0, and when the number of holding is 1, the interrupt of its own device is given. It is characterized in that processing is prioritized.

According to the present invention, even if there is an interrupt instruction and interrupt permission detection, when the own interrupt request device holds an interrupt for a certain number of times (one time) or more, its own interrupt processing is given priority and a certain number of times ( When it is held less than once, the interrupt of the lower interrupt request device is prioritized. Therefore, the interrupt request device close to the interrupt control device does not give priority to interrupt processing.

[0010]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention. FIG. 2 is an explanatory diagram for explaining an operation related to an interrupt of the interrupt request device according to the embodiment of the present invention.

The information processing apparatus shown in FIG. 1 includes an interrupt controller 1 for controlling interrupt processing, an interrupt request line 3 and interrupt enable lines 5a, 5b,
It is composed of a plurality of interrupt requesting devices 7a, 7b, 7c which are sequentially connected through 5c.

In the above-mentioned information processing apparatus, the interrupt control device 1 is connected to the interrupt request line 3, and the interrupt request detection circuit 11 for detecting an interrupt request and the interrupt permission line 5a.
And an interrupt permission circuit 12 for issuing an interrupt permission.

The interrupt requesting devices 7a, 7b and 7c have the same function. Therefore, the configuration of the interrupt requesting device 7a will be described as a representative, and the other components will be simply denoted by reference numerals and description thereof will be omitted.

Here, the interrupt request device 7a is connected to the interrupt request line 3 and requests an interrupt.
1a and interrupt status display circuit 72 for displaying the interrupt status
a, an interrupt permission detection circuit 73a which is connected to the interrupt permission lines 5a and 5b and permits an interrupt, an interrupt state detection circuit 74a which detects an interrupt state, an interrupt hold number storage circuit 75a which holds an interrupt, and an interrupt An interrupt determination circuit 76a for determining whether there is an interrupt and an interrupt instruction circuit 77a for instructing an interrupt are provided. In the interrupt request device 7a, the interrupt instruction circuit 77a is connected to the interrupt state display circuit 72a and the interrupt determination circuit 76a by an interrupt instruction line 771a, and the interrupt instruction line 772.
It is connected to the interrupt request circuit 71a at a. The interrupt permission detection circuit 73a is connected to the interrupt hold number storage circuit 75a via an interrupt hold line 731a and to the interrupt determination circuit 76a via an interrupt enable line 732. The interrupt pending frequency storage circuit 75a is connected to the interrupt determination circuit 76a via an interrupt pending frequency display line 751a. Interrupt judgment circuit 76
a is connected to the interrupt permission detection circuit 73a by an interrupt hold instruction line 761a. Interrupt state detection circuit 74a
Are connected to the interrupt determination circuit 76a by the interrupt state detection line 741.

The interrupt state detection circuit 74a of the interrupt requesting device 7a uses the interrupt display line 9b to detect the interrupt requesting device 7a.
It is connected to the interrupt state display circuit 72b of b. The interrupt state detection circuit 74b of the interrupt request device 7b is connected to the interrupt state display circuit 72c of the interrupt request device 7c by an interrupt display line 9c.

The operation of the embodiment having such a configuration will be described.

In each of the interrupt requesting devices 7a, 7b, 7c, when there is no interrupt, both the interrupt instruction line 771 and the interrupt permission line 732 are "0" as shown in FIG. 2A, and the interrupt hold line 751. And interrupt display line 9
Is "*". "*" Means that either "1" or "0" may be used.

On the other hand, in the interrupt request devices 7a, 7b, 7c, when an interrupt request occurs, the interrupt request circuit 71
a, 71b, 71c set the interrupt request line 3 to "1".
This causes an interrupt. Then, the interrupt request detection circuit 11 of the interrupt control device 1 detects that an interrupt request has been issued. At this time, when the interrupt control device 1 determines that the interrupt can be permitted, the interrupt permission circuit 12 sets the interrupt permission line 5a to "1".

As a result, the interrupt is permitted. Interrupt permission detection circuit 73a of interrupt request device 7a
Detects that the interrupt permission is given (the interrupt permission detection signal line 732a becomes "1").

Further, the interrupt requesting device 7b informs the interrupt requesting device 7a that the interrupt requesting device 7b is making an interrupt request by setting the interrupt display line 9b to "1" by the interrupt state display circuit 72b. As a result, the interrupt state detection circuit 74a of the interrupt request device 7a detects that an interrupt request is being made.

In such a state, the interrupt request device 7a is making an interrupt request and the interrupt permission detection circuit 73
When a detects the interrupt permission, the interrupt request device 7
Since a does not make an interrupt and informs the interrupt request device 7b of interrupt permission, it holds its own interrupt. When the interrupt is held, the interrupt permission detection circuit 73a changes the interrupt hold line 731a to “0”, “1”, and “0”, thereby indicating that the interrupt is held.
Tell 5a. Therefore, the interrupt pending frequency storage circuit 75a
Counts the number of times the interrupt hold line 731a has changed to “0”, “1”, and “0”, and stores the count as the number of times the interrupt is held.

Further, as shown in FIG. 2B, the interrupt permission detection circuit 73a detects the interrupt permission and sets the interrupt permission detection line 732a to "1", and the interrupt instruction circuit 77a for instructing the interrupt request is provided. If the interrupt instruction line 771a is set to "0" because no interrupt instruction is given,
Interrupt determination circuit 76a for determining whether or not to make an interrupt
Changes the interrupt hold line 761a from "1" to "0".
As a result, the interrupt permission detection circuit 73a changes the interrupt permission line 5b from "0" to "1", thereby transmitting the interrupt permission from the interrupt request device 7a to the interrupt request device 7b.

Further, as shown in FIG. 2C, the interrupt permission detection circuit 73a does not detect the interrupt permission, the interrupt permission line 732a is set to "0", and the interrupt instruction circuit 77a for instructing the interrupt request is provided. If the interrupt instruction line 771a is set to "1", the interrupt requesting device 7a waits for an interrupt.

Alternatively, as shown in FIG. 2 (4), the interrupt permission detection circuit 73a detects an interrupt, and the interrupt instruction circuit 77a issues an interrupt instruction to issue an interrupt instruction line 771a.
Is set to "1", and the interrupt state detection circuit 74a has not detected the interrupt request of the interrupt request device 7b (interrupt display line 9b
Is "0"), if the number of holding times indicated by the interrupt holding number storage line 751a is 0 in the interrupt holding number storage circuit 75a, the interrupt requesting device 7a executes an interrupt.

Alternatively, as shown in FIG. 2 (5), the interrupt permission detection circuit 73a detects the interrupt permission, and the interrupt instruction circuit 77a issues an interrupt instruction to issue an interrupt instruction line 77.
1a is set to "1", and the interrupt state detection circuit 74a detects the interrupt request of the interrupt request device 7b (interrupt display line 9
When “b” is “1”), the interrupt holding frequency storage circuit 75
If a has the number of holding times indicated by the interrupt holding number display line 751a of 0, an interrupt is transmitted to the interrupt requesting device 7b.

Alternatively, as shown in FIGS. 2 (6) and (7), the interrupt permission detection circuit 73a detects the interrupt permission,
Further, the interrupt instruction circuit 77a issues an interrupt instruction to set the interrupt instruction line 771a to "1", and the interrupt hold number storage circuit 7
5a indicates that the number of holding times indicated by the interrupt holding number display line 751a is one, and the interrupt state detection circuit 74a has not detected the interrupt request of the interrupt request device 7b (interrupt display line 9b is "0") or detected (interrupt). The interrupt requesting device 7a executes an interrupt regardless of whether the display line 9b is "1").

In the above embodiment, the interrupt request device 7
Although the operation of the interrupt processing has been described in relation to a and 7b, the same operation is performed with the interrupt requesting devices 7b and 7c so that the interrupt of the interrupt requesting device 7c can be accepted.

[0029]

As described above, according to the information processing apparatus of the present invention, even if the interrupt instruction and the interrupt permission are detected, the own interrupt requesting apparatus gives priority to its own interrupt processing when the interrupt request is held for a certain number of times or more. However, since the interrupts of the lower-order interrupt request device are prioritized when the interrupts are held for a certain number of times or less, there is an effect that the interrupts are not biased to the interrupt request devices close to the interrupt control device and efficient interrupt processing can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing device of the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment of the present invention.

[Explanation of symbols]

 1 Interrupt Control Device 3 Interrupt Request Lines 5a, 5b, 5c Interrupt Enable Lines 7a, 7b, 7c Interrupt Request Device 11 Interrupt Request Detection Circuit 12 Interrupt Enable Circuit 71 Interrupt Request Circuit 72 Interrupt Status Display Circuit 73 Interrupt Enable Detection Circuit 74 Interrupt Status Detection circuit 75 Interrupt pending frequency storage circuit 76 Interrupt determination circuit

Claims (3)

[Claims] 1. An interrupt control device for controlling interrupts, and a plurality of interrupt request devices connected to the interrupt control device sequentially through interrupt request lines and interrupt permission lines, and each interrupt request device. An information processing device in which the interrupt request lines are connected to each other by an interrupt display line, and each of the interrupt request devices issues an interrupt instruction to the interrupt request line Is held for a certain number of times or more, the interrupt processing of its own device is given priority, and when it is held for a certain number of times or less, a means for giving priority to an interrupt of a lower interrupt requesting device is provided. 2. Each of the interrupt request devices comprises an interrupt request circuit, an interrupt status display circuit, an interrupt permission detection circuit,
It has an interrupt state detection circuit, an interrupt pending count storage circuit, an interrupt determination circuit, and an interrupt instruction circuit. The interrupt instruction circuit issues an interrupt instruction, and the interrupt permission detection circuit detects interrupt permission from the interrupt permission line. However, when the number of interrupts from the interrupt pending count storage circuit is a certain number or more,
The information processing apparatus according to claim 1, wherein the interrupt processing of the own apparatus is prioritized regardless of the state of the interrupt display line. 3. The interrupt determination circuit prioritizes the interrupt processing of the lower interrupt request device when the number of times of holding from the interrupt holding number storage circuit is 0, and when the number of holding is 1, The information processing apparatus according to claim 1, wherein the interrupt processing is prioritized.