JPH05314057A - Information processor - Google Patents

Abstract

PURPOSE:To perform efficient interruption processing by making interruption uniform among interruption request devices. CONSTITUTION:This information processor successively and serially connecting an interruption controller and plural interruption request devices is provided with interruption judge circuits 260, 360 and 460 to instruct interruption permission detection circuits 230, 330 and 430 for transmitting the permission of interruption to the other interruption request device when the other interruption request device is under requesting the interruption and the number of times for holding the interruption is less than the manually instructed number of times even while the interruption is just requested, when the the permission of interruption is detected by the interruption permission detection circuits 230, 330 and 430, and to decide the execution of interruption under requesting even while the other interruption request device is just under interruption requesting, when the interruption is just requested and the number of times for holding the interruption is equal to the manually instructed number of times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus in which an interrupt control device and a plurality of interrupt requesting devices are sequentially connected in a sloppy manner by an interrupt enable signal line.

[0002]

2. Description of the Related Art In a conventional information processing apparatus of this type,
If multiple interrupt requesters make interrupt requests at the same time and the interrupt controller allows interrupts, the interrupt request device that is closest to the interrupt controller interrupts. An interrupt requesting device connected farther than the requesting device will have to wait for an interrupt. If the operating rate of the information processing device increases, the more interrupt requests are generated, and the farther the interrupt request device is from the interrupt control device, the more the interrupt request device waits for an interrupt. An interrupt requesting device close to the device made an interrupt when the device did not interrupt.

[0003]

In this conventional information processing apparatus, since the interrupts are biased toward the interrupt requesting device close to the interrupt control device, the interrupt processing is not efficient. Therefore, it is an object of the present invention to provide an information processing device that performs efficient interrupt processing by equalizing interrupts that are biased to interrupt request devices close to the interrupt control device.

[0004]

The apparatus of the present invention is an information processing apparatus in which an interrupt control device and a plurality of interrupt request devices are sequentially connected in a sloppy manner by an interrupt enable signal line. The interrupt control device has an interrupt request detection means for detecting that the interrupt request device is making an interrupt request, and an interrupt permission means for permitting an interrupt when the interrupt request detection means detects an interrupt request. In addition, each of the interrupt requesting devices makes an interrupt request to the interrupt control device, an interrupt request display device that indicates to the interrupt requesting device that an interrupt request is in progress, and the interrupt requesting device. When an instruction is made by the permitting means or the interrupt request device of the preceding stage to convey the interrupt permission, the interrupt permission is transmitted to the interrupt request device of the next stage. An interrupt status detecting means for detecting that an interrupt request is being made by the output means and the interrupt status display means of the interrupt requesting device at the next stage; Interrupt is not performed when it detects the interrupt, the interrupt hold number storage means for storing the number of times the interrupt of its own device was held because the interrupt permission was transmitted to the interrupt request device of the next stage, and the number of times the interrupt is held manually is set, When the interrupt permission is detected by the interrupt permission detecting means for instructing the set number of times of holding and the interrupt permission detecting means, if an interrupt request is not being made, the interrupt request device of the next stage is notified of the interrupt permission. Instructing the interrupt permission detecting means, or during the interrupt request and when the interrupt request device at the next stage is not the interrupt request, and If the number of times stored in the hold number of times storage means is less than the number of times instructed by the number-of-holds instruction means, the interrupt being requested is executed, or the interrupt requesting device at the next stage is making an interrupt request. If an interrupt request is made and the number of times stored in the interrupt holding number storage means is less than the number of times indicated by the holding number instruction means, the interrupt request is transmitted to the interrupt requesting device in the next stage. The instruction to the permission detection means, or the number of times during the interrupt request and stored in the interrupt pending frequency storage means,
If the number of times the instruction is given by the number-of-holds instruction means is equal to the number of times of interruption, it has an interruption judgment means for judging whether to execute the requested interruption regardless of whether or not the interruption requesting device at the next stage is making an interruption request. It is characterized by

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

Referring to FIG. 1, which is a block diagram of an information processing apparatus according to an embodiment of the present invention, the information processing apparatus includes an interrupt control device 100 for controlling an interrupt and three interrupt requesting devices 200 for performing an interrupt. , 300 and 40
It consists of zero.

The interrupt control device 100 has an interrupt request detection circuit 110 and an interrupt permission circuit 120, and each interrupt request device has the same configuration.
0,410 and interrupt status display circuits 220,320,4
20 and interrupt permission detection circuits 230, 330, 430
An interrupt state detection circuit 240, 340, 440, an interrupt hold number storage circuit 250, 350, 450, an interrupt determination circuit 260, 360, 460, an interrupt instruction circuit 270, 370, 470, and a hold number instruction circuit 280. ，
380 and 480.

Interrupt request device 200, 300 or 40
0, when an interrupt request is generated, the interrupt request circuit 211, 311 or 411 requests an interrupt by setting the interrupt request line 211 to "1", and as a result, the interrupt request detection circuit 110 interrupts. Detect what is requested.

At this time, when the interrupt control device 100 determines that the interrupt can be permitted, the interrupt permission circuit 120
However, the interrupt is permitted by setting the interrupt permission line 121 to "1". The interrupt permission detection circuit 230 detects that the interrupt permission is given.

When an interrupt request is generated in the interrupt request device 300, the interrupt status display circuit 320
By setting the interrupt status display line 321 to “1”, it indicates to the interrupt request device 200 that the interrupt request device 300 is requesting an interrupt. At this time, the interrupt state detection circuit 24
0 detects that an interrupt request is being made.

When the interrupt request device 200 is requesting an interrupt,
Further, when the interrupt permission detection circuit 230 detects the interrupt permission, the interrupt is not performed and the interrupt request is transmitted to the interrupt requesting device 300. Therefore, when the own interrupt is held, the interrupt permission detection circuit 230 sets the interrupt hold line 231 to “1”. 0 '→
By setting “1” → “0”, it is notified to the interrupt holding frequency storage circuit 250 that the interrupt is held.

The number-of-holds instruction circuit 280 indicates the number of times an interrupt set manually is to be held, the number-of-holds instruction line 281.
Indicate. The interrupt pending frequency storage circuit 250 counts the number of times that the interrupt pending line 231 changes from “0” to “1” to “0”, and stores it as the number of interrupt pending times.

The operation of this embodiment will be described below for each case shown in FIG. In addition, in FIG. 2, “*” is “0”.
Alternatively, "1" and "L" represent the number of times the interrupt request device holds the interrupt, which is instructed by the hold number instruction circuit.

(1) When the interrupt permission detection circuit 230 detects the interruption permission, the interruption permission detection line 232 is set to "1", and the interruption instruction circuit 27 for instructing the interruption request.
0 does not indicate an interrupt, so the interrupt instruction line 27
If 1 is set to “0”, the interrupt determination circuit 260, which determines whether or not to perform the interrupt, changes the interrupt hold instruction line 261 from “1” to “0”, and thus the interrupt permission detection circuit 230. To notify the interrupt request device 300 of the interrupt permission. At this time, the interrupt permission detection circuit 230 transfers the interrupt permission to the interrupt request device 300 by changing the interrupt permission line 122 from “0” to “1”.

(2) The interrupt permission detection circuit 230 has not detected the interrupt permission, the interrupt permission detection line 232 is set to "0", and the interrupt instruction circuit 27 for instructing the interrupt request is issued.
If 0 sets the interrupt instruction line 271 to "1", the interrupt request device 200 waits for an interrupt.

(3) The interrupt permission detection circuit 230 detects the interrupt permission, the interrupt instruction circuit 270 instructs the interrupt, and the interrupt normal state detection circuit 240 has not detected the interrupt request of the interrupt request device 300. At this time, if the number of holding times indicated by the interrupt holding number display line 251 is less than the number of holding the interrupt indicated by the holding number instruction circuit 280, the interrupt requesting device 200 executes the interrupt.

(4) The interrupt permission detection circuit 230 detects the interrupt permission, the interrupt instruction circuit 270 instructs the interrupt, and the interrupt state detection circuit 240 detects the interrupt request of the interrupt request device 300, When the interrupt status detection line 240 is set to "1", the interrupt hold count display line 25
The number of holding times indicated by 1 is the number of holding times instruction circuit 280.
Less than the number of pending interrupts indicated by
The permission is transmitted to the interrupt request device 300.

(5) and (6) Interrupt enable detection circuit 2
30 detects the interrupt permission, and the interrupt instruction circuit 27
0 indicates an interrupt, and the interrupt hold count display line 25
The number of holding times indicated by 1 is the number of holding times instruction circuit 280.
If it is equal to the number of times that the interrupt designated by the
Regardless of whether "41" is "0" or "1", the interrupt request device 20 is not notified to the interrupt request device 300 and the interrupt request device 20
0 executes an interrupt.

[0019]

As described above, according to the present invention, in an information processing apparatus in which interrupt request signals close to the interrupt control device are sequentially connected in a manner that produces interrupt enable signals, interrupt requests whose interrupts are close to the interrupt control device. Since the devices are not biased, efficient interrupt processing can be realized as an information processing device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment shown in FIG.

[Explanation of symbols]

 100 interrupt control device 110 interrupt request detection circuit 120 interrupt permission circuit 200,300,400 interrupt request device 210,310,410 interrupt request circuit 220,320,420 interrupt state display circuit 230,330,430 interrupt permission detection circuit 240,340 , 440 Interrupt state detection circuit 250, 350, 450 Interrupt hold number storage circuit 260, 360, 460 Interrupt determination circuit 270, 370, 470 Interrupt instruction circuit 280, 380, 480 Hold number instruction circuit

Claims (1)

[Claims] 1. An information processing apparatus in which an interrupt control device and a plurality of interrupt request devices are sequentially connected in a sloppy manner by an interrupt enable signal line, wherein the interrupt control device is the interrupt request device. Has an interrupt request detecting means for detecting that the interrupt request is detected, and when the interrupt request detecting means detects an interrupt request, it has an interrupt permitting means for permitting an interrupt. An interrupt request means for making an interrupt request to the interrupt control device, an interrupt status display means for indicating to the interrupt request device in the preceding stage that an interrupt request is being made, and the interrupt permission means or the interrupt request device in the preceding stage. , An interrupt permission detecting means for transmitting the interrupt permission to the interrupt requesting device of the next stage when instructed to transmit the interrupt permission, and the interrupt of the next stage. An interrupt status detecting means for detecting that an interrupt request is made by the interrupt status display means of the requesting device; and an interrupt is not made when an interrupt request is made and the interrupt enable detecting means detects an interrupt enable, An interrupt hold number storage means for storing the number of times the own device interrupt is held because the interrupt request was transmitted to the interrupt requesting device at the next stage, and the number of times to hold the interrupt manually is set, and the set number of holding times is instructed. When the interruption permission is detected by the pending count instruction means and the interruption permission detection means, if the interruption request is not being made, the interruption permission detection means is instructed to convey the interruption permission to the interruption requesting device at the next stage, or Stored during the interrupt request, and when the interrupt request device of the next stage is not an interrupt request, and the interrupt pending count storage means If the number of times the request is made is less than the number of times indicated by the hold number instruction means, the interrupt being requested is executed, or the interrupt request is being made and the interrupt requesting device at the next stage is making an interrupt request and the interrupt is being made. If the number of times stored in the number-of-holds storage means is less than the number of times instructed by the number-of-holds instruction means, the interrupt permission detection means is instructed to notify the interrupt permission to the interrupt request device in the next stage, Alternatively, if an interrupt request is made and the number of times stored in the interrupt hold count storage means is equal to the number of times specified by the hold count instruction means, the interrupt request device at the next stage is making an interrupt request. An information processing apparatus characterized by having an interrupt determination means for determining that a requested interrupt will be executed regardless of whether or not the interrupt is requested.