JPH06133192A - Video diplay device - Google Patents

Abstract

PURPOSE:To provide the video display device in which no deviation in displayed pictures is caused between both display modes even when display mode displaying directly video data from a video camera onto a display device or a display mode storing video data from the video camera once into a video memory, reading the video data from the video memory and displaying the video data onto the display device. CONSTITUTION:Video data from a video camera 18 inputted to a serial port in a storage area in a video memory 15 designated by an address generated at one preceding horizontal line period from an address generating section 2 are transferred in the write mode. The video data are transferred from the storage area in the video memory 15 designated by the address generated from the address generating section 2 in the read mode to the serial port to display the video data from the video memory 15 onto the display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display mode in which video data from a video camera is directly displayed on a display device, and video data from the video camera is temporarily stored in a video memory and then read from the video memory. The present invention relates to a video display device capable of switching a display mode displayed on a display device.

[0002]

2. Description of the Related Art Recently, a multi-port RAM (MP having a serial port and a RAM port as a video memory
RAM) is increasingly used. MPRA
In M, writing or reading of video data is performed only by applying a serial clock after data transfer to the serial port. For this reason,
The use of MPRAM as a video memory has an advantage that it can be used for a long time for access on the random port side, and is effective for a video display device that requires high-speed processing.

Generally, a CRT controller is often used as an address generation circuit for generating an access address of MPRAM. A general method of using the MPRAM is to use the display address output from the CRT controller to generate and access a transfer cycle to the serial port of the MPRAM at the beginning of the video display period of the horizontal synchronizing signal. is there.

[0004]

When video data is read from the MPRAM and displayed on a display device such as a CRT, a read transfer cycle is executed at the beginning of the video display period and is designated by the display address generated by the address generation circuit. One row of data is transferred from the storage area in the RAM port to the serial port. Thereafter, the video data is read from the serial port in synchronization with the serial clock and displayed on the display device.

Video data from a video camera is MPRA
When writing to M, a write transfer cycle is executed at the beginning of the video display period, and one row of data is transferred from the serial port to the storage area in the RAM port designated by the display address generated by the address generation circuit. .

However, in the case of the write transfer cycle, the video data transferred from the serial port to the RAM port is the video data one horizontal line before input to the serial port in synchronization with the serial clock before the write transfer. Therefore, in the case of a write transfer cycle, 1
Video data before horizontal line is sent from serial port to RAM
Forwarded to the port. Therefore, comparing the direct display of the video data from the video camera with the display of the video data read from the MPRAM after the video data is written in the MPRAM, it can be seen that the video data is on the same horizontal line. Also, the display of the video data from the MPRAM is displayed one horizontal line below the display of the video data from the video camera.

Therefore, in the video display device in which the display of the video data from the video camera is switched back and forth (through display) and the display of the video data from the MPRAM is frequently switched, even if the same image is displayed on the display device, a display image is displayed. It is very difficult to see because there is a gap in Also, MP
Since the video data is input to the RAM with a shift of one horizontal line, the accuracy of calculation and processing after the input is adversely affected.

According to the present invention, the display mode in which the video data from the video camera is directly displayed on the display device and the video data from the video camera are temporarily stored in the video memory.
An object of the present invention is to provide a video display device in which even if a display mode in which video data is read from a video memory and displayed on a display device is switched, a display image does not shift between the display modes.

[0009]

A video display device according to the present invention includes a video camera, a serial port, a video memory for storing video data from the video camera, and an address generation for generating an access address of the video memory. In a video display device including a display section and a display device, a read mode for reading video data from the video memory and displaying the video data on the display device, and a write mode for writing data from the video camera to the video memory. In the write mode, the mode switching means for switching between and is input to the serial port in a storage area in the video memory designated by an address generated one horizontal line period before from the address generation unit. A means for transferring video data from a video camera, the read mode At this time, the video data from the video memory is displayed on the display device by transferring the video data from the storage area in the video memory specified by the address generated by the address generation unit to the serial port. First display control means, second display control means for displaying the video signal from the video camera directly on the display device without sending it to the video memory, and a display mode by the first display control means and the second display control means. It is characterized by comprising display mode switching means for switching the display mode by the display control means.

[0010]

In the writing mode, one horizontal line before from the video camera input to the serial port is stored in the storage area in the video memory specified by the address generated one horizontal line before from the address generator. Image data of is transferred. Therefore, the video data is stored in the video memory without shifting by one horizontal line. In the read mode, video data is transferred to the serial port from the storage area in the video memory designated by the address generated by the address generator. Thereafter, the video data is output from the serial port in synchronization with the serial clock, and the video data from the video memory is displayed on the display device.

As described above, since the video data is stored in the video memory without being shifted by one horizontal line, the video data from the video camera is directly displayed on the display device.
Even if the display mode by the display control means and the display mode by the first display control means for temporarily storing the video data from the video camera in the video memory and reading the video data from the video memory and displaying it on the display device are switched. The display images in both display modes are not displaced, and an image that is easy to see can be obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the structure of a video display device.

In this image display device, the CCD camera 18
It is possible to switch between a display mode for displaying the video data from the CRT 22 and a display mode for displaying the video data from the video memory 15 on the CRT 22. The video display device is controlled by a central processing unit (CPU) 1.

The video memory 15 is a multiport R
AM (MPRAM) is used, and as shown in FIG. 2, it is composed of a dynamic RAM (RAM port) 51, a serial access memory (SAM port) 52 and a row address decoder 53. All operations of the SAM port 52 are executed in synchronization with the serial clock SC. At the time of serial read, as shown in FIG. 4, a definite output is obtained in synchronization with the rising edge of the serial clock SC. At the time of serial write, as shown in FIG. 5, the serial input data is latched by the rising edge of the serial clock SC and written to the SAM port 52.

The register 3 is accessed by the CPU 1 and outputs a transfer mode selection signal (mode selection signal) SEL to the video memory 15. Mode selection signal SE
Video memory 1 when L is at L level (SEL = L)
5 is a read transfer mode in which video data is transferred from the RAM port 51 to the serial port 52, and when the mode selection signal SEL is at the H level (SEL = H), write transfer is performed to transfer the video data from the serial port 52 to the RAM port 51. It becomes a mode.

The CRT controller 2 has a horizontal synchronizing signal * HSYNC, CRT22 for horizontally synchronizing the CRT 22.
Vertical sync signal * VSYNC to apply vertical sync to the screen, timing signal * DISP indicating the display period of the screen, video memory 1
Address strobe signal * AS indicating the timing of latching the address of 5, the signal * TRAN indicating the transfer cycle in which the video memory 15 performs the transfer operation, the signal * DRAW indicating the drawing cycle, and the signal indicating the address of the video memory 15.
Generate AD. A time chart of the output signal of the CRT controller 2 is shown in FIG.

One horizontal line period, which is one cycle of the horizontal synchronizing signal * HSYNC, includes a horizontal blanking period, a horizontal back porch, a display period, and a horizontal front porch period. There is one display period in one horizontal line period, and one horizontal line worth of data is RA during the display period in the read transfer mode.
The data is transferred from the M port 51 to the SAM port 52, and then the data of the SAM port 52 is sequentially output by the serial clock SC. In the write transfer mode, the video signal written in the SAM port 52 is R during the display period.
It is transferred to the AM port 51. That is, in both the read transfer mode and the write transfer mode, one transfer cycle occurs in one horizontal period.

The timing generator 4 outputs the output signals * HSYNC, * DISP, * AS, * TRAN and * D of the CRT controller 2.
Based on RAW and the output signal SEL of the register 3, the memory control signal of the video memory 15 and the address selection signal SEL1 are output. As the memory control signal, as shown in FIGS. 4 and 5, the row address strobe signal * RA is used.
There are S, column address strobe signal * CAS, data transfer / output enable signal * DT / OE and write enable signal * WB / WE, and these signals are sent to the video memory 15. Data transfer / output enable signal * D at the falling edge of row address strobe signal * RAS
If T / OE is at L level, it becomes a data transfer cycle, and if the data transfer / output enable signal * DT / OE is at H level at the falling timing of the row address strobe signal * RAS, it operates as output enable. If the write enable signal * WB / WE is at the L level at the falling timing of the row address strobe signal * RAS, the write transfer cycle is started.

The address selection signal SEL1 is the signal * TRAN indicating the drawing cycle when the signal * DRAW is at the L level (* DRAW = L) or the mode selection signal SEL is at the L level (read transfer mode) and indicates the transfer cycle. At L level (SEL
= L and * TRAN = L). When the mode selection signal SEL is at H level (write transfer mode) and the signal * TRAN indicating the transfer cycle is at L level (SEL = H
and * TRAN = L), the address selection signal SEL1
Becomes H level. The address selection signal SEL1 is input to the selection input terminal of the multiplexer 10. Further, the address selection signal SEL1 is input to the selection input terminal of the multiplexer 11 via the inverter 6.

The latch circuit 7 converts the address signal AD output from the CRT controller 2 into an address strobe signal.
* Latch at the falling edge of AS. The address signal AD latched by the latch circuit 7 is sent to the multiplexer 1
When it is 0, the row and column addresses are multiplexed, and when the address selection signal SEL1 is at L level (SE
L1 = L), which is sent to the video memory 15. That is, during the drawing cycle or the read transfer cycle, the address signal AD output from the CRT controller 2 is sent to the video memory 15 as it is.

The latch circuit 8 outputs the address signal AD output from the CRT controller 2 when the timing signal * DISP indicating the display period is L level and the signal * TRAN indicating the transfer cycle is L level (* DISP = L. and * TRAN
= L) Latch at the rising edge of address strobe signal * AS. Address signal AD latched by the latch circuit 7
Is sent to the latch circuit 9 in the next stage. The latch circuit 9 is
For the address signal AD output from the latch circuit 8, when the timing signal * DISP indicating the display period is L level and the signal * TRAN indicating the transfer cycle is L level (* DISP = L
Latch at the falling edge of the address strobe signal * AS of and * TRAN = L).

Address signal latched by the latch circuit 9
AD is a multiplexer 11 for row address and column
Address is multiplexed with address selection signal SEL1
Is at the H level, that is, the mode selection signal SE is at the H level and the signal * TRAN indicating the transfer cycle is at the L level (SEL = H and * TRAN = L). That is, in the write transfer cycle, the address signal AD output from the CRT controller 2 one horizontal line period before, that is, the address signal AD one horizontal line before is sent to the video memory 15.

The output of the oscillation circuit 13 is frequency-divided by the frequency dividing circuit 12 and then sent to the serial clock generator 14. The serial clock SC is output from the serial clock generator 14. The serial clock SC is sent to the video memory 15 and this serial
Video signal at video rate of clock SC Video memory 1
5 or output from the video memory 15.

The analog data input from the CCD camera 18 is converted into digital data by the A / D converter 19 and sent to the driver 16 and the selector 20. A mode selection signal is sent to the driver 16 via the inverter 5.
SEL is input as a control signal. Mode selection signal SE
When L is at H level (SEL = H), the driver 16 is enabled and the digital data output from the A / D converter 19 is sent to the SAM port 2 of the video memory 15.

The mode selection signal SEL is also sent to the driver 17 as a control signal. When the mode selection signal SEL is at L level (SEL = L), the driver 17 is enabled and the data from the video memory 15 is sent to the selector 20. The selector 20 is the CCD camera 18
The display is switched between the through display and the data display from the video memory 15.

The video data output from the selector 20 is sent to the video control unit 21. The video control unit 21 D / A converts the input digital data into analog data, superimposes the horizontal synchronizing signal * HSYNC and the vertical synchronizing signal * VSYNC, and outputs it to the CRT 22.
As a result, the video data selected by the selector 20 is displayed on the CRT 22.

FIG. 4 shows the MP in the read transfer cycle.
6 is a timing chart showing the operation of the RAM 15. In the read transfer cycle, the data for one row address stored in the address of the RAM port 51 designated by the address signal AD output from the multiplexer 10 is transferred to the SAM port 52. After that, the video data of the SAM port 52 is output in synchronization with the serial clock SC.

FIG. 5 is a timing chart showing the operation of the MPRAM 15 in the write transfer cycle. In the write transfer cycle, the address of the RAM port 51 designated by the address signal AD one horizontal line before output from the multiplexer 11 is set to SA.
The video data one horizontal line before, which is held in the M port 52, is transferred.

In the above embodiment, since the address of one horizontal line before is given to the MPRAM 15 in the write transfer mode, the video data is stored in the video memory 15 without being shifted by one horizontal line. Therefore, the display mode in which the video data from the video camera 18 is directly displayed on the CRT 22 and the video data from the video camera 18 are temporarily stored in the video memory 15 and then the video memory 15
Even if the display mode in which the video data is read from and is displayed on the CRT 22 is switched, the images on both sides do not shift, and an easy-to-see image is obtained.

[0030]

According to the present invention, the display mode in which the video data from the video camera is directly displayed on the display device, and the video data from the video camera is temporarily stored in the video memory and then the video data is read from the video memory. Even when the display mode displayed on the display device is switched, the display images in both display modes do not shift, and an easily viewable image can be obtained.

[Brief description of drawings]

FIG. 1 is an electrical block diagram showing a configuration of a video display control device.

FIG. 2 is an electrical block diagram showing a configuration of MPRAM.

FIG. 3 is a time chart showing an output signal of a CRT controller.

FIG. 4 shows MPRA in a read transfer cycle.
7 is a time chart showing the operation of M.

FIG. 5 shows MPRA in a write transfer cycle.
7 is a time chart showing the operation of M.

[Explanation of symbols]

 1 CPU 2 CRT controller 3 Register 4 Timing generator 7, 8, 9 Latch circuit 10, 11 Multiplexer 14 Serial clock generator 15 Video memory 18 CCD camera 20 Selector 21 Hide control unit 22 CRT 51 RAM port 52 SAM port 53 Low・ Address decoder

Claims (1)

[Claims] 1. A video display device comprising a video camera, a video memory having a serial port for storing video data from the video camera, an address generator for generating an access address of the video memory, and a display device, Mode switching means for switching between a read mode for reading video data from the video memory and displaying it on the display device and a write mode for writing data from the video camera to the video memory, in the write mode At the address generator 1
Means for transferring video data from the video camera input to the serial port to a storage area in the video memory specified by an address generated before a horizontal line period, the address generation in the read mode First display control means for displaying the video data from the video memory on the display device by transferring the video data from the storage area in the video memory designated by the address generated from the section to the serial port. A second display control means for displaying the video signal from the video camera directly on the display device without sending it to the video memory, and a display mode by the first display control means and a display mode by the second display control means. A video display device comprising display mode switching means for switching between and.