JPH0614068B2 - Delayed sweep device - Google Patents

Description

The present invention relates to an oscilloscope delay sweep device for observing a waveform of a high-speed electrical phenomenon.

In an oscilloscope, a delayed sweep device is used for precisely observing two time-delayed portions of an observed waveform, but the present invention provides an improved delayed sweep device.

[Prior Art] An example of a conventional delayed sweep device (Japanese Patent Publication No. 54-15503)
Is shown in FIG. 3 and will be described.

In FIG. 3, 11 is for sweeping the observed waveform,
It is a main sweep circuit that generates a sawtooth wave. When a trigger synchronized with the waveform to be observed is applied to the trigger input terminal 12, this main sweep circuit 11 outputs a main sweep output 14 which is a sawtooth wave to the main sweep output terminal 13 in synchronization with it. 1
Reference numeral 5 denotes a frequency divider, which is a frequency divider for dividing the sweep cycle of the main sweep circuit 11 and switching the changeover switch 22 with a frequency division output. Reference numeral 17 denotes a signal from the changeover switch 22, which is a delayed sweep circuit for outputting a delayed sweep output 19 which is a sawtooth wave delayed from the start of the operation of the main sweep circuit to the delayed sweep output terminal 18. Reference numerals 12A and 21B denote a first comparator and a second comparator, respectively, to which the main sweep output 14 is applied to one terminal, and potentiometers 26A and 2A to the other terminal, respectively.
The reference voltage from 6B is applied. Main sweep output 14
The first and second comparators 21A and 21B respectively output when the voltage exceeds the reference voltage. Two
Reference numeral 3 denotes a digital voltmeter for reading the difference between the two reference voltages of the potentiometers 26A and 26B, the output of which is the sweep rate of the main sweep circuit 11 in the digital display circuit 24 (the rising rate of the sawtooth wave 14). Is multiplied and displayed.

In an oscilloscope having a delay sweep circuit having such a configuration, a pulse train is currently displayed on the tube surface. For example, when observing the rising portion of the Nth pulse of the pulse train, the potentiometer 26A is used. When the amount is adjusted while observing the surface, the first comparator 21A operates at a point corresponding to the Nth pulse of the main sweep output 14, and its output passes through the changeover switch 22 and the delay sweep circuit 1
Since 7 is operated to obtain the delayed sweep output 19, the rising portion of the Nth pulse can be displayed simultaneously with the display of the pulse train by the operation of the main sweep circuit 11. Similarly, when the potentiometer 26B is adjusted while observing the rising portion of the N + 1th pulse of the pulse train, the second point is obtained at the point corresponding to the N + 1th pulse of the main sweep output 14.
The comparator 21B operates, and its output operates the delay sweep circuit 17 via the changeover switch 22 to obtain N + 1.
The rising portion of the Nth pulse can be superimposed and displayed on the rising portion of the Nth pulse.

By operating in this way, it is possible to observe a total of three waveforms of the pulse train by the main sweep, the rising portion of the Nth pulse and the rising portion of the N + 1th pulse by the delayed sweep.

These three waveforms are swept and displayed on alternate tube surfaces according to the order of switching of the selector switch 22 by the output from the frequency divider 15.

Here, when the position of the rising portion of the N-th pulse and the position of the rising portion of the N + 1-th pulse match on the tube surface, the digital display circuit 24 outputs the output of the digital voltmeter 23, The value multiplied by the sweep rate of the main sweep circuit 11 is displayed as the time interval between the Nth pulse and the N + 1th pulse. That is, the cycle of the pulse train is digitally displayed.

In the conventional example shown in FIG. 3, the offset voltage at the inputs of the first and second comparators 21A and 21B, the difference between the two offset voltages, and the delay time difference between the input and output fluctuate due to changes in the cycle temperature. , The delay time between the main sweep and the two delayed sweeps and between the two delayed sweeps varied, and an error occurred. Moreover, the circuit becomes complicated because two high-speed comparators (21A, 21B) are required, and the digital voltmeter 23 is required, so that it is inevitable that the price becomes high.

In order to solve such a problem, a delay sweep device as shown in FIG. 4 is used. In FIG.
31A and 31B are a first D / A converter and a second D / A converter, respectively. When data is input to 32A and 32B, the data is input to the first and second D / A converters 31 as first and second delay data 35A and 35B, respectively.
A first shift register and a second shift register for applying to A and B.

In the example shown in FIG. 4, in place of the potentiometers 26A and 26B shown in FIG.
A reference voltage is generated by the / A converters 31A and 31B, which is switched by the changeover switch 22 and applied to the comparator 21.

In FIG. 4, since there is one comparator,
The fluctuation factor due to the comparator is eliminated, and further, without using the expensive digital voltmeter 23 (FIG. 3),
From the data to the first and second shift registers 32A and 32B, the time difference between the two delay sweeps is calculated and displayed (the digital display circuit 24 is omitted in FIG. 4).

[Problems to be Solved by the Invention] The conventional example shown in FIG. 4 solves some of the problems of the conventional example shown in FIG. However, significant unsolved problems remain.

The problem is that the first and second D / A in FIG.
This is the difference in the characteristics of the converters 31A and 31B. The first and second D / A converters 31A and 31B are required to have a resolution of 12 bits to 16 bits, and it is extremely difficult to prepare the ones having the same characteristics with respect to the change in the ambient temperature, and it is expensive. It was also a big factor.

Such a difference in characteristics will be described with reference to FIG.

The X-axis of the figure shows the value of input data, and the Y-axis shows the delay time of two delay sweeps determined by the output voltage of the D / A converter.

The line 50 shows that the offset voltage of the D / A converter is zero, and the output voltage is generated so as to faithfully generate the delay time with respect to the input of data.

On the other hand, the lines 51 and 52 show cases where negative and positive offset voltages are generated, respectively.

The dotted line 53 shows the case where the offset voltage is zero but the gain of the D / A converter has an error.

Here, for example, the output characteristic of the first D / A converter 31A receiving the output of the first shift register 32A is represented by the line 51, and the data of 4 (mS) is input to the second shift register. The output characteristic of the second D / A converter 31B receiving the output of 32B is represented by the line 52 and is 5 (m
S), the difference between the inputted data is 1 (mS), as shown at points A and B in FIG. 2D /
Due to the offset of the output voltage of the A converters 31A and 31B, the delay time difference becomes 2 (mS).

As is apparent from FIG. 5, the error rate ratio of the delay times of the offset voltages of the first and second D / A converters 31A and 31B is larger as the data value is smaller.

However, the first and second D / A converters 31A, 3
If there is an error in the gain of either or both of 1B, the ratio of the error is constant (the slope is constant) as indicated by the dotted line 53, so there is no problem as caused by the offset voltage.

In the conventional example shown in FIG. 4, since two D / A converters are used, the difference in the characteristics causes an error, and since two characteristics are used as much as possible, it is expensive. It became a thing.

This difference in characteristics and the error in D / A conversion are also caused by the temperature characteristics of both D / A converters, and there is a problem in that those with well-matched temperature characteristics become more expensive.

[Means for Solving Problems] The present invention has been made to solve the problems of the conventional art.

Therefore, in the present invention, in the circuit shown in FIG.
A calibration comparator that compares the output of the D / A converter and the output of the second D / A converter, and the output of this calibration comparator, receives the calculation processing, and the output of this calibration comparator becomes zero. A first processing circuit for applying the first delay data and the second delay data to the first shift register and the second shift register to process the data at this plot point; A random access memory (RAM) for determining and storing at the plot points was provided.

[Function] Prior to measurement using the delay sweep device, the first delay data and the second delay data such that the output of the calibration comparator becomes zero.
The delay data is obtained at a plurality of plot points in the dynamic range of the first and second D / A converters, the correction processing is performed by calculating the delay data, and the correction coefficient is stored in the RAM. A first delay time to the start point of the first delayed sweep waveform that is output based on the output of the / A converter, and a second delay that is output from the start point of the main sweep waveform to the output of the second D / A converter When obtaining the second delay time up to the start point of the sweep waveform, the corrected data that does not cause an error in the first and second D / A converters via the first and second registers is calculated based on the correction coefficient. It was applied.

If this correction coefficient is plotted at many points in the dynamic range of the first and second D / A converters, the accuracy of correction can be improved to any extent.

Therefore, it is not necessary to use two expensive D / A converters having uniform characteristics, and it is possible to realize a highly accurate delay sweep device.

[Embodiment] An embodiment of the present invention will be described with reference to FIG. Here, parts corresponding to those shown in FIGS. 3 and 4 are shown by using the same numbers or symbols. Also the first
FIG. 2A is a waveform diagram for explaining the operation of what is shown in FIG.
A flowchart showing the flow of the operation is shown in FIG. 2C in FIG. 2 and FIG. 2B.

In FIG. 1, the main sweep circuit 11 has a trigger input terminal 12
The main sweep output 14 (Fig. 2A (b)) is connected to the main sweep output terminal 13 in synchronization with the trigger (Fig. 2A (a)) applied to the
To get

Inside the main sweep circuit 11, a main sweep gate 41 (FIG. 2A (e)) for generating the main sweep output 14 is formed, and this is applied to the frequency divider 15. The main sweep gate 41 (e) is divided into 1/4 by the frequency divider 15 and outputs a frequency division output 42 (FIG. 2 (f)).

The first delay time T ₁ (see FIG. 2A (b)) and the second delay time T ₂ (see FIG. 2A (b)), which are the delay times from the start point of the main sweep output 41 (b), are When the calculation processing circuit 36 including a processor outputs, for example, 24 bits of serial data, the upper 12 bits thereof are stored in the shift register 32A as the lower 1 bits.
The 2 bits are stored in the shift register 32B. The shift registers 32A and 32B use the first and second D / A converters 31A and 3A as the first delay data 35A and the second delay data 35B, respectively.
Sent to 1B. When the first delay data 35A is applied, the first D / A converter 31A outputs the first delay voltage V ₁
When the second delay data 35B is applied,
The D / A converter 31B outputs the second delay voltage V ₂ to the first and second D / A outputs 43A and 43B shown in FIG. 2A (d) (only the D / A output 43 is shown in FIG. 2A (d)). (Described) is simultaneously output to the calibration comparator 28 and is also applied to the delay sweep reference comparator 27 via the changeover switch 22.

The comparator 27 has a main sweep output 14 at one of its terminals.
(B) is applied to the other terminal, and the first delay voltage V ₁ or the second D / A output 43A, B (d) or the second delay voltage V ₁ is applied to the other terminal.
Since the delay voltage V ₂ is applied, the main sweep output 14
The voltage of (b) is the first delay voltage V ₁ or the second delay voltage V 1.
When the value exceeds ₂ , the delay sweep reference comparator 27 operates to operate the delay sweep circuit 17, and the first delay sweep output 19 corresponding to the first or second delay voltage V ₁ or V _2.
A or the second delayed sweep output 19B (FIG. 2A (c)) is output to the delayed sweep output terminal 18.

The main sweep output 14, the first delayed sweep output 19A, and the second delayed sweep output 19B thus obtained are applied to a sweep amplifier (not shown) and selected by a switch, and the result is shown in FIG. 2A (g). Amplified as the swept waveform shown in (4) is applied to the X axis of the cathode ray tube.

In the example shown in FIG. 2A, the frequency divider 15 is the main sweep gate 4
1 (e) is divided into 1/4, and after the divided output 42 (f) which is the output of the divider 15 changes, the main sweep is first selected as the sweep waveform (g). Output 14
Then, the first or second delayed sweep output 19A or 19B is selected. By doing so, the first or second D / A converter 31A or 31B
The first or second D / A output 43A, 43B generated in a stable state, the first or second delayed sweep output 19A,
This is because 19B can be selected as the sweep waveform (g).

Such a state becomes a problem during high-speed sweep, which will be described with reference to FIG. 2B.

When the main sweep output 14 reaches a peak in FIG. 2B (b), the first and second D / A outputs 43A, B (d) shift from the first delay voltage V ₁ to the second delay voltage V ₂ , for example. However, the settling time required for the transition is 1 μS in the D / A converter having a high precision as used in the embodiment.
The ringing as shown in FIG. 2B (d) may continue after that, but the first and second D / A
The first or second delayed sweep output 19A, 19B immediately after the output 43A, B is switched is not used as the sweep waveform because the first or second delayed sweep output 19A, 19B may be affected by the ringing or the like to cause an error. The main sweep output 14, which has nothing to do with the switching of the first and second D / A outputs 43A and B, is used as the sweep waveform immediately after the switching (see FIG. 2A (g)). As is apparent from FIG. 2A, if the frequency division ratio of the frequency divider 15 is changed, in the same figure (g), the first delayed sweep output 19A is continued twice after the main sweep 14 and then the main sweep. 1
It will be apparent that the number of repetitions of each sweep output can be arbitrarily changed, such as outputting 4 and then continuing the second delayed sweep output 19B twice.

Next, through the first shift register 32A, the first D /
The first delay data 35A applied to the A converter 31A and the second delay data 35B applied to the second D / A converter 31B via the second shift register 32B will be described with reference to the flowchart of FIG. 2C. To do.

Even if the same data is input, the first and second D / A converters 31A and 31B do not always output the same output voltage due to the characteristic difference, as described in FIG. Even if the voltage is obtained, a difference occurs in both output voltages when the ambient temperature changes due to the difference in temperature characteristics. Therefore, prior to the measurement using the delay sweep device, the following work is performed to obtain a correction coefficient for correcting the error.

First, the calculation processing circuit 36 sets and sends the first delay data 35A to the first D / A converter 31A (second C).
Figure, S81).

Next, the calculation processing circuit 36 sets and sends the second delay data 35B to the second D / A converter 31B (S).
82). Based on the first and second delay data 35A and 35B, the first and second D / A converters 31A and 31B output the first and second D / A outputs 43A and 43B, respectively.
Since the voltage is applied to the calibration comparator 28, the first and second D
If there is a difference voltage between the / A outputs 43A and 43B, the calibration comparator 28 has an output (S83Y).

Since it is possible to determine whether the second D / A output 43B is larger or smaller than the first D / A output 43A from the polarity of the voltage of this output, the calculation processing circuit 36 outputs the second delay data for reducing the difference voltage. Preparation for operation to occur (S8
4). Therefore, the value of the first delay data 35A is not changed and is set to the same value as the previous time (S81).
Only B is provided with data changed so as to reduce the differential voltage (S82), and the presence or absence of the differential voltage is checked (S83). When such an operation is repeated and a difference voltage is substantially not obtained at the output of the calibration comparator 28, the values of the two first and second D / A outputs 43A and 43B match (S83).
N). Therefore, the first and second delay data at this time are RA
Store in M37.

Next, in order to plot different points (S85
Y), the new first delay data 35A is set, and the first D /
It is sent to the A converter 31A (S81). Therefore, the data equivalent to the new first delay data 35A is set to the second delay data 3
It is set as 5B and sent to the second D / A converter 31B (S82). If there is a difference voltage that is the output of the calibration comparator 28 at this time (S83Y), the preparation for the change operation of the second delay data 35B is started (S84), and the first delay data 35A is sent without change. (S8
1), only the second delay data 35B is changed to reduce the difference voltage (S82).

In this way, when the difference voltage becomes substantially zero (S83
N), the first and second delay data 35 obtained at this time
A and 35B are stored in the RAM 37.

By plotting multiple points, the first and second D / A
The first and second delay data 35A of the converters 31A and 31B,
The first and second D / A outputs 43A for the input value of 35B,
The ratio of the values of 43B, ie the line 5 in FIG.
The inclinations of 1 and 52 are calculated (S86), and the correction coefficient between the plotted points is calculated and stored in the RAM 37 (S87).

In the above, when there is a difference voltage between the first and second D / A converters 31A and 31B, the second delay data 35B is changed to obtain data in which the difference voltage becomes zero. It will be apparent that the first delay data 35A may be modified to obtain data for which the differential voltage becomes zero.

In addition, for example, delay data 35B that causes the second D / A output 43B to be zero is applied to the first D / A converter 31A.
If various first delay data 35A are given to, the output value of the calibration comparator 28 indicates the linearity of the first D / A converter. Similarly, the linearity of the D / A converter 31B can be calculated.

The correction coefficient is obtained by the above operation, and the measurement using the delayed sweep described with reference to FIGS. 2A and 2B is started. The first and second delay data 35A and 35B used in this measurement are corrected by the correction coefficient. Since the operation for obtaining the correction coefficient is performed for each measurement, the measurement can be performed without being affected by the temperature change.

[Effects of the Invention] As is clear from the above description, since the D / A converter, which is the main factor of the delay time difference error, is automatically corrected immediately before measurement, it is not affected by temperature changes and is inexpensive. D /
With the A converter, a highly accurate delay sweep device of an oscilloscope can be realized. Therefore, the effect is extremely large.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIGS. 2A and 2B are waveform diagrams for explaining the operation of the circuit configuration shown in FIG. 1, and FIG. 2C is a correction coefficient calculation. FIG. 3 and FIG. 4 are circuit configuration diagrams showing a conventional example, and FIG. 5 is a characteristic diagram for explaining error factors of the circuit configuration shown in FIG. . 11 ... Main sweep circuit, 12 ... Trigger input terminal 13 ... Main sweep output terminal, 4 ... Main sweep output 15 ... Divider, 17 ... Delay sweep circuit 18 ... Delay sweep output terminal 19 ... Delay sweep output 19A ... First delay Sweep output 19B ... Second delayed sweep output 21 ... Comparator 21A ... First comparator 21B ... Second comparator 22 ... Changeover switch, 23 ... Digital voltmeter 24 ... Digital display circuit 26A, B ... Potentiometer 31 ... D / A Converter 31A ... First D / A converter 31B ... Second D / A converter 32A ... First shift register 32B ... Second shift register 35A ... First delay data 35B ... Second delay data 41 ... Main sweep gate, 42 ... divided output 43 ... D / A output 43A ... first 1D / A output 43B ... second 2D / A output 50 to 52 ... line, 53 ... dotted T ₁ The first delay time, T 2 _... the second delay time V 1 _... the first delay voltage, V 2 _... the second delay voltage.

Claims (1)

[Claims] 1. A main sweep circuit for forming a main sweep gate synchronized with an observed waveform and generating a main sweep output by the main sweep gate; and the main sweep output at one input terminal of the main sweep output. The delay voltage for setting the delay time, which is the time delayed from the start time, is applied to the other input terminal, and the main sweep output applied to the one input terminal is applied to the other input terminal. And a delay sweep reference comparator that generates an output at the moment when the delay voltage is exceeded, and the start of the main sweep output is delayed by the delay time from the start of the main sweep output to start the main sweep output. In the delay sweep device of the oscilloscope for processing the data relating to the delay time and displaying a numerical value, including a delay sweep circuit for generating a delay sweep output in Frequency dividing means for frequency-dividing the main sweep gate to obtain a frequency-divided output having a predetermined frequency division ratio, and first and second frequency-division means for instructing a delay time of two kinds of values as the delay time. First D / A conversion means for receiving the delay data and outputting a first D / A output and a second D / A output respectively corresponding to the first and second delay data for designating the delay time. A second D / A conversion means, and switching for selecting the first D / A output and the second D / A output by the frequency division output and applying the selected delay voltage to the other input terminal of the sweep comparator. Switch means, a calibration comparator for comparing the first D / A output and the second D / A output, and the first delay data as a first value prior to generating the delay sweep output. First to said output of calibration comparator by changing the serial second delay data substantially becomes zero
Points are plotted, the first and second delay data at this time are stored, and at least the first value to the second value of the fixed first delay data for plotting the second point are stored. And the second delay data is changed to store the first and second delay data when the output of the calibration comparator becomes substantially zero, and the plotted first point and The first for equalizing the first and second D / A output values from the stored first and second delay data at least at a second point.
And a calculation processing means for calculating a correction coefficient for calculating the second delay data.