JPH06150652A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Object] A semiconductor integrated circuit, such as a semiconductor memory device (DRAM), having a built-in substrate bias generation circuit, which efficiently and sufficiently lowers the substrate bias even when the power supply voltage is lowered. Provided is a semiconductor integrated circuit having a substrate bias generating circuit to be supplied. [Structure] The output of an oscillation circuit 1 for driving the first charge pump circuit by further pumping the output of the first charge pump circuit by a second charge pump circuit is divided by a frequency divider circuit 2 at a half frequency. The signal is converted into an oscillating signal, and this signal drives the second charge pump circuit. Since the second charge pump circuit is driven in a cycle twice that of the first charge pump circuit, the first charge pump circuit is driven every time the operation of discharging the charge of the node 107 is completed in the first charge pump circuit. There is no loss in the second charge pump circuit because the operation of charging up the output node 107 of the circuit and the operation of absorbing the electric charge from the substrate are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a technique effective in operating a substrate bias generating circuit at a low power supply voltage in a semiconductor integrated circuit including a substrate bias generating circuit such as DRAM. is there.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit composed of MOS transistors such as DRAM, an NMO is formed in order to reduce the junction capacitance between the source / drain region of the MOS transistor and the substrate and due to noise such as undershoot.
A negative substrate voltage is applied so that the source / drain region of the S transistor and the substrate are not forward biased to cause latch-up or destroy the data in the cell. The DRAM has a built-in substrate bias generation circuit as shown in FIG.

Reference numeral 1 denotes an oscillating circuit. The oscillating circuit 1 outputs alternating currents that are complementary to each other, and the two outputs drive the charge pump circuits. One charge pump circuit is composed of a pumping capacitor 104 and P-channel MOS transistors 101 and 102 which are rectifying elements, and the other charge pump circuit is a pumping capacitor 111 and P-channel MOS transistors 108 and 109 which are rectifying elements. It is configured.

The operation of this substrate bias generation circuit will be described. The pumping capacitors 104 and 111 are driven in opposite phases by the mutually complementary alternating currents output from the oscillator circuit 1. When “H” is input to the pumping capacitor 104, the potential of the node 106 rises. At this time, “L” is input to the pumping capacitor 111 and the node 11
The potential of 3 drops. The P-channel MOS transistor 101 is turned on by the potential difference between the node 106 and the node 113, and the charge of the node 106 is discharged to VSS. Subsequently, “L” is input to the pumping capacitor 104, and the potential of the node 106 drops. At this time, “H” is input to the pumping capacitor 111 and the node 11
The potential of 3 rises, and the P-channel MOS transistor 1
01 turns off. Since the potential of the node 106 drops by the amount of charges released to the above VSS, the potential difference between the substrate and the node 106 causes the P-channel MOS transistor 102.
Is turned on, and the positive charge of the substrate is absorbed by the node 106. This operation is repeated to supply the substrate current. While one of the charge pump circuits absorbs the charge of the substrate, the other charge pump circuit discharges the excess charge to VSS, so that the substrate current with less ripple can be supplied.

[0005]

In recent years, miniaturization of devices has progressed, and in MOS transistors, the gate oxide film tends to become thinner and thinner. In ICs such as DRAMs, it is necessary to lower the voltage applied to the gate in order to ensure reliability, and the effect of reducing power consumption is also obtained. Therefore, the power supply voltage (VCC) is set to 5. 0V
Has been developed from 3.3V to 3.0V.

The substrate current supply efficiency is obtained by dividing the substrate current (IBB) generated by drawing out positive charges from the substrate by the consumption current (ICC) consumed by the substrate bias generation circuit. In the above substrate bias generation circuit,
The capacitance of the pumping capacitor 104 is C, and the power supply voltage is V
Assuming CC, the charge consumed by the pumping capacitor 104 in one cycle is C × VCC, and the charge absorbed from the substrate to the node 106 in one cycle has a substrate potential of VBB and a P-channel MOS transistor. If the threshold voltage is Vth, C × (VCC + VBB−Vt
h). The substrate current supply efficiency is ideally (VCC +
Since VBB-Vth) / VCC, the substrate current supply efficiency decreases as the substrate potential (VBB) decreases.

Even if the power supply voltage drops, the substrate potential cannot be made too shallow in order to secure a margin against noise such as undershoot. When it is attempted to obtain the substrate potential -2V by using the substrate bias generating circuit with the power supply voltage of 3.0V, assuming that the threshold voltage Vth of the P-channel MOS transistor is 0.7V, the substrate current supply efficiency is Is less than 0.1. The decrease in the power supply voltage increases the current consumed by the substrate bias generation circuit.

The present invention has been made in view of the above problems,
An object of the present invention is to provide a semiconductor integrated circuit having a built-in substrate bias generation circuit that efficiently supplies a sufficiently low substrate potential even at a low power supply voltage.

[0009]

In order to achieve the above object, according to the present invention, the output of the first charge pump circuit is further pumped by the second charge pump circuit to drive the first charge pump circuit. It was decided to drive the second charge pump circuit at a frequency half the frequency.

More specifically, the invention of claim 1 is
A first charge pump circuit; and a second charge pump circuit for further pumping the output of the first charge pump circuit. The first charge pump circuit is driven by the output of the oscillator circuit, and the second charge pump circuit is provided. The circuit is driven by a frequency divider circuit that oscillates at a frequency half that of the oscillator circuit.

According to a third aspect of the present invention, in the above first aspect of the invention, a third charge pump circuit driven by a signal having a phase opposite to that of the first charge pump circuit and a phase opposite to the second charge pump circuit are used. Further includes a fourth charge pump circuit for further pumping the output of the third charge pump circuit, the output rectifying diodes of the second and fourth charge pump circuits being respectively the first and the first rectifying diodes. The second charge pump circuit controls the gate of the second N-channel MOS transistor by the output of the first capacitor which is composed of two N-channel MOS transistors and constitutes the second charge pump circuit. The gate of the first N-channel MOS transistor is controlled by the output of the constituting second capacitor, and the first and second A delay circuit for delaying the output signal of the frequency dividing circuit, and an output signal of the frequency dividing circuit and an output signal of the delay circuit are used as input signals so that a period in which both the outputs of the capacitors are "H" does not occur. A NAND circuit and a NOR circuit, and an inverter circuit that inverts the output signal of the NAND circuit are further included, and one of the second charge pump circuit and the fourth charge pump circuit is driven by the output of the NOR circuit. The other one is driven by the output of the inverter circuit.

According to a fourth aspect of the invention, in the first aspect of the invention, the substrate potential outputs "H" when the substrate potential is higher than a certain potential and "L" when the substrate potential is lower than a certain potential according to the substrate potential. "L" of the detection circuit and the substrate potential detection circuit
A level shift circuit for converting the level output to a substrate potential,
Further comprising a MOS transistor switch for controlling connection between the output terminal of the first charge pump circuit and the substrate,
An output signal of the level shift circuit is used as a control signal of the MOS transistor switch, and an output signal of the substrate potential detection circuit is used as a control signal of a circuit that transmits the output of the oscillation circuit to the frequency dividing circuit.

[0013]

According to the invention of claim 1, the second charge pump circuit, which is driven at half the frequency of the first charge pump circuit, further pumps the output of the first charge pump circuit. , After the first charge pump circuit completes discharging the charge from the first charge pump circuit output node, the second charge pump circuit
The charges of the substrate are sucked up to the node, and a low substrate potential can be efficiently generated.

According to the third aspect of the present invention, since the charge pump circuit trains of the two systems are driven by complementary alternating current, for example, when the output node of the first charge pump circuit becomes "L" level, Since the third charge pump circuit output node becomes "H" level and the second N-channel MOS transistor is turned on, the "L" level potential appearing at the first charge pump circuit output node is lost. Without being transmitted to the substrate. In addition, since the potentials of the first charge pump circuit output node and the third charge pump circuit output node are controlled so as not to be at the “H” level at the same time, the first or third charge pump circuit output node No positive charges flow back into the substrate.

According to the present invention, the output signals of the substrate potential detecting circuit control the connection between the outputs of the first and third charge pump circuits and the substrate, and the output signal of the oscillation circuit divides the frequency. Since it controls the circuit transmitted to the
Of the charge pump circuit alone to generate the substrate potential, or to output the outputs of the first and third charge pump circuits to the second,
The fourth charge pump circuit can be further pumped to generate the substrate potential, or can be selected according to the level of the substrate potential.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to embodiments of the present invention will be described in detail below.

(Embodiment 1) FIG. 1 shows a substrate bias generating circuit according to a first embodiment of the present invention.

In the figure, reference numeral 1 is an oscillator circuit, and 2 is a frequency divider circuit for converting the output signal of the oscillator circuit 1 into a half frequency. The P-channel MOS transistors 101 and 102 and the pumping capacitor 104 form a first charge pump circuit, and the P-channel MOS transistor 103 and the pumping capacitor 105 form a second charge pump circuit. Third and fourth charge pump circuits having a configuration similar to the first and second charge pump circuits are further provided.

The oscillator circuit 1 outputs alternating currents complementary to each other to drive the pumping capacitors 104 and 111 in opposite phases. When "H" is input to the pumping capacitor 104, the potential of the node 106 is tried to be raised, and at the same time, "L" is input to the pumping capacitor 111, the potential of the node 113 is lowered, and the transistor 101
Is turned on. Therefore, the node 106 is charged up by the pumping capacitor 104, but the potential does not rise above VSS, and excess charge is discharged to VSS. Subsequently, the pumping capacitor 104
When "L" is input to, the potential of the node 106 is tried to be lowered, and at the same time, "L" is applied to the pumping capacitor 111.
H ″ is input, the potential of the node 113 rises, and the transistor 101 is turned off. Therefore, positive charge does not flow into the node 106 from VSS,
The potential of the node 106 drops, the diode-type P-channel MOS transistor 102 is turned on, and the charge of the node 107 is absorbed. With the above operation as one cycle, the first charge pump circuit generates a negative voltage at node 107.

The negative voltage thus created is further reduced by the second charge pump circuit. At this time, “L” is input to the pumping capacitor 105 and the node 1
Node 10 when starting to absorb the electric charge of the substrate to 07
If the potential of node 7 is equal to the potential of node 107 when “H” is input to pumping capacitor 105 and node 107 has finished charging up, the potential of node 107 will not be lost in the second charge pump circuit and will be negative in the substrate. Can supply voltage. Therefore, it suffices to operate the second charge pump circuit at a cycle twice that of the first charge pump circuit. At this time, the substrate potential that can be generated is-(2VCC-2Vth).
(VCC is power supply voltage, Vth is P channel MO
S transistor threshold voltage).

FIG. 2 is a graph comparing the substrate current supply efficiencies of the substrate bias generating circuit of this embodiment and the conventional substrate bias generating circuit by a spice simulation.

Power supply voltage is 3.0V, P channel MOS
When the threshold voltage of the transistor is 0.7V, the substrate current supply efficiency of the substrate bias generating circuit of the present invention is better than that of the conventional substrate bias generating circuit when the substrate potential is around -1.5V. In the substrate bias generation circuit of
Under the above conditions, the substrate potential −2V cannot be generated, but the substrate bias generating circuit of the present invention has a substrate current supply efficiency of 2V.
A substrate potential of −2 V can be generated at 0%.

(Embodiment 2) FIG. 3 is a circuit diagram showing a modified example of the second and fourth charge pump circuits and a circuit for driving them. As shown in FIG. 1, the rectifying elements of the second and fourth charge pump circuits are diode-type P
Since it is composed of channel MOS transistors,
The potential of the substrate is higher than that of the nodes 107 and 114 by P
The threshold voltage of the channel MOS transistor increases. Therefore, the rectifying elements of the second and fourth charge pump circuits are respectively connected to the N-channel MOS transistor 1
The gate of N channel MOS transistor 115 is connected to node 114, and the gate of N channel MOS transistor 116 is connected to node 107. With such a configuration, the second charge pump circuit and the fourth charge pump circuit are driven in opposite phases. Therefore, when "L" appears at the node 107, the node 114 becomes "H". , N-channel MOS transistor 115 is turned on, and the potential of node 107 is transmitted to the substrate without loss regardless of the threshold voltage of the transistor.

Further, the output of the frequency dividing circuit 2 and the frequency dividing circuit 2
NOR output of the signal obtained by delaying the output of
The second charge pump circuit and the fourth charge pump circuit are driven by the output of the frequency dividing circuit 2 and the signal obtained by inverting the NAND output of the signal obtained by delaying the output of the frequency dividing circuit 2 by the delay circuit 3. When "H" is output from the frequency divider circuit 2, NO
The output of the R circuit immediately transits to "L", and the signal obtained by inverting the output of the NAND circuit transits to "H" after a delay time set by the delay circuit 3. From frequency divider 2 ”
When L "is output, the output of the NOR circuit transits to" H "with a delay of the delay time set by the delay circuit 3, and NAN is output.
The signal obtained by inverting the output of the D circuit immediately transits to "L". Therefore, there is no period in which the node 107 and the node 114 are “H” at the same time, so that the node 1
The charges of 07 and 114 do not flow back.

(Third Embodiment) FIG. 4 is a substrate bias generating circuit according to a third embodiment of the present invention, in which the method of generating the substrate potential is changed according to the substrate potential. As shown in FIG. 2, as long as the substrate potential is high, it is better to generate the substrate potential in only one stage of the charge pump circuit, as in the conventional case, to improve the substrate current supply efficiency. When the substrate potential becomes lower, pumping the output of the first-stage charge pump circuit further by the second-stage charge pump circuit improves the substrate current supply efficiency. Therefore, while the substrate potential is high, it is better to generate the substrate potential in only one stage of the charge pump circuit and pump the output of the charge pump circuit in the first stage by the charge pump circuit in the second stage as in the conventional case. When the substrate potential drops to a level where the substrate current supply efficiency improves, the output of the first-stage charge pump circuit is further pumped by the second-stage charge pump circuit to supply the substrate potential, which is the most efficient. A substrate potential can be generated.

The substrate is connected to the outputs of the second and fourth charge pump circuits, but the nodes 107 and 114 are connected through N-channel MOS transistors 117 and 118.
Is also connected. The level shift circuit 4 converts the signal of the amplitude VCC-VSS output from the substrate potential detection circuit 5 into a signal of the amplitude VCC-VBB, and controls the N-channel MOS transistor switches 117 and 118 with this signal.

The substrate potential detecting circuit 5 is "L" when the substrate potential reaches a level where the substrate current supply efficiency is improved by pumping the output of the first stage charge pump circuit by the second stage charge pump circuit. Is output and this "L"
The signal is converted into a substrate potential by the level shift circuit 4. That is, when the substrate potential reaches a level at which the substrate current supply efficiency is improved by pumping the output of the first-stage charge pump circuit by the second-stage charge pump circuit, the substrate of the gates of the N-channel MOS transistors 117 and 118 is reached. A potential is applied, the N-channel MOS transistors 117 and 118 are turned off, and the substrate and node 10
7, 114 are separated. Further, the output of the oscillation circuit 1 is transmitted to the frequency dividing circuit 2 when the output of the substrate potential detection circuit 5 becomes “L”.

Therefore, when the output of the substrate potential detecting circuit 5 becomes "L", the substrate is disconnected from the nodes 107 and 114, and the second and fourth charge pump circuits are driven to drive the first stage charge pump circuit. Further, the substrate potential is generated by the configuration in which the output of is further pumped by the second stage charge pump circuit.

[0029]

As described above, according to the first aspect of the present invention, the frequency of driving the first charge pump circuit by further pumping the output of the first charge pump circuit by the second charge pump circuit. Since the second charge pump circuit is driven at a frequency of 1/2, the power supply voltage is 3.
When the substrate potential is 0 V and the substrate potential is −2.0 V, the substrate current can be generated with an efficiency of 20%, and the power supply voltage can be lowered.

According to the invention of claim 3, the element for rectifying the output to the substrate of the charge pump circuit array of two systems is N.
The gates of the N-channel MOS transistors 115 and 116 are connected to the nodes 107 and 114, respectively, which are controlled so that the potentials thereof do not become "H" level at the same time. The potentials of the nodes 107 and 114 can be transmitted to the substrate without loss and without backflow of charges.

According to the invention of claim 4, the N-channel MOS transistors 117 and 118 are controlled by the output signal of the substrate potential detecting circuit and the circuit for transmitting the output signal of the oscillating circuit to the frequency dividing circuit is controlled. The optimum substrate current supply efficiency can be obtained according to the substrate potential.

[Brief description of drawings]

FIG. 1 is a substrate bias generation circuit according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram comparing the substrate current supply efficiencies of the substrate bias generation circuit of the same example and a conventional substrate bias generation circuit by a spice simulation.

FIG. 3 is a circuit diagram showing second and fourth charge pump circuits according to a second embodiment of the present invention and a modification example of a circuit for driving them.

FIG. 4 is a substrate bias generation circuit for changing a substrate potential generation method according to a substrate potential according to a third embodiment of the present invention.

FIG. 5: Conventional substrate bias generation circuit

[Explanation of symbols]

1 Oscillation circuit 2 Dividing circuit 3 Delay circuit 4 Level shift circuit 5 Substrate potential detection circuit 101-103,108,109,110 P-channel MOS transistor 104,111 Pumping capacitor 105,112 First and second capacitors 115-118 N-channel MOS transistor

Claims (4)

[Claims] 1. A first charge pump circuit, a second charge pump circuit that further pumps the output of the first charge pump circuit, and an oscillation that outputs an oscillation frequency that drives the first charge pump circuit. A semiconductor integrated circuit comprising: a circuit; and a frequency dividing circuit that outputs a half frequency of the oscillation circuit that drives the second charge pump circuit. 2. A third charge pump circuit driven by a signal having a phase opposite to that of the first charge pump circuit according to claim 1, and a second charge pump circuit driven by a signal having a phase opposite to that of the second charge pump circuit. The semiconductor integrated circuit further including a fourth charge pump circuit for further pumping the output of the charge pump circuit of 3. 3. The second charge pump circuit according to claim 2, wherein the output rectifying diodes of the second and fourth charge pump circuits are respectively constituted by first and second N-channel MOS transistors, and the second charge pump circuit is constituted. The output of the first capacitor controls the gate of the second N-channel MOS transistor, and the output of the second capacitor forming the fourth charge pump circuit controls the gate of the first N-channel MOS transistor. A delay circuit that controls and delays an output signal of the frequency dividing circuit so that a period in which the outputs of the first and second capacitors are both "H" does not occur; an output signal of the frequency dividing circuit; A NAND circuit and a NOR circuit that use the output signal of the delay circuit as an input signal; and an inverter circuit that inverts the output signal of the NAND circuit. And a second charge pump circuit and a fourth charge pump circuit, one of which is driven by an output of the NOR circuit and the other of which is driven by an output of the inverter circuit. . 4. The semiconductor integrated circuit according to claim 1, wherein
Depending on the substrate potential, if the substrate potential is above a certain level,
H ", a substrate potential detection circuit that outputs" L "when the substrate potential is lower than a certain potential, a level shift circuit that converts the" L "level output of the substrate potential detection circuit into a substrate potential, the first charge pump The circuit further comprises a MOS transistor switch for controlling the connection between the output terminal of the circuit and the substrate, wherein the output signal of the level shift circuit is used as the control signal of the MOS transistor switch, and the output signal of the substrate potential detection circuit is A semiconductor integrated circuit, which is used as a control signal for a circuit for transmitting an output of an oscillation circuit to the frequency dividing circuit.