JPH061632B2 - FiFo memory controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FiFo memory control device for an arithmetic processing device input buffer section.

2. Description of the Related Art Many input buffer units of conventional arithmetic processing devices use a FiFo memory, and examples thereof include the following documents. "32-bit Microprocessors with Successive Product Announcements", Nikkei Electronics April 30, 1984, PP 61-69.

FIG. 2 is a block diagram of a FiFo memory control device of a conventional arithmetic processing device input buffer unit. 1 is a FiFo memory that buffers input data, 2 is an arithmetic processing unit, 3 is an input control circuit that controls data input to the FiFo memory, and 4 is FiFo that stores a write address of the input data to the FiFo memory 1.
A memory write pointer, 5 is a FiFo memory read pointer that stores a read address of data in the FiFo memory 1 by the arithmetic processing unit 2, and 6 is a FiFo memory management unit that manages empty information and full information of the FiFo memory 1, It consists of the FiFo memory empty flag and the 8 FiFo memory full flag. Reference numeral 9 is a stack memory forming a stack area used in the arithmetic processing operation of the arithmetic processing unit 2, and 10 is a stack pointer for storing an address when the arithmetic processing unit 2 accesses the stack memory 9.

In the above configuration, the input control circuit 3 inputs data to the FiFo memory 1 regardless of the execution operation of the arithmetic processing unit 2. The data input operation is stopped only when the FiFo memory full flag 8 is on and the FiFo memory is full. On the other hand, the arithmetic processing unit 2 executes the arithmetic operation regardless of data input from the input terminal as long as the FiFo memory empty flag is in the off state. The FiFo memory write pointer 4 is incremented each time data is input to the FiFo memory 1 by the input control circuit 3, and the FiFo memory read pointer 5 is incremented each time data is output from the FiFo memory 1 by the arithmetic processing unit 2. FiFo memory 1 is configured as a memory having a first-in first-out function. Fi
The Fo memory management unit 6 uses the FiFo memory write pointer 4 and the FiFo
The empty information and the full information of the FiFo memory 1 are managed by detecting the coincidence status of the memory read pointer 5.

However, in such a configuration, in order for the input data to be supplied to the FiFo memory 1 and the input data to be consumed by the arithmetic processing unit 2 to be performed without waiting operation, the word of the FiFo memory 1 cannot be used. It is necessary to set the length well. If the word length of the FiFo memory 1 is too small, the input data is lost from the FiFo memory 1 and the input data waiting operation of the arithmetic processing unit 2 frequently occurs when the input data is consumed at high speed by the arithmetic processing unit 2. Also Fi
If the word length of the Fo memory 1 is too large, bus transfer for data input frequently occurs, and bus transfer due to data output and arithmetic processing may be hindered. That is, there is a problem in that the word length of the FiFo memory 1 that has been set once cannot be changed, although the quality of the word length setting of the FiFo memory 1 greatly affects the processing efficiency of the entire apparatus.

In view of the above problems, it is an object of the present invention to provide a FiFo memory control device capable of dynamically changing the word length of the FiFo memory so that the processing efficiency of the entire device is maximized.

Means for Solving the Problems The present invention relates to a memory and a Fi for input data in the memory.
FiFo memory limit pointer that stores the final address of the Fo memory area, FiFo memory write pointer that stores the input data write address to the memory, FiFo memory read pointer that stores the data read address from memory, and FiFo memory write A first comparator that compares the value of the pointer and the value of the FiFo memory limit pointer, a second comparator that compares the value of the FiFo memory read pointer and the value of the FiFo memory limit pointer, and the arithmetic processing of the memory Stack pointer for storing the access address to the stack memory area used for
o A third comparator that compares the value of the memory limit pointer, a FiFo memory management unit that manages the FiFo memory area in the memory, and an input of the FiFo memory management unit output and system lock A FiFo memory control device comprising a FiFo memory size change control circuit for changing a value.

Operation According to the present invention having such a configuration, the FiFo memory size change control circuit counts the empty information and the full information of the FiFo memory output by the FiFo memory management unit. Then, the FiFo memory limit pointer is changed to change the FiFo memory size according to the excess / deficiency state of the FiFo memory that occurs within a fixed time. As a result, the FiFo memory word length can be dynamically changed, and an optimal processing system for the target processing data can be configured. Further, by treating the unnecessary FiFo memory area as a stack memory area, it is possible to effectively use the memory.

Embodiment FIG. 1 is a block diagram of a FiFo memory control device in an embodiment of the present invention. In FIG. 1, 2 is an arithmetic processing unit, 3
Is an input control circuit, 4 is a FiFo memory write pointer,
5 is a FiFo memory read pointer, 6 is a FiFo memory management unit, 7 is a FiFo memory empty flag, 8 is a FiFo memory full flag, 10 is a stack pointer, and the above is the same as the configuration of FIG. 11 is a memory, 12 is a FiFo memory limit pointer that stores the final address of the memory 11 for the FiFo memory area for input data, 13 is a FiFo memory write pointer 4 and the value of the FiFo memory limit pointer 12 is compared, and a FiFo memory write pointer A first comparator that resets when the value of 4 becomes equal to or greater than the value of the FiFo memory limit pointer 12, 14 is the value of the FiFo memory read pointer 5 and FiFo
A second comparator that compares the values of the memory limit pointer 12 and resets when the value of the FiFo memory read pointer 5 becomes equal to or greater than the value of the FiFo memory limit pointer 12, 15 is the value of the stack pointer 10 and the value of the FiFo memory limit pointer 12 When the value of the stack pointer 10 matches the value of the FiFo memory limit pointer 12, the third comparator which outputs the stack area full information to the arithmetic processing unit 2, 16 outputs the empty flag 7 of the FiFo memory And the output of the full flag 8 and the system lock are input, the empty information and the full information of the FiFo memory area that occur at a fixed time are counted, and the FiFo memory limit pointer 12
It is a FiFo memory size change control circuit for changing.

The operation of this embodiment will be described below. Input control circuit 3 is Fi
As long as the Fo memory full flag 8 is off,
The input data is read assuming that there is an empty area in the FiFo memory area, and the FiFo memory write pointer 4 is incremented. The value of the FiFo memory write pointer 4 which is sequentially incremented is compared with the FiFo memory limit pointer 12 by the comparator 13, and is reset when the value of the FiFo memory limit pointer 12 or more is reached. Therefore, the FiFo memory write pointer 4 repeats the address from address 0 to the value of the FiFo memory limit pointer 12. Further, as long as the FiFo memory empty flag 7 is off, the arithmetic processing unit 2 reads the data as valid input data in the FiFo memory area of the memory 11 and increments the FiFo memory read pointer 5. The value of the FiFo memory read pointer 5 which is sequentially incremented is compared with the FiFo memory limit pointer 12 by the comparator 14, and is reset when the value of the FiFo memory limit pointer 12 or more is reached. Therefore, like the FiFo memory write pointer 4, the FiFo memory read pointer 5 starts from address 0.
The address up to the value of the FiFo memory limit pointer 12 is repeated. On the other hand, the area after the value of the FiFo memory limit pointer 12 of the memory 11 is used when the arithmetic processing unit 2 executes the arithmetic operation by using the stack pointer 10 as the stack memory area. The value of the stack pointer 10 is compared with the FiFo memory limit pointer 12 by the comparator 15, and if it matches the value of the FiFo memory limit pointer 12, the stack memory area full information is output to the arithmetic processing unit 2. The empty information and the full information of the FiFo memory area are managed by the FiFo memory management unit 6, and the output thereof is used to count the empty information and the full information of the FiFo memory area which are generated in a fixed time in the FiFo memory size change control circuit 16. . In the counting result, the value of the FiFo memory limit pointer 12 is decreased if the number of empty information occurrences is greater than a preset value, and the value of the FiFo memory limit pointer 12 is decreased if the number of full information occurrences is greater than a preset value. Is controlled by the FiFo memory size change control circuit 16. However, if the value of the stack pointer 10 is also input to the FiFo memory size change control circuit 16 and the value of the FiFo memory limit pointer 12 becomes larger than the value of the stack pointer 10 due to the change, the value of the stack pointer 10 becomes large. , FiFo memory limit pointer to change 1
Wait until the value becomes 2 or more and change. This can prevent the data in the stack memory area from being destroyed.

As described above, according to the present embodiment, the FiFo memory management unit 6
The number of empty information occurrences and the number of full information occurrences in the FiFo memory area
The size of the FiFo memory area can be dynamically changed by counting by the FiFo memory size change control circuit 16 and changing the value of the FiFo memory limit pointer 12 so as to reduce the number of occurrences for a certain period of time.

EFFECTS OF THE INVENTION As described above, according to the present invention, the size of the FiFo memory area can be dynamically changed, and the optimum FiFo memory size can be set for the target processing data. Furthermore, an unnecessary FiFo memory area can be used as a stack memory area, and effective use of the memory can be achieved. Especially, the effect that the FiFo memory size can be dynamically changed is effective when it is impossible or extremely difficult to change the circuit once created, such as the LSi circuit.
The practical effect of the present invention will be great in the future when Si is promoted.

[Brief description of drawings]

FIG. 1 is a block diagram of a FiFo memory controller according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional FiFo memory controller. 2 ... Arithmetic processing unit, 3 ... Input control circuit, 4 ... FiFo memory write pointer, 5 ... FiFo memory read pointer, 6 ... FiFo memory management unit, 10 ... Stack pointer, 11 ... Memory, 12 ... FiFo memory limit pointer, 13 ... first comparator, 14 ... second comparator, 1
5 ... Third comparator, 16 ... FiFo memory size change control circuit.

Claims (1)

[Claims] 1. A memory, an arithmetic processing unit for sequentially reading and arithmetically operating input data to the memory, an input control circuit for controlling data input to the memory, and a FiFo (first in, first out) for the input data in the memory. ) A FiFo memory limit pointer that stores the final address handled as a memory, a FiFo memory write pointer that stores the data write address to the memory that is incremented each time data is input to the FiFo memory area, and the arithmetic processing unit is a FiFo memory. FiFo memory read pointer that stores the data read address to the memory and is incremented each time the input data of the area is read, compares the value of the FiFo memory write pointer with the value of the FiFo memory limit pointer, and increments sequentially The value of the FiFo memory write pointer is
A first comparator for resetting the FiFo memory write pointer when the FiFo memory limit pointer value is greater than or equal to the value;
The value of the Fo memory read pointer is compared with the value of the FiFo memory limit pointer, and the value of the FiFo is sequentially incremented.
A second comparator that resets the FiFo memory read pointer when the value of the memory read pointer is greater than or equal to the value of the FiFo memory limit pointer, and a portion of the memory after the address indicated by the FiFo memory limit pointer as a stack memory area. The stack pointer that stores the address to be accessed by sequentially decrementing the stack memory area from the memory last address by the arithmetic processing unit, compares the stack pointer value and the FiFo memory limit pointer value, and compares the stack pointer. When the value of the FiFo memory limit pointer matches the value of the FiFo memory limit pointer, a third comparator that outputs stack memory area full information to the arithmetic processing unit, the value of the FiFo memory write pointer and the FiFo memory read pointer Enter a value to display the empty and full information in the FiFo memory area of the above memory. FiFo memory management section that manages, and the empty information, full information and system clock of the FiFo memory management section are input, and the empty information and the full information of the FiFo memory area that occur at a certain time are counted, and the value of the FiFo memory limit pointer is calculated. A FiFo memory control device, comprising: a FiFo memory size change control circuit for changing.