JPH06175967A - Dma controller - Google Patents

Abstract

PURPOSE:To prevent the use time of a system bus from being extended by the transfer speed of an input/output device. CONSTITUTION:A data buffer part 3 where transfer data is stored at the time of data transfer between a storage device 2-2 and an input/output device 2-4, an input/output device-side signal line 11 for data input/output between the data buffer part and the input/output device, and a storage device-side signal line 7a for data input/output between the data buffer part and a data bus 7 are provided, and data is transferred between the storage device and the input/ output device through a DMA controller. When the data buffer part can store plural data, a buffer counter 4 which outputs the storage address of the data buffer part 3 is added.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device in an information processing device, and more particularly to a DMA control device (Direct Memory Access) provided between a storage device and an input / output device.
Control device).

[0002]

2. Description of the Related Art A conventional DMA control device is controlled by an address counter unit for generating a data storage address of a storage device, a transfer counter unit for controlling the number of data transfers between an input / output device and the storage device, and a central processing unit. And a timing control unit for timing the reading and writing of data with respect to the storage device and the input / output device.

FIG. 3 is a diagram for explaining a data transfer method in such a conventional DMA control device. The central processing unit 3-1, the storage device 3-2, the DMA control device 3-3, and the input / output device 3-4 are connected to the data bus 3-5, the address bus 3-6, and the control bus 3-7. ing. The central processing unit 3-1 includes a DMA control unit 3-3 and an input / output unit 3-.
4, the storage bus storage address and the number of transfer data are set using the data bus 3-5, the address bus 3-6, and the control bus 3-7, and the storage bus 3-5 and the input / output device 3-4 are connected to each other. Start data transfer. When the input / output device 3-4 becomes ready for data transfer, the data transfer request signal line 3-8 is validated and notified to the DMA control device 3-3.
Validates the bus use request signal line 3-10 and notifies the central processing unit 3-1.

The DMA controller 3-3 is a central processing unit 3-.
1 enables the bus use permission signal line 3-11, the data transfer permission signal line 3-9 is activated, and the control bus 3-7 is activated.
The read or write signal is output to the storage device 3-2 and the input / output device 3-4 to execute data transfer. The transfer data is transferred through the data bus 3-5. Here, when the wait signal line 3-12 requesting the extension of the read or write signal line from the input / output device 3-4 is enabled, the DMA controller 3-3 extends the read or write signal of the control bus 3-7. Lengthen the transfer timing. Input / output device 3-
If the data transfer request signal line 3-8 is invalid, the DMA controller 3-3 becomes invalid.
Completes the data transfer by invalidating the bus use request signal line 3-10.

[0005]

When a low-speed input / output device transfers data to a high-speed storage device, the read or write signal is extended to match the read / write timing of the low-speed input / output device and the transfer timing is lengthened. Or
It was necessary to request the use of the system bus for each data transfer. Therefore, there has been a problem that the system bus is used for a long time.

[0006]

A DMA controller according to the present invention is a data transfer control unit for controlling data transfer between an input / output device and a storage device under the control of a central processing unit, which is an address bus. An address counter unit connected to the memory device for generating a data storage address of the storage device, a transfer counter unit connected to the data bus for controlling the number of data transfers between the input / output device and the storage device, and controlled by the central processing unit, In a DMA controller having a storage section, an input / output device, an address counter section, and a timing control section for controlling the timing of a transfer counter section, data to be transferred can be stored, and the timing control section takes timing. Data input / output
Data buffer unit, a storage device-side signal line that connects the data buffer unit and the data bus, and enables data input / output between the previous storage devices, the data buffer unit, and the input / output device And a signal line on the input / output device side that enables input / output of the data to / from the input / output device.

Further, in the MA controller of the present invention, in the above configuration, when the data buffer section is a data buffer capable of storing a plurality of data, the data is further controlled by the timing of the timing control section. It is characterized in that a buffer counter unit for generating an address of the buffer unit is added.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is an internal block diagram of an embodiment of the present invention, and FIG. 2 is a connection diagram of each device.

The outline of the data transfer method will be described with reference to FIG. 2. The central processing unit 2-1, the storage unit 2-2, and the DMA.
The controller 2-3 has a data bus 2-5 and an address bus 2-.
6, connected to the control bus 2-7, the input / output device 2-4 is D
It is connected to the MA control device 2-3. Central processing unit 2
-1 sets the storage address and the number of transfer data to the DMA controller 2-3 and the input / output device 2-4 by using the data bus 2-5, the address bus 2-6 and the control bus 2-7, The data transfer between the storage device 2-2 and the input / output device 2-4 is activated. In the case of data transfer from the input / output device 2-4 to the storage device 2-2, when the input / output device 2-4 becomes ready for data transfer, the data transfer request signal line 2-8 is enabled and DM
Notify the A control device 2-3.

The DMA controller 2-3 validates the data transfer permission signal line 2-9, and the I / O device read signal line 2-
14 is output to the input / output device 2-4 to execute data transfer. Transfer data is input / output device 2 via data signal line 2-13.
-4 to the DMA controller 2-3. Here, when the wait signal line 2-12 requesting extension of the read and write signals from the input / output device 2-4 is enabled, the DMA controller 2-3 extends the input / output device read signal line 2-14 and transfers it. Increase the timing. Input / output device 2-4 and D
When the data transfer is stored several times between the MA control devices 2-3 to store the transfer data, the DMA control device 2-3 enables the bus use request signal line 2-10. Central processing unit 2-1
Activates the bus use permission signal line 2-11, the DMA
The control device 2-3 outputs the storage address of the storage device to the address bus 2-6, the transfer data to the data bus 2-5, and validates the write signal of the control bus 2-7 to enable the storage device 2-2.
The transfer data stored in is continuously transferred.

Next, the internal operation of the DMA controller will be described with reference to FIGS. The capacity of the data buffer unit 3 is 1
Data transfer from the input / output device 2-4 to the storage device 2-2 with 0 bytes, the number of transferred data of 18 bytes, and the start address 0 will be described as an example. First, the leading address address 0 is stored in the address counter section 1 from the address bus signal line 6. Next, the transfer data number 18 is stored in the transfer counter unit 2 from the data bus signal line 7. Data transfer from the input / output device 2-4 to the data buffer unit 3 is performed by the input / output device 2-
4 starts when the data transfer request signal line 19 becomes valid. The timing control unit 5 enables (a) the data transfer permission signal line 20 and the input / output device read signal line 21 to read the transfer data from the input / output device to the input / output device side signal line 11, and (b) the buffer write. The signal line 12 is enabled, the transfer data of the input / output device side signal line 11 is stored in the location corresponding to the value of the buffer address signal line 14 of the data buffer unit 3, and (c) the buffer count signal line 13 is enabled. The value of the buffer counter section 4 is incremented by 1, and (d) the transfer count signal line 9 is enabled and the value of the transfer counter section 2 is decremented by 1. The above operations (a) to (d) are executed 10 times in total, and the value of the buffer counter unit 4 is 10 and the value of the transfer counter unit 2 is 8.
When this happens, the data transfer from the input / output device 2-4 to the data buffer unit 2 is temporarily interrupted, and the timing control unit 5 enables the bus use request signal line 15 to the central processing unit 2-1.

When the central processing unit validates the bus use permission signal line 16, data transfer from the data buffer unit 3 to the storage device is started. The execution procedure is as follows: (e) enable the buffer count signal line 13 to set the value of the buffer counter unit 4 to 0, and (f) output the data storage address 0 of the storage device from the address counter unit 1 to the address bus signal line 6. And (g)
The transfer data is output from the data buffer unit 3 to the data bus signal line 7 through the storage device side signal line 7a, and (h) the timing control unit 5 enables the storage device write signal line 18,
(i) After data transfer, the address count signal line 8 is enabled and the value of the address counter unit 1 is incremented by 1, and (j) the buffer count signal line 13 is enabled and the value of the buffer counter unit 4 is incremented by 1. When the above operations (e)-(j) are executed 10 times in total, the data transfer from the data buffer unit 3 to the storage device is temporarily terminated.

The data transfer of the remaining 8 bytes is started from the value 10 of the address counter 1 and the value 8 of the transfer counter 2, and the data transfer from the input / output device to the data buffer unit 3 is performed in the above (a)-(e). When the operation is executed 8 times, the value of the transfer counter 2 becomes 0 and the transfer end signal line 10 becomes valid. The timing control unit 5 ends the data transfer from the input / output device to the data buffer unit 3 and enables the bus use permission request signal line 15. When the bus use permission signal line 16 becomes valid, data transfer is started from the data buffer unit 3 to the storage device, and when the operations of (f)-(j) are executed eight times in succession, all data transfer ends. At this time, the value of the address counter unit 1 is 18, and the value of the transfer counter unit 2 is 0.

In the above embodiment, the case where the capacity of the data buffer unit 3 can store a plurality of data of 10 bytes has been described. However, when the transfer of 1 byte can be executed like a personal computer, It is sufficient to prepare a data buffer unit 3 having a capacity of 1 byte, and at the same time, the buffer counter unit 4 becomes unnecessary.

[0015]

As described above, according to the present invention, since the input / output device side data signal line and the data buffer portion for storing the transfer data are provided, the input / output device can be directly connected to the DMA control device. Even if the data transfer rate of the device is slow, the read or write signal on the side of the storage device is not extended, the transfer data is stored in the data buffer, and the transfer data for the data buffer can be stored by one bus use request. By continuously transferring data between storage devices, the system bus usage time can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a connection diagram of each device of the present invention.

FIG. 3 is a connection diagram of each conventional device.

[Explanation of symbols]

 1 Address Counter Section 2 Transfer Counter Section 3 Data Buffer Section 4 Buffer Counter Section 5 Timing Control Section 6 Address Bus Signal Line 7 Data Bus Signal Line 7a Storage Device Side Signal Line 8 Address Count Signal Line 9 Transfer Count Signal Line 10 Transfer End Signal Line 11 Input / output device side signal line 12 Buffer write signal line 13 Buffer count signal line 14 Buffer address signal line 15 Bus use request signal line 16 Bus use permission signal line 17 Storage device read signal line 18 Storage device write signal line 19 Data transfer Request signal line 20 Data transfer permission signal line 21 Input / output device read signal line 22 Input / output device write signal line 2-1 Central processing unit 2-2 Storage device 2-3 DMA control device 2-4 Input / output device 2-5 Data Bus 2-6 Address bus 2-7 Control bus 2-8 switching Transmission request signal line 2-9 Transfer permission signal line 2-10 Bus use request signal line 2-11 Bus use permission signal line 2-12 Wait signal line 2-13 Data signal line 2-14 I / O device read signal line 3- 1 Central Processing Unit 3-2 Storage Device 3-3 DMA Control Device 3-4 Input / Output Device 3-5 Data Bus 3-6 Address Bus 3-7 Control Bus 3-8 Transfer Request Signal Line 3-9 Transfer Enable Signal Line 3-10 Bus use request signal line 3-11 Bus use permission signal line 3-12 Wait signal line

Claims (2)

[Claims] 1. A data transfer control device for controlling data transfer between an input / output device and a storage device under the control of a central processing unit, which is connected to an address bus to generate a data storage address of the storage device. Address counter section
A transfer counter unit that is connected to a data bus and controls the number of data transfers between the input / output device and the storage device; and timings of the storage unit, the input / output device, the address counter unit, and the transfer counter unit that are controlled by the central processing unit. In a DMA control device having a timing control unit for controlling the data, a data buffer unit capable of storing data to be transferred and inputting / outputting the data at a timing by the timing control unit, and the data buffer unit. And the data bus are connected to each other, and a signal line on the storage device side that enables input / output of data to / from the previous storage device is connected to the data buffer unit and the input / output device. A DMA controller including an input / output device-side signal line that enables input / output of data to / from an output device. 2. When the data buffer unit is a data buffer capable of storing a plurality of data, a buffer counter unit for generating an address of the data buffer unit under the control of the timing of the timing control unit is further added. The DMA controller according to claim 1, wherein the DMA controller is formed of: