JPH06181578A - 1 horizontal period delay circuit - Google Patents

Abstract

(57) [Summary] [Objective] In a 1H delay circuit using a CCD and an Fsc, the circuit is simplified by giving information of the video system to the CCD and switching the number of stages of the CCD so as to match 1H of the video system. thing. [Structure] Each Fsc output from an image block 5 is used to input a CCD to a CCD 2 according to video information.
Optimal for each video system by switching the number of stages
An H delayed signal can be obtained. [Effect] Although a dedicated clock circuit was required for video signals having different 1H periods, the circuit can be reduced because Fsc can be used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 1H delay circuit for VTRs and video discs, and more particularly to a 1H delay circuit suitable for a multi-system VTR (hereinafter abbreviated as multi-VTR) that handles a plurality of different 1H video signals.

[0002]

2. Description of the Related Art A conventional circuit is, for example, an actual circuit shovel 62-18.
The configuration is as described in Japanese Patent No. 3477, and the clock frequency is changed in order to change the delay time of the delay circuit.

[0003]

In the above-mentioned prior art, PA is used.
In order to obtain an optimum 1H delay signal for video signals having different 1H delay times, such as L and NTSC, as shown in FIG.
When using CCD block 2 for L (565 steps) CC
When the clock input to D is PAL, Fsc (f = 4.43 MHz) is output from the video block 5 and is switched by the switch 8 and passed through the multiplication circuit 6 and then the CCD 2
Is input to the delay time T,

[0004]

[Equation 1] T (sec) = number of CCD stages (565 stages) / (2 × Fs)
c) (Hz) + Δt Δt = Delay time of the circuit (here, about 0.3 μs). By substituting Fsc = 4.43 MHz into this equation 1, it operates as a 1H delay circuit for PAL (delay time = about 64 μs).

Next, in the case of NTSC, when Fsc (f = 3.58 MHz) from the video block 5 is used, substituting it into Equation 1 gives T = about 79 μs, which is 1H (about 6) of NTSC.
Therefore, in the prior art, the clock generator 7 for NTSC uses a clock (f = approximately 4.47) different from the frequency of N times the color subcarrier so that the frequency becomes 1H of NTSC.
MHz) and switch with switch 8 to double circuit 6
After passing through, it was input to CCD2. Thus, the clock generator needs to be configured, and the circuit becomes complicated.

An object of the present invention is to use a clock that is N times as many as a color subcarrier corresponding to various video systems, thereby eliminating the need for a new clock generator, simplifying the circuit, and optimal for each system. 1H delay signal.

[0007]

For the above object, a CCD
In the 1H delay circuit using Fsc and Fsc, the circuit is simplified by supplying video system information to the CCD and switching the number of CCD stages so as to match 1H of the video system.

[0008]

The 1H delay circuit is composed of a CCD and a clock, and its delay time is determined by the number of CCD stages and the clock frequency. Therefore, according to the present invention, Fsc of the video block can be used as a clock, so that the circuit is simplified.

[0009]

EXAMPLE An example of the present invention will be described below with reference to FIG.
The L and NTSC methods will be described as an example. A video signal is input from the video input terminal 1 and supplied to the CCD block 2. This CCD block 2 produces a 1H delay signal. The delay time is
It is determined by the number of CCD stages.

First, the case of the PAL system will be described. PAL information is input to the video system input terminal 4. This information is input to the video block 5 and the CCD block 2. In the video block 5, PAL system signal processing is performed. Fsc =
Outputs 4.43MHz, passes through the doubler circuit 6 and CCD
Input to block 2, while P in CCD block 2
Upon receiving the AL information, the number of CCD internal stages is switched so as to match 1H of PAL (565 stages), and a 1H delay signal of PAL is output. The number of steps is from 1

[0011]

## EQU2 ## CCD stage number = (1H-.DELTA.t) .times.2.times.Fsc. Next, the case of the NTSC system will be described. The NTSC information is input to the video system input terminal 4. This information is input to the video block 5 and the CCD block 2. The video block 5 performs the signal processing of the NTSC system and Fsc.
= 3.58MHz is output and passes through the doubler circuit 6 and CC
On the other hand, the CCD block 2 receives the information of the NTSC and switches the number of CCD internal stages to match the 1H of the NTSC (452 stages) and outputs the 1H delay signal of the NTSC. From output terminal 3,
It is possible to obtain an optimum 1H delay signal for both NTSC and PAL systems.

In addition to PAL and NTSC, M-PAL (Fsc = 3.575611MHz,
1H = about 63.5 μs, N-PAL (Fsc = 3.5
82056 MHz, 1H = about 64 μs), etc., and in each of these cases, each Fs output from the video block as well.
Optimal 1 for each system by switching the number of CCD stages according to the video system information input to the CCD using c.
An H delayed signal can be obtained.

[0013]

According to the present invention, a dedicated clock circuit is required in the case of video signals having different 1H periods as in the prior art, but since Fsc that is always present in each video system can be used, it is very simple. Circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a conventional block diagram.

[Explanation of symbols]

1 ... video input terminal, 2 ... CCD block, 3 ... video output terminal, 4 ... video system input terminal, 5 ... video block, 6
… Double circuit, 7… NTSC clock generator.

Claims (1)

[Claims] 1. A charge coupling terminal (hereinafter abbreviated as CCD) and a charge transfer clock (hereinafter abbreviated as clock) circuit.
In the horizontal period delay circuit, N times the color subcarrier (hereinafter abbreviated as Fsc) is used as a clock, and a circuit capable of changing the number of CCD stages in accordance with the frequency of the clock is provided. Delay circuit.