JPH0618321B2 - Timer circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a timer circuit having a reset signal.

[Technical background of the invention and its problems]

A conventional timer circuit is shown in FIG. In the figure, 1 is an N-channel transistor that receives the start signal ST as a gate input, 2 is a flip-flop that holds the start signal, and 3
Is a reset N-channel type transistor having a reset signal RS as a gate input, 4 is a time counting device, 5 is an inverter, 6 is a delay circuit, and 7 is an AND circuit. The time counting device 4 operates as shown in the timing chart of FIG.

In the timer circuit of FIG. 4, when the start signal ST enters the gate of the transistor 1, the flip-flop 2 performs the latch operation, the node 8 becomes “H” (high level), and the time counting device 4 is started. . Then, as shown in FIG. 5, after the time T determined by the time counting device 4, the potential of the node 9 changes from “H” to “L” (low level).
become. At this time, the AND circuit 7 generates the reset signal RS which becomes "H" within the width of the signal delay time to in the delay circuit 6.

However, in the circuit of FIG. 4, for example, when the "H" level of the reset signal RS starts to be output and the fixed time to required for reset has not yet passed (this time to
Is sufficient, it means that sufficient time and drive capability are ensured for the node 8 to become the “L” level via the transistor 3, that is, the pulse width of the reset signal is sufficiently secured. When the start signal ST is input to the flip-flop 2, the left input of the flip-flop 2 is at the "L" level, and therefore, at this time, the node 8 should have been at the "L" level. Since the driving capability of the flip-flop 2 driven from is stronger than the capability of turning on the transistor 3 to bring the node 8 to the “L” level, the node 8 at the right output of the flip-flop 2 returns to the original “H” level. It became node 9
Also becomes "H" level again (node 9 has a waveform like the rising portion on the left side of FIG. 5) and the output of the inverter 5 becomes "L" level, so the reset signal RS should be cut off at that time. Therefore, the reset signal RS having the specified pulse width cannot be obtained. Therefore, the device controlled by the timer circuit in FIG. 4 may not be completely reset, which may affect the next operation.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a timer circuit that accurately generates a reset signal having a prescribed pulse width.

[Outline of Invention]

In the present invention, when the output is at the first logic level (for example, “H” level) and the input is at the first logic level from the second logic level (for example, “L” level) during standby, the operation is started. A time counting device whose output changes from a first logic level to a second logic level after a set time,
A start signal of the timer operation is transmitted to an input of the time counting device through a delay circuit, and a reset signal is obtained from an AND circuit which receives an inverted signal of the input of the time counting device and the output of the time counting device. is there.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
The figure is a circuit diagram of the same embodiment. As shown in the figure, one end of an N-channel type transistor 11 having a start signal ST as a gate input is grounded, and the other end is connected to inverters 13 and 1.
4 is connected to one end of a flip-flop 12.
The other end of the flip-flop 12 is connected to one end of the delay circuit 15, one input end of the AND circuit 16 and one end of the reset N-channel transistor 17, respectively. The other end of the delay circuit 15 is connected to the input end a of the time counting device 18 and one input end of the AND circuit 19, respectively. The output terminal b of the time counting device 18 is connected to the other input terminal of the AND circuit 16 and the input terminal of the inverter 20, respectively, and the output terminal of the inverter 20 is connected to the other input terminal of the AND circuit 19. The AND circuit 16 outputs the timer circuit output OUT, and the AND circuit 19 outputs the reset signal RS.
The output terminal of the AND circuit 19 is connected to the gate of the transistor 17, and the other end of the transistor 17 is grounded.

The time counting device 18 operates as shown in the timing chart of FIG. FIG. 3 shows a concrete example of the time counting device 18, 21 and 22 are transfer gates, and 23 to 25.
Is an inverter, 26 and 27 are capacitors, 28 and 29 are P-channel transistors, 30 and 31 are N-channel transistors, V _DD is a power supply, and φ _a and φ _b are clock pulses. In the operation of FIG. 3 (see FIG. 2), the signal at the input end a given to the gate of the transistor 29 is “L”.
At the level, the capacitor 27 is charged. Then, the output of the time counting device of FIG.
Since "8" is on, the "H" level is held. On the other hand, when a circuit (not shown) is driven by the start signal ST and the supply of the clocks φ _a and φ _b is started from this circuit, the transfer gate 22 is opened and closed to discharge the charged load of the capacitor 27 to the capacitor 26 and When the gate 21 is opened and closed, the charged load of the capacitor 26 is discharged to the ground. When the discharge of the capacitor 27 progresses and its terminal voltage drops to a certain value, the inverter 25 inverts,
The transistor 28 turns off. At this time, the transistor 31
If it is turned on, the transistors 30, 31
The output of the time counting device of FIG. 3 goes down to "L" level via the.

As described above, the time from when the signal at the input terminal a becomes “H” level to stop the charging of the capacitor 27 until the output becomes “L” level is set as shown in FIGS. 2 and 6. It is time T.

In FIG. 1 (see the time chart of FIG. 6), since the node b is at the “H” level during standby, when the start signal ST enters the transistor 11, the flip-flop 1
A latch operation (that is, the left input of the flip-flop 12 is "L" and the right output of the flip-flop 12 is "H") is performed at 2, and at the same time, the output OUT becomes "H" level. Time T in FIG.
After that (when the voltage of the capacitor 27 is discharged to the set value), the node b changes from “H” to “L”. At the same time, the output OUT becomes "L" level and the reset signal RS
Rises and the transistor 17 is turned on, so that the flip-flop 12 is reset and the node c becomes "L" level. Since the potential of the node a remains at the “H” level while the signal of the node c is delayed by the delay circuit 15,
During that time, the reset signal RS is output. When the reset signal RS is output and the start signal ST is input, the delay circuit 15 causes the node a
Since the level of is not changed while the level of the node c is delayed, the reset signal RS is not interrupted.

The present invention is not limited to the embodiments, and various applications are possible. For example, the AND (logical product) circuit 19 may be a NAND (negative logical product circuit).

〔The invention's effect〕

As described above, according to the present invention, when the start signal is input to the timer circuit, the output rises without delay and the reset signal can be output with the pulse width specified by the delay circuit. The reset signal is not interrupted even if the start signal is input during output. As a result, the device controlled by the timer circuit is incompletely reset, and the next operation is not affected.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the time counting device itself used in the circuit, and FIG. 3 is a circuit diagram in which the essential parts of the circuit are detailed.
FIG. 4 is a conventional timer circuit diagram, FIG. 5 is a timing chart showing the operation of the time counting device itself used in the circuit, and FIG. 6 is a timing chart showing the circuit operation of FIG. 11, 17 ... N-channel type transistor, 12 ... Flip-flop, 15 ... Delay circuit, 16, 19 ... AND circuit, 18 ... Time counting device, 20 ... Inverter.

Claims (1)

[Claims] 1. The output is at a first logic level during standby, and when the input changes from a second logic level to a first logic level to start operation, after a set time, the output changes from the first logic level. A time counting device having a second logic level is provided, and a start signal of the timer operation of the time counting device is transmitted to an input of the time counting device through a start signal holding circuit and a delay circuit, and the output of the time counting device and the output of the time counting device. An output is obtained from a logical product circuit of the output of the start signal holding circuit, and means for obtaining a reset signal from the logical product circuit having the input of the time counting device and the inverted signal of the output of the time counting device as an input, A timer circuit characterized in that the output side of the means controls the input side of the delay circuit to a reset state.