JPH0620182Y2 - Power supply state holding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] A power supply state holding circuit that holds the power supply state during maintenance and replacement of a power supply control unit that controls power on / off of a power supply unit. , For the purpose of maintaining the power-on state of the power supply unit, in the power supply unit whose on / off switching is controlled according to the power control signal set by the power control unit, the power supply control unit removal period is A connection detection signal whose logic level is opposite to that of the logic level is input, and when the power supply control unit is removed, the reverse time of the logic level of the power supply control signal is delayed from the reverse time of the logic level of the connection detection signal to control the power supply. And a delay circuit for delaying the reverse time of the logic level of the connection detection signal from the reverse time of the logic level of the power supply control signal, and the power supply control signal via this delay circuit. Is used as a data input, and a connection detection signal via this delay circuit is also used as a latch input to hold the logic level of the power supply control signal at the logic level of the attachment period during the removal period.

[Industrial application field]

The present invention relates to a power supply state holding circuit that holds a power supply state of a power supply control unit that controls power-on / off of a power supply device when maintenance and replacement are performed.

[Conventional technology]

In a highly reliable system and a fault-tolerant computer (FTC), which has been emphasized in recent years, it is a necessary condition in the system configuration that maintenance work can be performed while the system is operating, that is, while the power is turned on.

The power supply unit controls the power on / off operation by the power supply control unit, but it is provided to fix the power on state to the power supply unit when maintenance replacement of the power supply control unit is performed while the power supply is on. It was necessary to operate the switch and hold the power on state before removing the power control unit.

[Problems to be solved by the device]

However, prior to maintenance replacement of the power supply control unit, the work of maintaining the power-on state by the switch operation is troublesome, and if the switch is operated incorrectly or is forgotten, remove the power supply control unit. As a result, the power supply may be inadvertently cut off.

On the other hand, the power supply control unit sends a single pulse signal when the power supply is turned on and off to control the turning on and off of the power supply device, thereby fixing the power-on state of the power supply device when the power supply control unit is removed. There is a method to eliminate the operation.

However, the single-shot pulse signal may be indistinguishable from noise and the like, and there is a problem in reliability as compared with the conventional level signal for controlling power on / off. That is, in a power supply device controlled by such a pulse signal, countermeasures against noise have become a major issue.

It is an object of the present invention to provide a power supply state holding circuit that can hold the power supply state of a power supply device in a power-on state with a simple configuration during maintenance and replacement of a power supply control unit.

[Means for Solving the Problems]

 FIG. 1 is a block diagram of the principle of the present invention.

The power supply device 13 is configured to control turning on / off of power according to a power control signal set by the power control unit 11.

The connection detection signal is a signal having a logic level whose height is opposite to that of the mounting period during the removal period of the power supply control unit 11.

The delay circuit 15 delays the reverse time of the logic level of the power supply control signal from the reverse time of the logic level of the connection detection signal when the power supply control unit 11 is removed, and reverses the logic level of the power supply control signal when the power supply control unit 11 is attached. The configuration is such that the reverse time of the logic level of the connection detection signal is delayed from the time.

The latch circuit 17 inputs the power supply control signal via the delay circuit 15 as data, and also uses the connection detection signal via the delay circuit as a latch input to set the logic level of the power supply control signal during the extraction period to the logic of the mounting period. It is a structure to hold at the level.

[Action]

According to the present invention, the delay circuit 15 makes it possible to make the reverse time of the logic level of the power supply control signal during the removal period of the power supply control unit 11 relative to the reverse time of the logic level of the connection detection signal relatively late during removal and earlier during mounting. it can.

Therefore, the latch circuit 17 which is stably latched by this connection detection signal prohibits the inversion of the logic level of the power supply control signal during the removal period of the power supply control unit 11, and can maintain the power supply state at the time of removal. That is, the power supply device 13 in the power-on state is the power supply control unit 1
Even if 1 is removed, the power-on state can be maintained without any special operation.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the embodiment of the present invention.

In the figure, a power supply control unit 21 and a power supply device 23 are connected via predetermined connectors 22 and 24, respectively, to a power supply control signal (hereinafter referred to as "PON") line 25 and a connection detection signal (hereinafter referred to as "INS"). Connected by line 27.

The power supply state holding circuit 30 of the power supply device 23 uses the PON line 25.
The PON delay circuit 31 connected to the INS line 27, the INS delay circuit 33 connected to the INS line 27, and the output of the PON delay circuit 31 are used as data inputs, and the output of the INS delay circuit 33 is used as a latch input. A latch circuit 3 that outputs a start signal (hereinafter, referred to as “PWR”) to be performed.
5 and.

In the PON delay circuit 31, two resistors and a capacitor, one of which is grounded, are connected in a T-shape, and a diode is connected in parallel to the input side resistor with the cathode being the input side. IN
In the S delay circuit 33, two resistors and a capacitor, one of which is grounded, are connected in a T-shape, and a diode is connected in parallel with the resistor on the input side with the anode on the input side.

In addition, each signal line connected to each connector 22 and 24 is
It is pulled up to a predetermined voltage by a pull-up resistor in the power supply device.

Here, PON is a level signal, which is turned on at a low level (hereinafter referred to as “L”) and high level (hereinafter, referred to as “L”).
It is indicated by "" H "". ) Indicates cutting. INS grounded in the power supply control unit 21 is connected to the connector by "L",
"H" indicates a state where the connector is removed. The latch circuit 35 holds the output when the latch input (INS) is at the high level and ignores the data input (PON).

The table shows the operation of the latch circuit 35.

FIG. 3 is a time chart explaining the operation of the delay circuit.

As shown in FIG. 3 (a), the PON delay circuit 31 causes a delay in the output signal when the input signal (PON) rises. In the INS delay circuit 33, as shown in FIG. 3 (b), the output signal is delayed when the input signal (INS) falls.

Note that the delay circuit that operates in this way is not limited to the circuit configuration shown in FIG.

FIG. 4 is a time chart for explaining the operation sequence of the embodiment of the present invention.

The operation of the embodiment of the present invention will be described below with reference to FIGS. 2 and 4.

When the power supply control unit 21 and the power supply device 23 are connected, the INS is “L” because it is grounded in the power supply control unit 21, and the latch circuit 35 of the power supply device 23 is in the non-latching state.

At this time, P is controlled by the power-on control of the power control unit 21.
When ON becomes “L”, this signal is transmitted to the PON delay circuit 31.
Via, it becomes the data input of the latch circuit 35 with almost no delay. Therefore, the PWR output from the latch circuit 35 immediately becomes "L" and the power is turned on.

While the power is on, if the connector 22 is removed for maintenance replacement of the power control unit 21 (pulling out the power control unit),
Both the PON line 25 and the INS line 27 are in the open state, but both PON and INS become "H" due to the pull-up resistors in the power supply state holding circuit 30.

When the PON becomes “H”, the diode inside the PON delay circuit 31 becomes reverse biased, and the PON (delays due to the integration time constant for charging the capacitor whose one side is grounded from the resistor connected to both ends of the diode. (Data input / output) changes to "H".

Further, when INS becomes “H”, the diode inside the INS delay circuit 33 becomes a forward bias state and the capacitor whose one side is grounded is immediately charged through the diode, so that INS (latch input) immediately becomes “H”. It changes to ".
Due to this interaction, PON (data input) is INS
It is input to the latch circuit 35 later than (latch input) (FIG. 4). Therefore, the latch circuit 35 is
PWR is held in a closed state (“L”) because the latched state is set earlier than the change of PWR.

When the connector 22 of the power supply controller 21 is connected (power supply controller mounted), PON and INS become "L" again.
The INS that becomes "L" is delayed by the integration time constant that the diode inside the INS delay circuit 33 is in the reverse bias state and the capacitor connected to both ends of the diode discharges the capacitor whose one side is grounded. Latch input) changes to "L".

Further, in the PON that becomes “L”, the diode inside the PON delay circuit 31 becomes a forward bias state and the capacitor whose one side is grounded is immediately discharged through the diode, so that the PON (data input) immediately becomes “L”. It changes to ".
Due to the interaction between the PON delay circuit 31 and the INS delay circuit 33, INS (latch input) is input to the latch circuit 35 later than PON (data input) (fourth time).
Therefore, the output (PWR) of the latch circuit 35 does not change.

Power-off control sets PON to "H", but PON is PO
The N delay circuit 31 acts to delay the data for a predetermined time to input the data to the latch circuit 35, and the operation opposite to that at the time of the closing control causes PWR to be "H" and the power supply to be cut off. It should be noted that this disconnection operation is delayed by the PON delay circuit 31, but does not particularly hinder the power supply device 23.

Also, when removing the power supply control unit 21 while the power is off,
Since ON (data input) remains "H", INS
The change of (latch input) changes the output of the latch circuit 35 (PW
R) is not affected and the power-off state (PWR = “H”) is maintained.

The power supply state holding circuit 30 of the present invention can be similarly realized by inverting the logic of one or both of PON and INS in this embodiment.
However, in this case, the respective delay circuits 31 and 33 are appropriately configured such that the logical inversion of PON in the removal period of the power supply control unit 21 is made relatively late in the removal and early in the installation in comparison with the logical inversion of INS. There is a need to. For example,
When the logic of INS is inverted, the INS delay circuit 3
3 has the same configuration as the PON delay circuit 31.

Further, since the power supply device 23 using the power supply state holding circuit of the present invention is configured to operate by the level signal (PON), it has sufficient resistance to noise and the like.
By inserting known simple noise filters between the connector 24 and the delay circuits 31 and 33, respectively,
A malfunction of the latch circuit 35 can be avoided.

[Effect of device]

According to the present invention, even if the power supply control unit is removed from the power supply device in the power-on state, the power supply state is automatically maintained. Therefore, when the power supply control unit is to be replaced for maintenance while the power is on, it is not necessary to operate switches or the like, and it is possible to easily prevent accidental disconnection of the power supply device due to an operation error.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a time chart explaining the operation of each delay circuit, and FIG. It is a time chart explaining an operation sequence. In the figure, 11 is a power supply control unit, 13 is a power supply device, 15 is a delay circuit, 17 is a latch circuit, 21 is a power supply control unit, 22 and 24 are connectors, 23 is a power supply device, and 25 is a power on / off control signal (PON). Reference numeral 27 is a connector connection detection signal (INS) line, 30 is a power supply state holding circuit, 31 is a PON delay circuit, 33 is an INS delay circuit, and 35 is a latch circuit.

Claims (1)

[Scope of utility model registration request] 1. A power supply device (1) in which turning on and off of a power supply is controlled according to a power supply control signal set by a power supply control section (11).
In 3), a connection signal that is logically inverted during the removal period of the power supply control unit (11) is input, and delays the logic inversion of the power supply control signal with respect to the connection detection signal when the power supply control unit (11) is removed. By delaying the logic inversion of the connection detection signal with respect to the power supply control signal when the power supply control unit (11) is attached, a delay for the power-on state not to transition at the moment the power supply control unit is removed. A circuit (15) and a latch circuit (17) for holding the logic state of the power supply control signal during the extraction period by using the power supply control signal via the delay circuit (15) as a data input and the same connection detection signal as a latch input. And a start signal for turning the power supply device on and off by the latch circuit (17), and a power supply state holding circuit.