JPH0620341B2 - Motor overcurrent prevention circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor overcurrent prevention circuit preferably used for a DC motor for driving a small printer used for an electronic cash register or the like.

2. Description of the Related Art A small-sized printer used for an electronic cash register usually uses a DC motor as a driving device. In the above small printer, in order to realize the downsizing, the paper is fed by one motor, the print head is moved,
In many cases, a mechanism for performing operations such as ink ribbon feeding is adopted. In a motor used in such a printer, it is necessary to promptly stop the rotating motor at a predetermined timing in addition to simply driving the motor.
The drive circuit for controlling the drive and stop is realized by, for example, the configuration shown in FIG.

Referring to FIG. 4, a fifth node is provided on the bases of both the PNP transistor TR2 and the NPN transistor TR1.
H-level stop signal S shown in FIGS. 1 and 2
And the drive signal D respectively, the transistor T
R2 is turned off and transistor TR1 is turned on. Therefore, the motor drive current Id flows through the motor 15 from the power supply line 12 that is energized by the power supply voltage + Vcc, and the motor 15 is driven by this.

On the other hand, when the drive signal D and the stop signal S of L level are applied to the bases of the transistors TR1 and TR2, respectively, the transistor TR2 becomes conductive and the transistor TR2
1 is in the cutoff state. As a result, the power line 12
As shown in FIG. 4, a control current Is flows from therethrough, whereby the rotating motor 15 is quickly stopped. Driving and stopping of the motor 15 are controlled by such a driving circuit.

Problems to be Solved by the Invention However, if the motor 15 is overloaded due to a paper jam of a small printer, or the transistor TR2 causes a short-circuit failure, the drive circuit 14 has a structure as shown in FIG. The short-circuit current I flows through. As a result, the transistor TR1 which has not failed
There is a problem in that the power supply and the motor 15 generate abnormal heat. Further, when the transistor TR1 causes a short circuit failure while the motor is stopped, the short circuit current I flows in the same manner, which also causes a problem that the above-mentioned abnormal situation occurs.

An object of the present invention is to solve the above-mentioned problems and provide a motor overcurrent prevention circuit capable of advantageously protecting a drive unit, a switching unit and the like from an abnormal current or the like.

Means for Solving the Problems In the present invention, (a) the power supply + Vcc, the motor 3, the first switching means TR1, and the current detection resistor RS are connected in series, and (b) the motor 3 has Second switching means TR2 in parallel
And (c) the first switching means TR1 and the current detection resistor R
The integrating circuit 8 is composed of a resistor R4, one end of which is connected to a connection point with one end of S, and a capacitor C1 which is connected between the other end of the resistor R4 and the other end of the current detection resistor RS. (D) The output of the capacitor C1 in the integrating circuit 8 and the predetermined reference voltage V0 are given to the comparison circuit 9, and (e) the output of the capacitor C1 exceeds the reference voltage V0 in response to the output of the comparison circuit 9. At this time, the latch circuit 1 is in the set state in which the output of one level remains derived, and keeps the output at the other level in response to the reset signal.
0, (f) a reset signal generation source for generating a reset signal and giving it to the latch circuit 10, and (g) at the time of starting the motor 3, the drive signal D is derived after the stop signal S is cut off, and at the time of stop, the drive signal D In response to the signal source that derives the stop signal S after the interruption of D, and (h) the output of the latch circuit 10 and the drive signal D from the signal source, and the output is at the other level, the drive signal D When given, the first switching means T
When R1 is made conductive and the drive signal D is cut off, the first switching means T
First logic circuits 6 and 7 that shut off R1 and shut off the first switching means TR1 when the output is at the one level; and (i) the output of the latch circuit 10 and the stop signal S from the signal source. And the output is at the other level, when the stop signal S is applied, the second switching means T
When R2 is made conductive and the stop signal S is cut off, the second switching means T
And a second logic circuit (4, 5) for shutting off R2 and shutting off the second switching means TR2 when the output is at the one level.

Operation According to the present invention, when the latch circuit 10 is reset by the reset signal from the reset signal generation source and the output remains at the other level, the start signal D is set to the first logic circuit for starting the motor 3. When given to 6, 7, the first
The switching means TR1 is brought into conduction, whereby the current Ib flows through the motor 3 via the current detection resistor RS and the motor 3 is started. Before the drive signal D is given,
The stop signal S is cut off, which cuts off the second switching means TR2 and thus the first and second
The switching means TR1 and TR2 do not conduct at the same time. When the motor 3 is stopped, the drive signal D is cut off to cut off the first switching means TR1, and then the stop signal S is generated to turn on the second switching means TR2, whereby the braking current is supplied to the motor 3. Is flows to enable a rapid stop.

While the first switching means TR1 is conducting and the second switching means is shut off to drive the motor 3,
When an overcurrent flows through the motor 3, the voltage of the current detection resistor RS rises, the voltage is integrated by the integrating circuit 8 and given to the comparison circuit 9, and when the integrated output exceeds the reference voltage V0, the latch circuit 10 is set, whereby the output of the latch circuit 10 changes from the other level to the one level, whereby the first switching means TR1 has the first level.
While being cut off by the logic circuits 6 and 7, the second switching means TR2 is in a state of being cut off by the second logic circuits 4 and 5.

Furthermore, the first switching means TR1 is cut off,
When the output voltage of the integrating circuit 8 exceeds the reference voltage V0 due to an overcurrent flowing through the current detecting resistor RS for some reason while the switching means TR2 is conducting, the output of the latch circuit 10 is the same as described above. On the other hand, it becomes the level, and at this time also the first and second switching means TR
1, TR2 are the first and second logic circuits 6, 7: 4, 5
Is kept in the cutoff state.

Embodiment FIG. 1 is a diagram showing an electrical configuration of a motor drive circuit 2 including a protection circuit 1 which is an embodiment of the present invention. The motor drive circuit 2 includes a DC motor 3, which is a drive device for driving a small printer used for an electronic cash register, an NPN type transistor TR1, a PNP type transistor TR2, a protection circuit 1, and the like. The motor 3 is powered by the power supply voltage + Vcc.
The emitter of the transistor TR2 is connected to the power supply line l1, the collector is connected to the collector of the transistor TR1 via a connection point A, and the output of the motor 3 is given to the connection point A. . The emitter of the transistor TR1 is grounded via the current detection resistor RS.

The base of the transistor TR2 is connected to the power supply line 11 via the resistor R1, and is connected to the output terminal of the AND circuit 5 via the resistor R2 and the inverter 4. The base of the transistor TR1 is connected to the power supply line 11 via the resistor R3, and the NAND is connected via the inverter 6.
It is connected to the output terminal of the circuit 7. The two inverters 4 and 6 are provided to invert the outputs of the AND circuit 5 and the NAND circuit 7 and convert them into voltage levels for driving the two transistors TR1 and TR2. Connection point B between the emitter of the transistor TR1 and the current detection resistor RS
Is an integrating circuit 8 including a resistor R4 and a capacitor C1.
Is connected to the non-inverting input terminal of the comparator 9, and the reference voltage V0 is applied to the inverting input terminal. It should be noted that the current detecting resistor RS, the integrating circuit 8 and the comparator 9 constitute an abnormal current detecting unit 11 described later.

The output of the comparator 9 is given to a set input terminal S of a latch circuit 10 realized by, for example, an RS flip-flop, and the output from the output terminal of the latch circuit 10 is the AND circuit 5 and the NAND circuit. 7 to each one terminal. Also, these AN
A stop signal S and a drive signal D, which will be described later, are applied to the other terminals of the D circuit 5 and the NAND circuit 7, respectively, and a protection circuit reset signal R, which will be described later, is input to the reset input terminal of the latch circuit 10. The two inverters 4, 6, the AND circuit 5, the NAND circuit 7 and the latch circuit 10 constitute a switching control means.

2 and 3 are timing charts for explaining the operation of the motor drive circuit 2. 1 and 2
The operation of the motor drive circuit 2 when the motor 3 is driven will be described with reference to the drawings. Note that the latch circuit 10 is normally in the reset state, and the output terminal
An H level signal is given to one terminal of each of the AND circuit 5 and the NAND circuit 7.

At time t0, when the stop signal S becomes L level as shown in FIG. 2 (2) and this is input to the other terminal of the AND circuit 5, the output of this AND circuit 5 becomes L level, and therefore the output of the inverter 4 Q2 becomes H level as shown in FIG. In this way, the H-level output Q2 is P
Given to the base of the NP type transistor TR2,
This transistor TR2 is turned off.

On the other hand, at time t1, the drive signal D becomes H level and is input to the other terminal of the NAND circuit 7 (see the same figure).
(See (1)), the NAND circuit 7 gives an L level signal to the inverter 6, whereby the output Q1 of the inverter 6 becomes H level as shown in FIG. When the H-level output Q1 is applied to the base of the NPN transistor TR1 as described above, the transistor TR1 becomes conductive.

In this way, at time t1, the transistor TR2 is in the cutoff state and the transistor TR1 is in the conduction state. Therefore, the motor drive current Id flows from the power supply line 11 toward the connection point B via the motor 3 and the transistor TR1, and the motor 3 is driven by this. The reason why the levels of the stop signal S and the drive signal D are not changed at the same time is as follows. That is, for example, when the drive signal D is set to the H level at time t0, both the transistors TR1 and TR2 are rendered conductive, whereby the power supply line 11 is grounded and short-circuited. Therefore, when the motor 3 is driven, the level of the drive signal D is switched with a slight delay from the level of the stop signal S in order to prevent the short circuit. Further, as will be described later, the same operation is performed when the motor 3 is stopped.

Next, the operation of stopping the motor 3 will be described with reference to FIGS. 1 and 3. Even in this case, the latch circuit 10 is in the reset state, and the H-level signal is output from the output terminal.

Referring to FIG. 3, at time t6, drive signal D attains an L level as shown in (1) of the same figure, and this is input to the other terminal of NAND circuit 7. As a result, an H level output is given from the NAND circuit 7 to the inverter 6,
The output Q1 of the inverter 6 becomes L level (see (8) in the same figure). When this L level output Q1 is given to the base of the PNP type transistor TR1, this transistor T1
R1 is cut off.

At time t7, the stop signal S changes to H as shown in FIG.
When the level becomes a level and is input to the other terminal of the AND circuit 5, an H level output is given from the AND circuit 5 to the inverter 4, whereby the output Q of the inverter 4 is output.
2 becomes the L level (see (7) in the same figure). When the L-level output Q2 is applied to the base of the transistor TR2, the transistor TR2 becomes conductive.

Thus, at time t7, the transistor TR1 is in the cutoff state and the transistor TR2 is in the conductive state. Therefore, the power supply line 11 and the connection point A are short-circuited, whereby the braking current Is flows through the motor 3 and the motor 3 is stopped.

In this way, when the latch circuit 10 is in the reset state, the drive signal D of H level and the stop signal S of L level are provided.
Are applied to the other terminals of the AND circuit 5 and the NAND circuit 7, respectively, the motor 3 is driven, while the L-level drive signal D and the H-level drive signal S are applied to the AND circuit 5 and the NAND circuit 7, respectively. Then, the motor 3 is stopped.

Next, the operation of the protection circuit 1 will be described with reference to FIG. At time t1, as described above, the transistor T
With R2 cut off and the transistor TR1 conductive, the motor 3 is driven. At this time, the motor 3
Is driven from the stopped state, the load is large, and the potential at the connection point B sharply rises as shown in FIG. 2 (3), and the peak portion P1 is formed. However, when the motor 3 starts to drive, the load becomes small, so that the potential becomes stable.

The peak portion P1 of the voltage at the connection point B at the time of starting the motor 3 is smoothed by the integrating circuit 8 and given to the comparator 9. In the integrating circuit 8, the reference voltage V0 applied to the inverting input terminal of the comparator 9 is set to a level higher than the level output from the integrating circuit 8 by the peak portion P1. Therefore, nothing is output from the comparator 9 depending on the peak portion P1 when the motor 3 is started.

Therefore, for example, when an abnormal current flows due to load on the rotating motor 3 at time t2 or a short-circuit failure in the transistor TR2, the potential at the connection point B is as shown in FIG. 2 (3). Then, the peak portion P2 is formed. As a result, when the output of the integrating circuit 8 exceeds the reference voltage V0 at time t3 (see (4) in the same figure), the comparator 9 gives a constant level output to the set input terminal of the latch circuit 10. The latch circuit 10 is set by the output from the comparator 9. As a result, the output from the output terminal becomes L level, and this is applied to one terminal of the AND circuit 5 and the NAND circuit 7, respectively.

Therefore, in AND circuit 5, regardless of the signal level of stop signal S, inverter 4 is always provided with an L level output. As a result, the transistor TR2 is always turned off. On the other hand, in the NAND circuit 7 as well, regardless of the signal level of the drive signal D, the inverter 6 has the H level.
Level output is provided, which causes the transistor T
R1 is always shut off. When the latch circuit 10 is set in this way, the two transistors TR are irrespective of the signal levels of the stop signal S and the drive signal D.
Both 1 and TR2 are cut off.

Thus, at time t3, the transistors TR1 and TR2 are
When both are turned off, the potential at the connection point B immediately becomes 0 level. The output of the comparator 9 does not immediately reach the 0 level, but falls below the reference voltage V0 at time t4, for example, and then the potential gradually decreases. Therefore, the output of the comparator 9 becomes 0 level after time t4 (see (5) in the same figure). It should be noted that the latch circuit 10 includes a comparator 9
The set state is maintained by catching the rising edge of the output from, and thereafter, the set state is maintained unless the reset signal R is input to the reset input terminal.

Next, the operation of the protection circuit 1 while the motor 3 is stopped will be described with reference to FIG.

At time t7, as described above, the transistor TR1
Is in a cutoff state and the transistor TR2 is in a conductive state, so that the motor 3 is stopped. Therefore, the potential at the connection point B becomes 0 level as shown in FIG.

Therefore, at time t8, for example, when an abnormal current due to a short circuit failure of the transistor TR1 flows, the potential at the connection point B starts to rise rapidly, and a peak P3 is formed. As a result, for example, at time t9, the output from the integrator circuit 8 becomes the reference voltage V as shown in FIG.
When it exceeds 0, the output of the comparator 9 is given to the set input terminal of the latch circuit 10, and the latch circuit 10 is set. As a result, as described above, the transistor TR
Both 1 and TR2 are cut off, and the unit of the connection point B immediately becomes 0 level. Further, the output from the integrator circuit 8 does not immediately become 0 level as described above, and the time t1
At 0, the voltage drops below the reference voltage V0, and then gradually decreases.

In this way, if a short-circuit fault occurs between the emitter and collector of either one of the transistors TR1 and TR2 due to accidental accident or overload of the motor 3, and an abnormal current flows, the abnormality detection unit 11 At, the occurrence of an abnormal current is detected and the latch circuit 10 is set. As a result, the two transistors TR1 and T
Both R2 are cut off and two transistors TR
1 and TR2 can be protected from the abnormal current.

In order to set the latch circuit 10 in the set state to the reset state, the reset signal R may be manually input to the reset input terminal R of the latch circuit 10, for example. To further describe the configuration, the motor 3, the transistor TR1, and the current detection resistor RS are connected in series to the DC power supply + Vcc. A transistor TR2 is connected in parallel to the motor 3.

In the integrating circuit 8, one end of the resistor R4 is connected to a connection point B between the transistor TR1 and one end of the current detection resistor RS. The capacitor C1 is connected between the other end of the resistor R4 and the other end of the current detecting resistor RS.

In this way, according to this embodiment, it is possible to prevent the transistors TR1 and TR2, the motor 3, etc. from being damaged due to the generation of the abnormal current.

As described above, according to the present invention, the first switching means T
When R1 is conductive and the second switching means TR2 is cut off to drive the motor 3 and an overcurrent occurs, the latch circuit 10 is set and the first and second logic circuits 6, 7; , 5, the first and second switching means TR1 and TR2 are kept in the cutoff state.

Further, according to the present invention, while the motor 3 is at rest, the first switching means TR1 is cut off and the second switching means TR2 is conducting at this time, whereby the braking of the motor 3 is achieved. Has become. When an overcurrent flows in this state, the latch circuit 10 is set and the first switching means TR1 is kept in the cut-off state, and the second switching means TR2 is also cut off.

When the overcurrent flows in this way, both the first and second switching means TR1 and TR2 are brought into a cutoff state.

Further, according to the present invention, the second switching means TR2 is connected in parallel to the motor 3, and when the motor 2 is started, the second switching means TR2 is cut off by cutting off the stop signal S, and then the driving signal D is generated. By making the first switching means TR1 conductive, it is possible to reliably prevent simultaneous conduction of the first and second switching means TR1, TR2.

Further, according to the present invention, when the motor 3 is stopped, first, the first switching means TR1 is cut off by cutting off the drive signal D, and thereafter, the second switching means TR2 is made conductive by the stop signal S to generate the braking current Is. It is made to flow and the motor 3 is stopped rapidly. Thus, also when the motor 3 is stopped, the first and second switching means TR1, TR2 are also provided.
It can be surely prevented that they are simultaneously conducted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a motor drive circuit 2 which is an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the motor drive circuit 2 while the motor 3 is being driven. FIG. 3 is a timing chart for explaining the operation of the motor drive circuit 2 when the motor 3 is stopped, and FIG. 4 is a typical prior art motor drive circuit 14
5 is a block diagram showing the electrical configuration of the motor drive circuit 14, FIG. 5 is a waveform diagram of the stop signal S and the drive signal D supplied to the motor drive circuit 14, and FIG. 6 is a diagram for explaining the operation of the motor drive circuit 14. 1 ... Protection circuit, 2 ... Motor drive circuit, 3 ... Motor, 4, 6 ... Inverter, 5 ... AND circuit, 7 ...
NAND circuit, 8 ... Integrator circuit, 9 ... Comparator, 10 ...
… Latch circuit, 11 …… Abnormal current detector, TR1, TR
2 ... Transistor, RS ... Resistance for current detection

Claims (1)

[Claims] 1. A power source + Vcc, a motor 3, and a first
The switching means TR1 and the current detection resistor RS are
(B) second switching means TR2 connected in series in parallel with the motor 3;
And (c) the first switching means TR1 and the current detection resistor R
The integrating circuit 8 is composed of a resistor R4, one end of which is connected to a connection point with one end of S, and a capacitor C1 which is connected between the other end of the resistor R4 and the other end of the current detection resistor RS. (D) The output of the capacitor C1 in the integrating circuit 8 and the predetermined reference voltage V0 are given to the comparison circuit 9, and (e) the output of the capacitor C1 exceeds the reference voltage V0 in response to the output of the comparison circuit 9. At this time, the latch circuit 1 is in the set state in which the output of one level remains derived, and keeps the output at the other level in response to the reset signal.
0, (f) a reset signal source that generates a reset signal and gives it to the latch circuit 10, and (g) when the motor 3 is started, the drive signal D is derived after the stop signal S is cut off, and when the motor 3 is stopped, the drive signal D In response to the signal source that derives the stop signal S after the interruption of D, and (h) the output of the latch circuit 10 and the drive signal D from the signal source, and the output is at the other level, the drive signal D When given, the first switching means T
When R1 is made conductive and the drive signal D is cut off, the first switching means T
First logic circuits 6 and 7 for shutting off R1 and shutting off the first switching means TR1 when the output is at the one level, and (i) the output of the latch circuit 10 and the stop signal S from the signal source. And the output is at the other level, when the stop signal S is applied, the second switching means T
When R2 is made conductive and the stop signal S is cut off, the second switching means T
And a second logic circuit (4, 5) for shutting off R2 and shutting off the second switching means TR2 when the output is at the one level.