JPH06208546A - Program download system - Google Patents

Abstract

PURPOSE:To shorten a downloading time by enabling respective slave-side microprocessors to read information on a bus simultaneously with a master side with a downloading start indication from a master-side microprocessor. CONSTITUTION:A download control part 31 in the master-side microprocessor 3 sets a downloading frequency in a counting register and sends a common memory read indication and a local memory write indication, and also sends the downloading start indication to a control line 4 for the slave-side microprocessors 6 while performing master-side downloading. After 1st downloading, the address registers of a common memory 2 and local memories 5 are added for next downloading and the contents of a count register are decreased by one. The slave-side microprocessors 6, on the other hand, receive the downloading start indication and write the information on the bus 1 in the local memories 5. This cycle is repeated until the count register reaches 0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program download system, and more particularly to a program download system from a common memory to a plurality of local memories.

[0002]

2. Description of the Related Art Conventionally, when a plurality of microprocessors download the same program from a common memory to their own local memory, each microprocessor independently downloads from the common memory to its own local memory. While the microprocessor was downloading, no other microprocessor could download.

[0003]

Therefore, in the above-mentioned conventional program download method, there is a problem in that each microprocessor takes a download time corresponding to the number of microprocessors to download the program.

[0004]

According to the program download method of the present invention, a common memory and a plurality of microprocessors are connected on one bus, and all the microprocessors are transferred from the common memory to their own local memory. In a program download system for downloading the same program, a first download control unit that controls the master side microprocessor to write the program in its own local memory and at the same time notifies the slave side microprocessor of the download start. , A control signal line for transmitting a download start instruction from the first download control section, and a slave side microprocessor for receiving the download start instruction from the control signal line at the same time as the master side microprocessor. Serial and a second download control unit for performing control to write the program to their local memory reads information on the bus.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, a common memory 2, a master side microprocessor 3 and a plurality of slave side microprocessors 6 are connected on one bus 1, and A local memory 5 is connected to each of the processors 3 and 6. A control line 4 for notifying a download instruction is connected between the microprocessor 3 and the microprocessor 6.

FIG. 2 is a block diagram of the download control unit A31 in the microprocessor 3 on the master side in FIG. 1. The address register 32 of the common memory 2, the address register 34 of the local memory 5, and the address adder 3 are shown.
3 and 35, a common memory read / local memory write controller 36, a count register 37 that counts the number of downloads, and a count subtractor 38.

FIG. 3 is a block diagram of the download control unit B61 in the microprocessor 6 on the slave side of FIG. 1, which includes an address register 62 of the local memory 5, an address adder 63, and a local memory write control unit 64. Become.

Next, the operation at the time of downloading will be described with reference to FIGS.

First, the download control unit A31 in the microprocessor 3 on the master side sets the number of download transfers in the count register 37. Next, the common memory read / local memory write control unit 36 of the download control unit A31 issues a common memory read instruction 39 and a local memory write instruction 40, and the master side download is performed. At the same time, it issues a download start instruction to the control line 4 to the slave side microprocessor 6. 1
When the second download is completed, the contents of the address register 32 of the common memory 2 and the contents of the address register 34 of the local memory 5 are added by the internal control lines 41 and 42 using the address adder 33 to perform the next download. , The content of the count register 37 is decremented by 1 using the count subtractor 38 via the internal control line 43.

On the other hand, the slave microprocessor 6
In the local memory write control unit 64, when receiving the download start instruction from the master side microprocessor 3 through the control line 4, the information read instruction 6 on the bus
5. The local memory write instruction 66 is given to write the information on the bus 1 to the local memory 5. When the writing is completed, the contents of the address register 62 of the local memory 5 are added by the internal control line 67 using the address adder 63 for the next download.

With the above, one download cycle is completed. Repeat the download cycle in the same way,
When the content of the count register 37 becomes 0, the download ends.

[0013]

As described above, according to the present invention, since each slave microprocessor reads information on the bus at the same time as the master microprocessor in response to a download start instruction from the master microprocessor,
The processor can be downloaded from the common memory to the local memory of each microprocessor only once, which has the effect of significantly reducing the download time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a download control unit A31 in the microprocessor 3 on the master side in FIG.

FIG. 3 is a block diagram of a download control unit B61 in the microprocessor 6 on the slave side in FIG.

[Explanation of symbols]

 1 Bus 2 Common Memory 3 Microprocessor on Master Side 4 Control Line 5 Local Memory 6 Microprocessor on Slave Side 31 Download Control Unit A 61 Download Control Unit B

Claims (1)

[Claims] 1. A master in a program download method in which a common memory and a plurality of microprocessors are connected on one bus, and all the microprocessors download the same program from the common memory to their own local memory. And a first download control section for notifying the slave side microprocessor of the start of download at the same time that the microprocessor on the side controls the writing of the program in its own local memory, and the download start from the first download control section. A control signal line for transmitting an instruction and a download start instruction from the control signal line are received, and the microprocessor on the slave side reads the information on the bus at the same time as the microprocessor on the master side. The A program download method comprising: a second download control unit that controls to write a program.