JPH06232893A - Cell resolving multiplex processor - Google Patents

Abstract

PURPOSE:To provide a cell resolving multiplex processing system for arbitrarily setting a bit rate to be used for each channel by providing one buffer memory for preserving cells for each virtual channel (VC) and separately preparing a control memory for keeping the order of cells to be received for each VC. CONSTITUTION:At a cell resolution control part 2, first of all, concerning the cells stored in a buffer memory 12, the payload part of a bank designated by reading the address of a first control memory 13 is read out, and the payload parts are successively read out to the final cell by referring to the chain information of the cells of the VC in a third control memory 15. Then, the clock of a time division multiplex highway is outputted synchronously with a frame pulse 8. At the same time, the bank reading the payload part is written at the end of a control queue 16 as a non-used bank. Thus, the required memories can be miniaturized by resolving the cell into fixed bit rate data 11 of the time division multiplex highway while dynamically using the memory 12.

Description

Detailed Description of the Invention

The present invention relates to an ATM system (Asynchronou
s Transfer Mode). According to the present invention, an input ATM cell is input to a virtual channel (VC: Virt).
ualChannel: VC = VPi + VCi (hereinafter referred to as VC)), the present invention relates to a cell disassembling / multiplexing apparatus for disassembling into frame rate on a time division multiplexed data highway and fixed bit rate data synchronized with a clock.

[0002]

2. Description of the Related Art A conventional cell disassembling and multiprocessing system is ATM.
When decomposing cells into fixed bit rate data of time division multiplexed data highway, for N types of VC cells,
A time-division multiplexed highway clock to be input is provided by providing N buffer memory control units of a FIFO format for storing cells in a one-to-one correspondence with VCs and storing them in an orderly manner, and N buffer memories. And frame pulse to VC
, The data is read from the buffer memory indicated by VC, and output to the time division multiplexed data highway.

[0003]

In the above-mentioned conventional cell disassembling / multiplexing method, it is necessary to make the buffer memory for additional delay the size corresponding to the data rate of the disassembled fixed bit rate data. It was Therefore, in order to use the fixed bit rate data of different speeds, it is necessary to set the size of all the buffer memories to the buffer memory size of the maximum fixed bit rate or to limit the VC to be used for each bit rate. there were.

For example, setting 6 ms as an additional delay,
Consider a case where 32 channels of fixed bit rate data of 64 Kbps and 2 channels of fixed bit rate data of 1.5 Mbps are accommodated.

64 Kbps: 1 channel Necessary memory = 384 bits = 64 Kbps × 6 ms 1.5 Mbps: 1 channel Necessary memory = 9216 bits = 1.5 Mbps × 6 ms Therefore, if any time slot of time division multiplexing can be used, the required memory as a whole is: required memory = 313 Kbit = (32 + 2) × 9216, and VC to be used for each constant bit rate speed
If it is limited to, necessary memory = 31 Kbit = 32 × 384 + 2 × 921
6, the memory used can be reduced. But,
Overall fixed bit rate speed is less than overall 1.5 Mb
Even if only 3 channels of ps are to be accommodated, the required memory is 28Kbit, which is small, but cannot be used because the memory that can be used for each VC is limited.

According to the present invention, one buffer memory is provided for each VC, and a control memory for keeping the order of cells received for each VC is separately prepared, so that the buffer memory is dynamically used. It is an object of the present invention to provide a cell disassembling / multiplexing method that can minimize the amount of use of the cell and can arbitrarily set the bit rate that can be used for each channel.

[0007]

According to the present invention, in a cell disassembling / multiplexing apparatus for converting an ATM cell into time division multiplex data, a buffer memory composed of a plurality of banks for storing a payload portion of the cell and arrival The cell storage control unit that stores the payload part of the cell in an unused bank and outputs the address of the bank, the control memory that holds the address for each virtual channel, the frame pulse and clock of the time division multiplex highway Based on the above, the address in the control memory is read for each virtual channel designated by the host device, the data of the data unit of the time division multiplex highway is read from the bank indicated by the address and is output as the time division multiplex data, and the bank is also output. And a cell disassembly control unit in which an unused bank is provided. That.

The cell storage control unit is provided with means for accumulating addresses of unused banks in a queue format. When a cell arrives, the cell accumulation control unit reads the bank address from the head of the queue and stores the payload portion of the cell. The cell disassembly control unit may include a unit that writes the address of the bank whose output of the payload unit has been completed to the end of the queue.

The control memory includes a first control memory for storing the address of the bank in which the first cell is stored and a second control memory for storing the address of the bank in which the last cell is stored for each virtual channel. And a third control memory for storing chain information of bank addresses for each virtual channel.

Further, the cell disassembly control unit can include additional delay means for absorbing a fluctuation in the arrival interval of cells by adding a fixed amount of cell delay at the beginning of cell disassembly.

[0011]

The payload portion of the arrived cell is stored in each bank by the cell storage control unit in the buffer memory having a bank structure in which the buffer memory is logically divided. This storage is
The address of an unused bank is extracted from the control queue that manages the queue of the addresses of the unused banks. Then, for each VC, the address of the bank storing the head cell of the cell and the address of the bank storing the last cell are stored in the first control memory and the second control memory, respectively. Further, the chain information for chaining from the address of the first cell to the address of the last cell is stored in the third control memory.

In the cell disassembly control unit, for the cells thus stored in the buffer memory, the address of the first control memory is first read, the payload part of the bank designated by the address is read, and the last and the last are sequentially read. Up to the cell, the payload section is read by referring to the chain information of the cell of the VC of the third control memory, and is output in synchronization with the clock and frame pulse of the time division multiplex highway. In addition, the bank from which the payload part is read is written at the end of the control queue as an unused bank.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the structure of an ATM cell disassembling / multiplexing apparatus according to an embodiment of the present invention. This embodiment is ATM
In the cell disassembling / multiplexing processing device for converting cells into time division multiplexed data, a feature of the present invention is that a buffer memory 12 composed of a plurality of banks in which payload parts of cells are stored and a payload part of arriving cells are not stored. The cell storage control unit 1 which stores the address of the bank to be stored in the bank to be used, the control memories 13, 14 and 15 which holds the address for each virtual channel, the frame pulse and the clock of the time division multiplex highway. Based on this, the address in the control memory is read for each virtual channel specified by the host device, the data of the data unit of the time division multiplex highway is read out from the bank indicated by the address and output as time division multiplex data, and the bank And a cell disassembly control unit 2 which is an unused bank.

Further, the structure of the cell disassembling / multiplexing apparatus of this embodiment will be described in detail.

The cell on the ATM cell highway 5 is the first
It is input to the cell storage control unit 1 via the clock transfer unit 6 and the header logical channel conversion unit 7. Further, the clock of the time division multiplexed data highway for outputting the time division multiplexed data obtained by decomposing the cells and the frame pulse 8 are input to the cell disassembly control unit 2 via the output logical channel conversion means 9. The time division multiplex data created by the cell division control unit 2 is sent through the second clock transfer means 10 to the fixed bit rate data 1 of the time division multiplex highway.
It is output as 1.

Further, the apparatus of this embodiment has a sequence controller 4, a buffer memory 12, a first control memory 13, and a second memory.
Control memory 14, a third control memory 15, and a control queue 16, and the memory control unit 3 is connected to the cell accumulation control unit 1 and the cell disassembly control unit 2 to control the above memory.

The cell storage control unit 1 receives the output of the header logical channel conversion means 7 and receives a buffer memory address read control unit 101 and a payload write control unit 10.
2. A sequence number check means 103 and a buffer memory address write control unit 104 are provided. Further, the cell disassembly control unit 2 receives the output of the output logical channel conversion unit 9 and receives the buffer memory address read control unit 2
01, this buffer memory address read control unit 20
Payload read control unit 20 to which the output of 1 is input
2. Transmission completion bank write control unit 20 to which the read operation end output of the payload read control unit 202 is input
3, an idle data transmission control unit 204, a multiplexed data output selection unit 205 to which the payload section read by the payload read control unit 202 and the output of the idle data transmission control unit 204 are input.

Each part will be further described.

The buffer memory 12 has a structure for accumulating the received cells in an area logically divided into a certain size called a bank.

The first control memory 13 uses the logical channel designated by the upper control system corresponding to the VC of the received cell as an address, and receives the most of the received cells corresponding to the logical channel stored in the buffer memory 12. The buffer memory address of the bank accumulating a cell having an early arrival time (hereinafter referred to as a top cell) is stored as data. The second control memory 14 is a buffer memory of a bank in which a cell having the latest arrival time (hereinafter referred to as a last cell) among reception cells corresponding to the logical channel stored in the buffer memory 12 using the logical channel as an address is stored. The address is stored as data. Third control memory 1
Reference numeral 5 designates a buffer memory address indicated by the first control memory 13 as an address, and a buffer memory address indicating a bank in which a cell received next to the top cell (hereinafter referred to as a second cell) is accumulated as data. The second chain structure is such that the buffer memory address indicates the bank of the cell received next to the second cell.
The control memory 14 continues to the buffer memory address of the bank in which the last cell indicated by the above is stored, and holds and stores the time-related information of the received cell.

The control queue 16 stores the buffer memory address of a bank not used for storing received cells as data in a queue format. Further, reference numeral 17 indicates a host control system, which indicates a logical channel for the VC of the cell or a logical channel for the time slot.

The memory control unit 3 includes a buffer memory 12,
It controls writing and reading of data in the first control memory 13, the second control memory 14, the third control memory 15, and the control queue 16.

The first clock transfer means 6 is an ATM
The cell arriving at the cell highway 5 is changed from the clock on the ATM side to the internal clock of this device. Further, the header logical channel converting means 7 converts the header of the cell whose clock has been changed by the first clock changing means 6 into the logical channel designated by the upper control system 17 and outputs it in synchronization with the payload data of the cell. To do.

Further, the output logical channel conversion means 9 performs conversion into a logical channel of a cell which is decomposed to output time division multiplexed data based on the clock of the time division multiplexed data highway and the frame pulse 8 which are inputted. . Second
The clock transfer means 10 converts the time division multiplexed data into the fixed bit rate data 1 of the time division multiplexed data highway.
When outputting as 1, the internal clock is changed to the clock of the time division multiplexed data highway.

The cell storage controller 1 receives the output of the header logical channel converter 7 as an input and writes the payload data of the cell into the buffer memory 12 in bank units for each cell reception, and the first control memory for each logical channel. 13,
A bank chain structure is formed on the second control memory 14 and the third control memory 15 to store cells.

The cell disassembly control unit 2 disassembles the payload of the top cell of the chain structure of the bank of the corresponding logical channel formed on the buffer memory 12 according to the output logical channel instruction from the output logical channel converting means 9. Second clock transfer means 1 as time division multiplexed data
Output to 0, and if there is no cell to disassemble, output idle data.

The sequence control unit 4 includes the cell storage control unit 1
And contention control of data writing and reading from the cell disassembly control unit 2 to the buffer memory 12, the first control memory 13, the second control memory 14, the third control memory 15, and the control queue 16.

Next, the operation of the apparatus of this embodiment will be described.

First, the operation of the cell accumulation control unit 1 will be described with reference to FIGS. FIG. 2 is a flowchart for explaining the flow of processing of the cell accumulation control unit 1, and FIG. 4 is a diagram showing the structure of the cell.

First, 1 to 4 octets of the cell shown in FIG. 4 are a header, and this portion is converted into a logical channel by the header logical channel converting means 7. Five octets are used for error checking. Six octets are called sequence numbers and are used for cell sequence control. 7-
53 octets are data called payload,
This portion is output to the time division multiplex highway as fixed bit rate data.

As shown in the flowchart of FIG. 2, when the logical channel and the payload data which are the outputs of the header channel logical conversion means 7 are input, the buffer memory address indicating the unused bank is read from the control queue 16. Next, the chain structure formed on the third control memory 15 is updated. In that case, if it is the first cell received in that logical channel, the buffer memory address is also written in the first control memory 13 indicating the top cell. Further, the buffer memory address is also written in the second control memory 14 indicating the last cell. This process is performed every time a cell arrives, but not when an idle cell arrives.

FIG. 6 shows an example of the chain structure of the addresses constructed in the first to third control memories 13 to 15 to further explain this operation.

In this example, the number of VCs to be processed is 4, VC1 is 4 cells in logical channel 2, VC2 is 1 cell in logical channel 1, VC3 is 2 cells in logical channel 0, and VC4 is 0 in logical channel 10. Have been accumulated.

Since VC1 has two logical channels, the buffer memory address of the top cell is found by referring to the address "02" of the first control memory 13, and the data "11" is the buffer memory address of the top cell. It turns out that Further, referring to the third control memory 15 using this "11" as an address, the data is "1".
2 ”, and it can be seen that the buffer memory address in which the next cell is stored is“ 12 ”. Similarly, if "12" is the address, the data is "13", and if "13" is the address, the data is "01", which is the data of the address "02" of the second control memory 14. It can be seen that “01” is the last cell because it is the same as

Similarly, since the VC2 is the logical channel 1, the data is "14" by referring to the address "01" of the first control memory 13, which means that the data of the second control memory 14 is Since it is "14", it can be seen that the top cell and the last cell are the same. Since VC3 is the logical channel 0, the data "04" is referenced by referring to the address "00" of the first control memory 13, and the data "08" of the address "04" of the third control memory 15 is "08". It can be seen that the second cell and the last cell are the same because the data of the second control memory 14 is "08".
Further, in the VC 4, both the first control memory 13 and the second control memory 14 have the data "-1", so it can be seen that the bank is not used.

Here, the operation when the VC4 cell arrives will be described with reference to FIG. 7 for explaining the chain structure.
When a cell arrives, an unused buffer memory address is read from the control queue 16. Here, the buffer memory address is "06". Payload data is written to this buffer memory address. Next, the second control memory 14 is updated,
Since the data is "-1", it can be seen that the cell is a top cell. Therefore, writing is also performed in the first control memory 13. That is, the first control memory 13, the second
The data of the address "10" of both the control memory 14 of the above becomes "06". Further, when a cell of VC4 arrives, if the buffer memory address of the unused bank is "07", the data of the second control memory 14 becomes "07",
The data of the address "06" of the third control memory 15 becomes "07". The first control memory 13 remains unchanged.

Next, the disassembly processing operation in the cell disassembly control unit 2 will be described with reference to FIGS. 3 and 5. FIG. 3 is a flow chart for explaining the flow of cell disassembly processing, and FIG. 5 shows the format of the time division multiplexing highway to be output.

As shown in FIG. 5, the time slot of the frame pulse is "0", and one frame is composed of the time slot of the (N-1) time slot. A logical channel is assigned to each time slot, and the VC corresponding thereto is decomposed and output.

The processing operation will be described with reference to FIG.

When the logical channel is converted from the time slot, the buffer memory address is read from the first control memory 13 indicated by the logical channel as an address. At this time, the additional delay information is determined, and if the additional delay is in progress, idle data is output on the time division multiplex highway, the additional delay is updated, and the first control memory 13 is updated.
Written in. When the additional delay is completed, the payload data is read into the payload read control unit 202 by the buffer memory address and the bank offset address indicating the data position in the bank, and the read data is sent to the multiplex data output selection unit 205. Via the time division multiplexed highway. Thereafter, the bank offset address is updated, and it is determined whether or not the payload data in the bank remains. If it remains, the buffer memory address is written to the first control memory 13. If not, the buffer memory address is written into the control queue 16 that stores an unused bank, the buffer memory address of the second cell is read from the third control memory 15, and the first cell is newly added as the top cell. Written to control memory.

Thus, by dynamically using the buffer memory to decompose the cells into fixed bit rate data of the time division multiplex highway, the required memory can be minimized and the fixed bit rate data assigned to the time division multiplex highway can be minimized. The time slot position of can also be arbitrary.

[0043]

As described above, according to the present invention, by dynamically using the buffer memory, the fixed bit rate data in which the usable bit rate for each channel is arbitrarily set while minimizing the usage amount of the buffer memory. Cell decomposition into

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a cell accumulation process.

FIG. 3 is a flowchart illustrating cell disassembly processing.

FIG. 4 is a diagram illustrating a cell format.

FIG. 5 is a diagram illustrating a format of a time division multiplex highway.

FIG. 6 is a diagram illustrating an example of a chain structure configured on a buffer memory.

FIG. 7 is a diagram illustrating an example of a chain structure configured on a buffer memory.

[Explanation of symbols]

1 Cell accumulation control unit 2 Cell disassembly control unit 3 Memory control unit 4 Sequence control unit 5 ATM cell highway 6 First clock transfer unit 7 Header logical channel conversion unit 8 Time division multiplexed data highway clock and frame pulse 9 Output logical channel Conversion means 10 Second clock transfer means 11 Time division multiplexed data Highway fixed bit rate data 12 Buffer memory 13 First control memory 14 Second control memory 15 Third control memory 16 Control queue 17 Upper control system 101 Buffer Memory address read control unit 102 Payload write control unit 103 Sequence number check means 104 Buffer memory address write control unit 201 Buffer memory address read control unit 202 Payload read control unit 203 Transmission completion bank write control unit 204 Idle data transmission control unit 205 Multiplex data output selection unit

Claims (4)

[Claims] 1. A cell demultiplexing / multiplexing apparatus for converting an ATM cell into time division multiplexed data, wherein a buffer memory composed of a plurality of banks in which a payload portion of a cell is stored and a payload portion of an arriving cell are unused. Specified by the host device based on the cell accumulation control unit that stores the address of the bank and the control memory that holds the address for each virtual channel, and the frame pulse and clock of the time division multiplexed highway. The address in the control memory is read for each virtual channel, the data of the data unit of the time division multiplex highway is read from the bank indicated by the address and is output as the time division multiplex data, and the cell is decomposed to set the bank as an unused bank. A cell disassembling multi-processing device characterized by comprising a control unit . 2. A means for accumulating addresses of unused banks in a queue format, wherein the cell accumulation controller reads the bank address from the head of the queue and stores the payload portion of the cell when the cell arrives. 2. The cell disassembling multiple processing apparatus according to claim 1, wherein the cell disassembling control unit includes means for writing the address of the bank whose output of the payload section has been completed to the end of the queue. 3. The control memory comprises a first control memory for storing an address of a bank storing a head cell for each virtual channel and a second control memory for storing an address of a bank storing a last cell of each virtual channel. 3. The cell disassembling / multiplexing apparatus according to claim 1 or 2, further comprising: a third control memory that stores chain information of a bank address for each virtual channel. 4. The cell according to any one of claims 1 to 3, wherein the cell disassembly control unit includes an additional delay unit that absorbs fluctuations in cell arrival intervals by adding a fixed amount of cell delay at the beginning of cell disassembly. Decomposition and multiprocessing equipment.