JPH0624882Y2 - Fail-safe circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a fail-safe circuit for a safety device and the like.

[Prior Art] Generally, various safety devices for preventing danger are added to a machine tool or the like. For example, in a press machine, a large number of light beams are provided by using light emitting elements and light receiving elements between the press drive area and the work area of the worker, and if there is an object that blocks the light flux during the press operation, it is a safety to stop the press operation. A device is provided.

A fail-safe system used for such a safety device is a system that controls so that safety does not deteriorate due to the failure even if any one element constituting the safety device fails.

3 (a) and 3 (b) are circuit diagrams showing an example of the fail safe as described above.

This circuit is generally used as a matching circuit, and the circuits shown in (a) and (b) of the same figure both input the same signal (for example, high signal or low signal) from inputs A and B. Is a circuit that outputs a low signal to the output X. For example, when this circuit is used in the above-mentioned press machine, the light receiving signal from the light receiving element is input to A, and the signal for detection confirmation is input to B, so that only when both signals match, a lower signal is output. A signal is output, and the press operation and the like are stopped by this low signal.

[Problems of conventional technology]

However, the conventional fail-safe circuit as described above is composed of a gate circuit. For example, when the gate circuit is destroyed, the inputs A and B do not match, but the output shows a signal indicating a match (low signal). ) May be output.

For example, in the example of FIG. 3 (a), when the NAND gate 1 is damaged for some reason and the output of the NAND gate 1 is fixed to the L level state, or the output of the NAND gate 4 is damaged for some reason, the NAND gate 1 When the output of 4 is fixed to the L level state, a low signal is output from X. Also, in the example of FIG. 6B, the EXOR gate is damaged,
When the output of the EXOR gate 5 becomes a low register, a low signal is output from X.

Therefore, since the output X indicates a match even though the inputs A and B do not match, a very dangerous state occurs when the output X is used as a signal for preventing danger and the like.

[Purpose of device]

In view of the above-mentioned conventional drawbacks, the present invention has an object to provide a fail-safe circuit capable of reliably ensuring safety even if a part of the circuit is destroyed by using a fail-safe element described later. To do.

[Key points of device]

In order to achieve the above-mentioned object, the present invention is directed to the first and second switching means, and the first AND operation oscillation which is oscillated when all the inputs are inputted with the outputs of the first and second switching means. Means, second logical product operation oscillating means for inverting and inputting the outputs of the first and second switching means, and an OR circuit for inputting outputs of the first and second logical product operation oscillating means And the first,
The present invention is characterized by including an adding means for adding the outputs of the second AND operation oscillating means, and a third AND operation oscillating means for receiving the output of the adding means and the output of the OR circuit.

[Example of device]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 (a) is a circuit diagram of the fail-safe monitor of this embodiment. In the figure, a fail-safe monitoring 6 of the present application, the fail-safe device _F 1 _{to F} 3, OR gate 7, the adder 8, an inverter 9a, is composed of a 9b. Further, the fail-safe monitor 6 has an input terminal C,
D and an output terminal Y are provided. The signal switching circuit 10 is connected to the input terminal C, and the signal switching circuit 11 is connected to the input terminal D. In addition, each signal switching circuit 1
One ends of 0 and 11 are grounded. Therefore, when the signal switching circuit 10 is turned on, the input terminal C becomes L level, and when the signal switching circuit 11 is turned on, the input terminal D becomes low level.

Further, the resistors R ₁ and R ₂ are connected to the input terminals C and D, respectively, and a predetermined voltage V is applied via the resistors R ₁ and R ₂ . Therefore, when the signal switching circuits 10 and 11 are turned off, the input terminals C and D both become H level.

The input terminal C is connected to the fail-safe element F ₁ and also connected to the fail-safe element F ₂ via the inverter 9a. Similarly, the input terminal D is connected to the fail-safe element F ₁ and also connected to the fail-safe element F ₂ via the inverter 9b.

As shown in FIG. 2 (a), the output states of the fail-safe elements F ₁ , F _{2 and the} like change depending on the states of the inputs a and b. The figure which shows the change of the output x with respect to this input a, b is the same figure (b). As shown in (b) of the figure, the fail-safe element outputs an oscillation signal when a high signal is input to both inputs a and b, and a low signal is input to both inputs a and b. When either one of b is a low signal and the other is an H signal, oscillation is stopped. Further, even if a high signal is input to the input a and a signal higher than the H level is input to the input b, the oscillation is stopped.

The oscillation signals of the fail-safe elements F ₁ and F ₂ are output to the OR gate 7 (FIG. 1 (a)) and the adder 8. The adder 8 has two input terminals, outputs a signal higher than the H level when an oscillation signal is input to both input terminals, and outputs an L signal when an oscillation signal is not input to both input terminals (when a stop signal is input).
When the oscillation signal is input to only one input terminal, it becomes H level. The output of the adder 8 and the output of the OR gate 7 which are in such an output state are both output to the fail-safe element F ₃ . Fail-safe element F ₃
Has the same configuration as described above, and this fail-safe F ₃ sends an output signal via the output terminal Y.

The circuit operation of the fail-safe monitor of this embodiment having the above configuration will be described below with reference to the truth diagram of FIG. 1 (b).

First, the signal switching means 10 and 11 are turned on, and the input C,
When a low signal is input to the D, the low signal is supplied to the input terminals of the fail-safe device F _1, the output of the fail-safe device F ₁ becomes the oscillation stop state as shown in FIG. 2 described above (b) . On the other hand, the two input terminals of the fail-safe element F _2, inverter 9a, since the high signal is supplied through an 9b, the oscillation state than the second view (b) as well.

Therefore, the OR gate 7 supplies the output of the fail-safe element F ₂ as a high signal to the fail-safe element F ₃ , and the adder 8 outputs the high signal as a fail-safe element because only one of both inputs is an oscillation signal. Supply to F ₃ .
Thus, the fail-safe element F ₃ is an oscillating state because of the input high signal to both inputs. Therefore, with this circuit, it can be confirmed from the oscillation signal output from Y that the same signal is input to both the C and D inputs.

On the other hand, as described above, when the low signals are input to both the inputs C and D, when any _{one of} the fail safe elements F ₁ and F ₂ or the inverters 9a and 9b is destroyed, the fail safe element F ₁ or the fail safe element is received. Since one of the elements F ₂ serves as a stop signal, the OR gate 7 detects this and outputs a low signal to the fail-safe element F ₃ , so that the output of Y always serves as a stop signal. In addition, the inverter 9
When both a and 9b are destroyed and both the fail-safe elements F ₁ and F ₂ are in the oscillating state, the high signal from the adder 8 causes H.
Fail-safe element F ₃ for outputting a level signal
Is also a stop signal.

Next, when the signal switching means 10 and 11 are both turned off and a high signal is input to the inputs C and D, the fail safe element F
_A high signal is supplied to both input terminals of No. _{1 and} the output of the fail-safe element F ₁ is in an oscillating state as shown in FIG. 2 (b). On the other hand, the two input terminals of the fail-safe element F _2, because the low signal is supplied via the inverter 9a, 9b, likewise oscillated from FIG. 2 (b) is in a stopped state.

Therefore, the OR gate 7 supplies the oscillation output of the fail-safe element F ₁ to the fail-safe element F ₃ , and the OR gate 7 and the adder 8 have only one of both inputs as an oscillation signal. Supply to the fail-safe element F ₃ . Thus, the fail-safe element F ₃ is an oscillating state because of the input high signal to both inputs. Therefore, by this circuit, it can be confirmed by the oscillation signal output from Y that the same signal is input to both the C and D inputs.

On the other hand, as described above, when low signals are input to both inputs C and D, when any _{one of} the fail-safe elements F ₁ and F ₂ or the inverters 9a and 9b is destroyed, or when both of the inverters 9a and 9b are destroyed. If you did the same as above,
The fail-safe element F ₃ (Y) output becomes a stop signal.

As described above, the inverter 9a, 9b, the fail-safe device F _1, F _2, if F ₃ is destroyed input terminal C, even though this application circuit for signal input from the D match Then, the stop signal is always output from Y. Therefore, when control is to be performed by this output, the control operation can be stopped and the fail-safe function can be surely executed.

Further, when one of the signal switching means 10 or 11 is turned on and a low signal is input to the input C or D, a low signal and a high signal are supplied to both input terminals of the fail safe element F ₁ and fail safe. The output of the element F ₁ is stopped. On the other hand, the fail-safe element F ₂ is also stopped similarly.

Therefore, the output of the OR gate 7 and the output of the adder 8 are stop signals, and the low signal is supplied to the fail-safe element F ₃ . Thus, the fail-safe element F ₃ is stalled because of the input is low signal to both inputs. Therefore,
Of course, this circuit can also determine that different signals are input to both the A and B inputs.

As described above, according to the fail-safe monitor of the present embodiment, whether or not the input signals match is confirmed by the oscillation signal, and when the internal circuit element is destroyed, the output signal is the stop signal ( Since it changes to a low signal), the output signal does not become a signal for operating the control system such as a high signal due to damage to the circuit element or the like.

[Effect of device]

As described in detail above, according to the present invention, when the internal circuit element or the like is damaged, the output signal always shifts to the fail-safe (operation for stopping driving of the control system) example.
If this output signal is used for a safety device or the like, safety is further improved.

[Brief description of drawings]

FIG. 1 (a) is a circuit diagram of the fail-safe monitor of this embodiment, FIG. 1 (b) is a truth table of the circuit diagram of FIG. 1 (a), and FIG. 2 (a) is a fail of this embodiment. A circuit diagram of essential parts of the safe monitor, FIG. 2 (b) is a truth table of the circuit diagram of FIG. 2 (a), and FIGS. 3 (a) and 3 (b) are conventional circuit diagrams of the fail safe monitor. . 6 ...... failsafe monitor, 7 ...... OR gate, 8 ...... adder, 9a, 9b ...... inverter, 10, 11 ...... switching _{means, F 1, F 2, F} 3 ...... failsafe device.

Claims (1)

[Scope of utility model registration request] Claim: What is claimed is: 1. First and second switching means, first AND AND operation oscillating means for oscillating when all the inputs are received by the outputs of the first and second switching means, and the first and second switching means. A second logical product operation oscillating means to which the output of the second switching means is inverted and input; an OR circuit to which the output of the first and second logical product operation oscillating means is input; A fail characterized by comprising: an addition means for adding the output of the second AND operation oscillation means, and a third AND operation oscillation means for receiving the output of the addition means and the output of the OR circuit. Safe circuit.