JPH0626348B2 - FSK demodulation circuit - Google Patents

Description

The present invention relates to an FSK demodulation circuit, and more particularly to an FSK demodulation circuit realized on a semiconductor integrated circuit.

[Conventional technology]

Conventionally, this type of FSK demodulation circuit includes various types of circuits such as a pulse counting type circuit. As an example, the sixth
Figure shows a block diagram of the pulse counting method. The monostable multivibrator 22 operates by the trigger pulse generated from the trigger pulse generator 21 at the rising or falling of the FSK modulated signal S _IN to generate a pulse having a constant width. This pulse is passed through the LPF 23 and the obtained voltage,
The output voltage of the DC voltage generating circuit 24 is compared with the comparison circuit 25 to obtain a demodulation output.

[Problems to be Solved by the Invention]

The conventional FSK demodulation circuit described above is used for analog LPF 23 even in circuits of pulse count type and other types.
In particular, when it is realized on a semiconductor integrated circuit, an RC active filter or the like is used as the LPF 23. Therefore, in the conventional structure, a large chip area is required to form a resistor, a capacitor and the like, and there is a drawback that the design is difficult due to the large variation in each element.

The object of the present invention is to eliminate such drawbacks, and by utilizing a switched capacitor circuit, an analog LPF is provided.
An object of the present invention is to provide an FSK demodulation circuit that does not require a circuit and can be configured with a small chip area on a semiconductor integrated circuit.

[Means for Solving the Problems]

The configuration of the FSK demodulation circuit of the present invention includes a first clock generation circuit which inputs a FSK demodulation signal and outputs a first clock having a frequency proportional to the frequency of the FSK modulation signal,
A second clock generating circuit for inputting a constant frequency signal and outputting a second clock having a frequency proportional to the frequency of the constant frequency signal; and a direct current voltage generating circuit for resistively dividing a power supply voltage to generate a constant voltage. A first switched capacitor equivalent resistance circuit sampled at one of the first and second clocks and having one end connected to a power supply terminal; and the other clock of the first and second clocks. Of the second switched capacitor equivalent resistance circuit, which is sampled at and has one end grounded and the other end commonly connected to the other end of the first switched capacitor equivalent resistance circuit, and the first and second switched capacitor equivalent resistance circuits. Input a comparison circuit that compares the output voltage from the common connection point with the output voltage of the DC voltage generation circuit and the output of this comparison circuit. A timing signal from an external by characterized by comprising a flip-flop circuit for outputting this input.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a part of an embodiment of the present invention by a specific circuit. In this embodiment, the first and second clock generation circuits 1 and 2, the first and second switched capacitor equivalent resistance circuits 3 and 4, the DC voltage generation circuit 5, and the equivalent resistance circuits 3 and 4 are included. It is composed of a comparison circuit 6 for comparing the output and the output of the DC voltage generation circuit 5, and a flip-flop 7. The first clock generation circuit 1 has an FS of frequency _IN
Enter the K modulation circuit S _IN, first clock phi ₁₁ two-phase non-overlapping frequency _'IN proportional to the frequency _IN, and outputs the phi _12, the second clock generator circuit 2 is constant frequency ₀ enter the frequency signal _{S 0,} the frequency ₀
It outputs the two-phase second clocks φ ₂₁ and φ ₂₂ having a frequency ₀ ′ proportional to the above and not overlapping with each other. The first switched capacitor equivalent resistance circuit (hereinafter referred to as the first SC equivalent resistance) 3 is sampled at the first or second clock, and the second switched capacitor equivalent resistance circuit 4 (hereinafter referred to as the second SC equivalent resistance). ) Is the first SC equivalent resistance 3
It is sampled by the clock that is not used in. The first and second SC equivalent resistance circuits 3 and 4 have a power source V
_A resistor divider circuit is formed between _DD and ground, and the intermediate terminal voltage is the compared voltage V _R ′ of the comparison circuit 6. This S
Generally, the equivalent resistance value of the C equivalent resistance changes in inverse proportion to the frequency of the input clock.

Therefore, one of the equivalent resistors forming the resistance division circuit is inversely proportional to the FSK modulation signal frequency _IN and the other has a constant value, so that the comparison voltage V _R ′ changes according to the FSK input signal _IN. .

By selecting the resistors R ₃ and R ₄ to set the output voltage of the DC voltage generating circuit 5 to an appropriate value and setting this as the comparison voltage V _R of the comparison circuit 6 and the comparison voltage V _R ′, the FSK modulation signal S A comparison circuit output corresponding to _IN is obtained. This output is given to the flip-flop 7 and the demodulation output S _OUT is outputted at the timing synchronized with the timing signal S _T given from the outside so that the demodulation signal can be detected at a good timing.

Next, in the circuit of this embodiment, FIG. 2 is a circuit diagram of an example of the clock generation circuits 1 and 2, and FIG. 3 is a waveform diagram of FIG. 2. In this embodiment, a binary FSK modulated signal It gives a demodulation output. The first SC equivalent resistance circuit 3 includes switches S _{1 to} S ₄ and a capacitor C ₁ , and is sampled by the first clocks φ ₁₁ and φ ₁₂ . At this time, the first S
The equivalent resistance value R ₁ of the C equivalent resistance circuit 3 is given by the following equation.

_{R 1 = 1 / (2 ·} IN '· C 1) = A / (IN · C 1) _{where, A = IN / (2 ·} IN' shows the constants).

In addition, the second SC equivalent resistance circuit 4 includes switches S ₅ to
It is composed of S ₈ and a capacitor C ₂ , and is sampled by the second clocks φ ₂₁ and φ ₂₂ , and the equivalent resistance value R ₂ is as follows.

R ₂ = 1 / ( _2.0 ′ · C ₂ ) = B / ( ₀ · C ₂ ), where B = ₀ / ( _2.0 ′) is a constant.

Here, assuming that C ₁ = C ₂ and A = B for simplification, the compared voltage V _R ′ is given by the following equation.

V _R '= _{[R 2 / (R 1 + R} 2) ] × V _DD = _[IN / ₍₀ + _IN)] × V _DD now the frequency of the FSK-modulated signal S _IN binary _IN1 and
When _{IN2 (IN1> IN2),} the voltage to be compared _{V R'1} and _{V R'2} corresponding to each becomes the following equation.

V _R'1 = _[IN1 / ₍₀ + _IN1)] × V _DD V _R'2 = _[IN2 / ₍₀ + _IN2)] × V _DD V for both are distinguished by a comparator of the comparator circuit 6 is _{R '1> V R>} V _{R'2 [IN1} / ₍₀ + _IN1)] × _{V DD>} V _{R> [IN2} / ₍₀ + _IN2)] × V _DD become resistor _R as 3, _{R 4} an appropriate Elect comparison voltage V _R
Just decide.

FIG. 4 is a time chart showing a concrete operation state in this embodiment. FSK modulation input signal frequency
_{When IN2} changes to _IN1 , the frequency of the first clock φ _{11 also} changes, which causes the compared voltage via the switched capacitor equivalent resistance circuits 3 and 4 to rise from V _R2 to V _R1 . This voltage rise is detected by the comparison circuit 6, and the detection output is synchronized with the timing signal S _T to output the output signal S _OUT.
And

As described above, in this embodiment, by using the switched capacitor equivalent resistance circuit whose characteristics are determined by the ratio of capacitors that can ensure accuracy on the semiconductor integrated circuit, the chip area is smaller than that of the conventional FSK demodulation circuit using the analog LPF. In addition, the FSK demodulation circuit can be designed without particularly considering the variation in the absolute value of the element.

FIG. 5 is a block diagram showing a partial circuit of the second embodiment of the present invention. First and second clock generation circuits 1,
2 is the same as in FIG. The first SC equivalent circuit 3 includes switches S _{1 to} S ₄ and a capacitor C ₁ and is sampled by the first clocks φ ₁₁ and φ ₁₂ , and the second SC equivalent resistance circuit 4 includes switches S _{5 to} S _8. , And a capacitor C ₂ for sampling with the second clocks φ ₂₁ and φ ₂₂ . In this embodiment, the comparison voltage V _R is also made by using a resistance division circuit using the SC equivalent resistance circuits 8 and 9, and the switches S _{9 to} S ₁₂ and the capacitor C ₃ are equivalent to the SC equivalent resistance circuit 8. The resistance value R ₃ , the switches S _{13 to} S ₁₆ , and the capacitor C _{4 form} the resistance value R ₄ of the SC equivalent resistance circuit 9, both of which are sampled by the second clocks φ ₂₁ and φ ₂₂ . The comparison circuit 6 uses a switched-capacitor type comparator circuit for sampling with the second clock, and is composed of switches S _{17 to} S ₁₉ , a capacitor C ₅ , a comparator 6 including a switch S ₁₉ and a 10-stage inverter 35. There is. In this example,
_{IN / IN '= 0/0} ', the following equation to determine the _{C 1 = C 2 = C 3} = C 4 as a comparison voltage _{V R} and the voltage to be compared _{V R} '.

V _R = 1/2 × V _DD V _R ′ = [ _IN / ( ₀ + _IN )] × V _DD Similar to the first embodiment, considering a binary FSK modulation signal, [ _IN1 / ( ₀ + _IN1 )] _{× V DD> 1/2 ×} V DD> _[IN2 / ₍₀ +
_IN2 )] × V _DD That is, the demodulation operation can be performed by selecting the frequency ₀ of the constant frequency signal S ₀ such that _IN1 > ₀ > _IN2 .

〔The invention's effect〕

As described above, the present invention makes it possible to realize an FSK demodulation circuit in a small area by using a switched capacitor equivalent resistance circuit whose characteristics are determined by the ratio of capacitors in a semiconductor integrated circuit in which the ratio accuracy of elements can be secured. There is an effect that the same circuit can be designed without particularly considering the variation of the absolute value of.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, a circuit diagram, FIG.
FIG. 3 is a circuit diagram and a waveform diagram of an example of the clock generation circuit of FIG. 1, FIG. 4 is a time chart showing the operation of this embodiment, and FIG. 5 is a circuit diagram of the second embodiment of the present invention. FIG. 6 is a block diagram of an example of a conventional FSK demodulation circuit. 1 ... 1st clock generation circuit, 2 ... 2nd clock generation circuit, 3 ... 1st switched capacitor equivalent resistance circuit, 4 ... 2nd switched capacitor equivalent resistance circuit, 5, 24 ... DC Voltage generation circuit, 6, 25 ... Comparison circuit, 7 ... Flip-flop, 10 ... Signal input terminal, 11 ... Clock input terminal, 13 ... Signal output terminal, 21 ... Trica pulse generator, 22 ... Monostable multivibrator, 23 ... LPF.

Claims (1)

[Claims] 1. A first clock generation circuit for inputting an FSK modulation signal and outputting a first clock having a frequency proportional to the frequency of the FSK modulation signal; and a constant frequency signal for inputting the constant frequency signal. A second clock generating circuit for outputting a second clock having a frequency proportional to the frequency; a direct current voltage generating circuit for resistively dividing the power supply voltage to generate a constant voltage; and a first clock of the first and second clocks. A first switched capacitor equivalent resistance circuit sampled by one clock and connected at one end to a power supply terminal, and one clock sampled by the other clock of the first and second clocks, one end grounded and the other end Second connected in common with the other end of the switched capacitor equivalent resistance circuit of 1.
Of the switched capacitor equivalent resistance circuit, a comparison circuit for comparing the output voltage from the common connection point of the first and second switched capacitor equivalent resistance circuits with the output voltage of the DC voltage generation circuit, and the output of the comparison circuit. And a flip-flop circuit that outputs this input according to a timing signal from the outside.
Demodulation circuit.