JPH0628832Y2 - Reset signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a reset signal generator for generating a reset signal for resetting a lock in a circuit immediately after power is turned on.

[Prior Art] FIG. 2 is a circuit diagram showing the configuration of a conventional reset signal generating circuit of this kind. In the figure, 1 is a power supply terminal, 2 is a Schmitt trigger type buffer, R is a resistor, and C is a capacitor. .

FIG. 3 is a waveform diagram showing the voltage waveform of each part of the circuit of FIG. 2, in which the horizontal axis represents time t and the vertical axis represents voltage.
(A) and (c) show the power supply voltage, and (b) and (d) show the voltage at point E. If the power is turned on at t0, the power supply voltage normally rises as shown in FIG. 3 (a),
At the point t1, all the circuits operated by this power supply are in a state of operating normally. The voltage at the point E rises as shown in FIG. 7B due to the time constant of RC, and when reaching the point t2, the voltage becomes sufficient to operate the buffer 2 and the reset signal 3 is generated. That is, in the relationship shown in FIGS. 3 (a) and 3 (b), the reset signal is generated after the logic reaches a state where the logic operates normally.

However, some power supplies have a rising characteristic as shown in FIG. 3 (c). In this case, the voltage at the point E rises almost like the power supply voltage, as shown in FIG. 3 (d). In such a case, after the reset signal is output at the point t2, the circuit operates normally only at the time t3, so that the reset signal becomes invalid.

[Problems to be Solved by the Invention] As described above, in the conventional circuit, the reset signal may become ineffective when the rise of the power supply is delayed as compared with the RC time constant (FIG. 2). There is a problem that a large resistance and a large capacitor must be used to increase RC, which is disadvantageous.

An object of the present invention is to solve the above-mentioned problems in the prior art and to provide a reset signal generation circuit capable of generating an effective reset signal regardless of the rise of the power supply voltage.

[Means for Solving the Problems] In this invention, the resistance R of the time constant RC of the conventional circuit is FE.
The internal resistance of the on-state of T is set, and this FET is controlled so that it is turned on only after the power supply voltage reaches a predetermined voltage value.

[Operation] Since the charging of the capacitor is started after the power supply voltage reaches a predetermined voltage value, it is not necessary to increase the value of the time constant RC so much regardless of the rising waveform of the power supply voltage.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a connection diagram showing an embodiment of the present invention, in which the same reference numerals as those in FIG. 2 designate the same or corresponding parts, Q1 and Q4 are p-channel FETs, and Q2 and Q3 are n-channel Fs, respectively.
ET, C1, C2 are capacitors, I1, I2, respectively.
I3 and I4 are inverters, A, B and D are connection points, and A is tentatively referred to as a voltage division output point.

Comparing FIG. 1 with FIG. 2, Q4 is R, C2 is C,
D corresponds to E, and I1 to I4 correspond to buffer 2.

Connect Q1 and Q2 in series and connect between power supply terminal 1 and ground,
Configure a voltage divider circuit. When the power is turned on, the gate of Q1 is connected to the ground, and the gate of Q2 is C1.
Since a voltage is applied via the above, both Q1 and Q2 are turned on, and a voltage proportional to the power supply voltage appears at point A. As the power supply voltage rises, the voltage at point A rises, and when it reaches a predetermined voltage, Q3 turns on and C1 is charged, and the voltage at point B drops to ground. B
When the voltage at the point drops, Q2 is cut off, the voltage at the point A becomes close to the power supply voltage, the ON state of Q3 is maintained, and Q4
Becomes Å and charging of C2 starts.

The reset signal continues to be output until C2 is charged and the voltage at point D reaches a predetermined voltage value.

As described above, since the charging of the capacitor C2 is started only after the power supply voltage reaches the predetermined voltage value, an effective reset signal can be generated regardless of the rising waveform of the power supply voltage.

[Advantage of the Invention] As described above, according to the present invention, an effective reset signal can be generated regardless of the rise of the power supply voltage without requiring a too large time constant.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional circuit of this kind, FIG. 3 is a waveform diagram showing voltage waveforms of respective parts in FIG. Power supply terminal, 3 ... Reset signal, Q1, Q4 ...
P-channel FETs, Q2, Q3 ... n each
Channel FET, C2 ... Capacitor, I1-I4 ...
Inverter. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] 1. A reset signal generating circuit for generating a reset signal for resetting a logic circuit operated by the power source immediately after the power source is turned on, comprising a p-channel FET (Q1) and an n-channel FET (Q2).
Is connected in series between the power source and the ground, the voltage dividing circuit using the connection point A of Q1 and Q2 as the voltage dividing output point, the gate of Q1 is grounded, and the gate of Q2 is capacitor C1.
Means for connecting to the power supply via an n-channel FE connected between the gate of Q2 and ground
A means for connecting the gate of T (Q3) to the voltage dividing output point A, and a gate of a p-channel FET (Q4) connected between the other terminal of the capacitor C2 whose one terminal is grounded and the power supply. A reset signal generator comprising means for mutually connecting the gate of Q2 and generating a reset signal from the voltage of the other terminal of C2.