JPH06295167A - Display controller - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a display control device for simultaneously performing different displays for a plurality of display devices, one memory is shared by the plurality of display devices, and different displays are provided for the plurality of display devices. I do. [Structure] One frame memory 13 in an information processing apparatus main body 10 is written with display data and a write clock signal from a memory access control circuit 12 when a write access is made from a CPU 11. . The access check circuit 14 checks the write access to the frame memory 13. When the write access is detected, the mask operation of the output mask circuit 15 is invalidated, and a predetermined display among the plurality of display devices 20 _{1 to} 20 _n is displayed. Only the contents of the display memory 23 in the device are updated. When there is no write access, the output mask circuit 15 validates the mask operation and cuts off the display data transmission.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
In particular, the present invention relates to a display control device that allows different displays to be simultaneously displayed on a plurality of display devices.

[0002]

2. Description of the Related Art In an information processing apparatus such as a personal computer or a workstation, when a plurality of display devices are provided with different displays to provide multi-screen display, information is usually associated with the display devices in a one-to-one correspondence. It is necessary to provide the processing device body. However, such a configuration is uneconomical because the same number of information processing device bodies as the display devices are required.

Therefore, there has been conventionally known a display control device in which a plurality of display devices are simultaneously controlled by one display control device to enable multi-screen display and the like (for example, Japanese Laid-Open Patent Publication No. Hei. No. 90591). According to this conventional display control device, by providing a plurality of bitmap memories corresponding to each of the plurality of color liquid crystal display devices, the plurality of color liquid crystal display devices are simultaneously controlled by one device, Different displays can be displayed at the same time.

[0004]

However, the above-mentioned conventional display control device requires the same number of bitmap memories, that is, frame memories, in one main body as the color liquid crystal display device to be controlled (hence, it is necessary). , N frame memories are required for simultaneous control of n color liquid crystal display devices.), The more color liquid crystal display devices to control, the greater the power consumption and display device There is a problem of increasing the size.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a display control device which solves the above conventional problems by sharing one frame memory among a plurality of display devices. To aim.

[0006]

In order to achieve the above object, the present invention provides a single memory for storing display data to be written in each display memory of a plurality of display devices each having a display memory. A display data writing unit, the display data writing unit monitors write access of display data to the memory from a higher-level device, and when a write access occurs, the display data of each of the display memories in the plurality of display devices is monitored. Of these, only the display memory in a specific one display device to which the display data is written is writable, and the display data read out after being written in the memory is written, and in each of the other display devices. The display memory is not writable.

Further, according to the present invention, when there is no write access to the display data to the memory, transmission of the read display data from the memory to the plurality of display devices is prohibited, and the display data to the memory is When a write access occurs, it has an output circuit for transmitting the display data read out after being written in the memory to each display memory in the plurality of display devices.

Further, in the present invention, the output circuit, when a write access to display data to the memory occurs, performs a first sync operation of a vertical synchronizing signal simultaneously supplied to the plurality of display devices before the write access occurs. 2 of the vertical synchronizing signal after the end of the write access from the edge input time
The display data read from the memory is transmitted to the display memories in the plurality of display devices until a time immediately before the time of inputting the second leading edge.

Furthermore, in the present invention, the display data and the display timing signal from any one display device are selected by the first selection circuit, and the display data from the first selection circuit and the display from the host device are displayed. Of the data, the display data selected by the second selection circuit according to the instruction of the host device is
Switching output based on the display data timing signal from the host device or the first selection circuit and writing to the single memory.

[0010]

According to the invention described in claim 1, since the display data read from the single memory is written in the built-in display memory in the plurality of display devices, the display data is read from the single memory. The display data are simultaneously displayed, and the display data can be rewritten by writing the display data only to the display memory of one display device selected by the display data writing means. A single memory can be shared as a display data storage memory, and different displays can be simultaneously performed by a plurality of display devices.

According to the second aspect of the invention, when the write access to the memory is not generated by the output circuit, the display data is not transmitted to the display device. Therefore, the memory and the display device are not transmitted during the non-transmission period. Power consumption between can be eliminated.

Further, according to the invention of claim 3, the display data rewritten in the memory is synchronized with the vertical synchronizing signal of the display device even if the write access to the memory of the host device is performed randomly. Then, the data can be transmitted from the memory to the display memory of the display device frame by frame.

Further, according to the present invention, the display data from any one display device can be switched and output according to the instruction of the host device and written in the single memory. Any display data being displayed can be processed with.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of a first embodiment of the present invention. In the figure, reference numeral 10 denotes a main body of an information processing apparatus such as a personal computer or a workstation, which includes a central processing unit (CPU) 11, a memory access display control circuit 12, a frame memory 13, and an access check circuit 14.
And an output mask circuit 15 and the like.

The CPU 11 includes a memory access display control circuit 12, a frame memory 13, and an access check circuit 1.
An upper device for controlling the memory 4 and the like supplies addresses, data and read / write control signals for accessing the frame memory 13 to the memory access display control circuit 12 and the access check circuit 14 via the bus 16.

The memory access display control circuit 12 is a circuit for generating a read / write access control and display timing signal for the frame memory 13 and a read address for the frame memory 13. The memory access display control circuit 12 performs read / write access to the frame memory 13 via the bus 17. Address and display data are supplied, and a write clock signal is supplied to the frame memory 13 via the transmission line 18.

The frame memory 13 reads out the stored display data and outputs a plurality of n display devices 20 ₁ to 20 2.
The display devices 20 _{1 to} 20 are memories that respectively output to 0 _n.
Commonly used for _n . The output mask circuit 15 is based on the mask signal c ₀ from the access check circuit 14,
The display data a from the frame memory 13 to the display devices 20 _{1 to} 20 _n is passed or blocked to form the display data b.

The access check circuit 14 includes the CPU 11
From the memory access display control circuit 12, and a display timing signal d such as a horizontal synchronizing signal, a vertical synchronizing signal, a shift clock, etc. are input, and the write mask signal c _{1 is} supplied from these signals.
To c _n was supplied to generate and display device 20 ₁ to 20 _n respectively, and controls the writing operation of the display memory 23 are respectively incorporated in the display device 20 ₁ to 20 _n. The access check circuit 14 constitutes display data write control means together with a write mask circuit 22 described later.

FIG. 2 shows a block diagram of an embodiment of the access check circuit 14 described above. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. As shown in FIG. 2, the access check circuit 14 is an AND circuit in which output terminals are connected to the write access detection circuit 31, the write control register 32, and the display devices 20 _{1 to} 20 _n in a one-to-one correspondence. It is composed of a 33 ₁ ~ 33 _n.

The write access detection circuit 31 monitors the presence or absence of write access to the frame memory 13, is a valid display data mask signal c ₀ and a write mask signal c ₁ to c _n and each time write access is not, write together when the access is present and disables the display data mask signal c _0, it outputs a high level signal, respectively to the aND circuits 33 ₁ ~ 33 _n. The write access detection circuit 31 constitutes the output circuit together with the output mask circuit 15.

The write setting register 32 is used by the CPU 11
Based on the setting, out of the AND circuit 33 ₁ ~ 33 _n, a value which supplies a signal of a high level only one AND circuit corresponding to the display device for trying to write is set. As a result, only one AND circuit corresponding to the display device to which data is written is set to the gate “open” state.
A high level signal from the write access detection circuit 31 is taken out through the circuit and is output as a write mask signal indicating invalidity.

In FIG. 1, the display devices 20 _{1 to} 20 _n are
The display control circuit 21, the write mask circuit 22, the display memory 23, and the display module 24 have the same configuration.
Consists of. The display control circuit 21 uses the display timing signal d.
A read / write address to the display memory 23 is generated based on the above, and input to the display memory 23 via the bus 25.

The write mask circuit 22 sends the write signal e from the display control circuit 21 to the access check circuit 1.
The signal f passed or blocked based on the write mask signal from 4 is supplied to the display memory 23. Display memory 23
Is a memory for temporarily storing display data, and the read data is input to the display module 24 via the bus 26. The display module 24 moves from the display memory 23 to the bus 2
The display data input via the display control circuit 21
It is displayed based on the display timing signal g from.

Next, the display device 20 ₁ will be taken as an example of the operation when the frame memory 13 is not rewritten as in the case of still image display and when the frame memory 13 is rewritten by moving the application software or the like. Explained.

First, the operation when rewriting of the frame memory 13 does not occur will be described. The memory access display control circuit 12 generates a read address and supplies it to the frame memory 13, and also generates a display timing signal d. As a result, the display data a according to the read address input via the bus 17 is output from the frame memory 13 and supplied to the output mask circuit 15.

On the other hand, when there is no write access to the frame memory 13, the access check circuit 14 (write access detection circuit 31 shown in FIG. 2) makes the display data mask signal c ₀ valid, so that the output mask circuit 15 becomes ,
The input display data a is masked and the display data a is not output to the display device 20 ₁ .

In the display device 20 ₁ , the display control circuit 21 outputs the read address to the display memory 23 via the bus 25 and the display timing signal g to the display module 24. Since the write mask signal c ₁ is validated, the write signal e is not supplied from the write mask circuit 22 to the display memory 23, and the write operation of the display memory 23 is prohibited.

Therefore, the display data read from the display memory 23 based on the read address is displayed on the display module 24 according to the display timing signal g. At this time, the display data b is stored in the display memory 23.
Since the writing is prohibited, the content of the memory does not change, and the display of the same image is repeated on the display module 24, so that a still image is displayed.

As described above, according to the present embodiment, when the rewriting of the frame memory 13 does not occur, the output of the display data a is masked by the output mask circuit 15 and is not input to the display device 20 _1. And display device 20 ₁
It is possible to reduce unnecessary power consumption that is consumed in data transmission between the two.

Next, the operation when the frame memory 13 is rewritten will be described. In this case, CPU1
1 performs write access to the frame memory 13 through the memory access display control circuit 12, and the stored contents of the frame memory 13 are rewritten. The access check circuit 14 (write access detection circuit 31 in FIG. 2) detects this write access and detects the display data mask signal c.
₀ is invalid, an AND circuit 33 ₁ ~ 33 _n of FIG. 2, and outputs a write mask signal c ₁ to c _n of the logical product of the set value of the write control register 32 and the display data mask signal c _0.

At this time, the write access detection circuit 31
Monitors the vertical synchronizing signal in the display timing signal d, instead of disabling the display data mask signal c ₀ at the same time detecting the write access, as schematically shown in FIG. 3 (B), the time t ₁ assuming that a write access to ~t _3, after the time t ₁ in which there is write access, the detection time t ₂ of the leading edge of the vertical synchronizing signal shown in the first figure (a), FIG. (C) The display data mask signal c ₀ is invalidated as schematically shown in FIG.

Further, the display data mask signal c ₀ is not made valid at the same time as the end of the write access, but after the write access end time t ₃ , the second leading edge detection of the vertical synchronizing signal shown in FIG. 3A is performed. At time t ₄ , the display data mask signal c ₀ is validated as schematically shown in FIG.

Therefore, according to the present embodiment, after the write access is started, the display data mask signal c ₀ is invalidated from the first time when the display on the display module 24 reaches the head of the screen, and the write access is further terminated. After the vertical synchronizing signal is monitored until the display data for one frame is output from the frame memory 13, the display data mask signal c ₀ is validated. This is done by the CPU 11
Since the write access is randomly performed to the frame memory 13, even if the display data at the address immediately after being read from the frame memory 13 is rewritten, the display data for one frame can be read from the frame memory 13 further. This is to reflect all the rewritten display data on the display of the display device.

The display data a read from the frame memory 13 of FIG. 1 in accordance with the read address is output mask circuit 1 because the display data mask signal c ₀ is invalid.
It is output as the display data b to the display memory 23 in the display device 20 ₁ without being masked by 4. Here, the writing of the display data b to the display memory 23 in the display device 20 ₁ is controlled by the set value of the write control register 32 shown in FIG.

That is, when the setting of the write control register 32 is writable, the signal supplied from the write control register 32 of FIG. 2 to the AND circuit 33 ₁ is high level and the write mask signal c ₁ is invalid. Therefore, the write mask circuit 22 is changed to the display control circuit 21.
Writing to the display memory 23 is performed by passing the write signal e from the. Further, when the setting of the write control register 32 is write-disabled, the write mask signal c ₁ is valid, so that the write mask circuit 22 prohibits the write signal e from the display control circuit 21 to pass. , Display memory 23
The display data b is not written to.

As described above, according to this embodiment, the output mask of the display data is released only when the content of the frame memory 13 in the main body is updated, and the write control register 32 is released.
N display devices 20 ₁ to
By independently controlling whether or not the display data of the display memory 23 in 20 _n is written, and updating only the stored contents of the display memory in the specific display device, the single frame memory 13 can also be used in the display device. Different displays can be displayed.

Next, a second embodiment of the present invention will be described. FIG. 4 shows a block diagram of a second embodiment of the display control device of the present invention. In the figure, the same components as those in FIG.

In the first embodiment shown in FIGS. 1 and 2, when the read-modify-write (processing the read data and writing back to the same address) is performed on the display data currently being displayed, the data currently stored in the main body is read. It can be executed only for the display of the display device in which the display data exists in the frame memory 13.

Therefore, in the second embodiment shown in FIG. 4, the display data timing selector 41 and the data selector 42 are connected to the information processing apparatus main body 10 so that the read-modify-write can be performed on the display data being displayed on an arbitrary display device.
The display data is displayed inside an arbitrary display device and can be read out to the frame memory 13 in the main body.

The display data timing selector 41, the first selection circuit, a display device 20 ₁ to 20 _n of the display timing signal g ₁ to g _n from each display display read out from the memory 23 the data h ₁ ~ h _n and are input, and one designated display data among them is selected at the timing of the display timing signal. This selected display data j
Is input to the data selector 42, and the selected display timing signal k is input to the memory access display control circuit 12.

The data selector 42 is a second selection circuit, which selects one of the write data p from the memory access display control circuit 12 and the display data j.
Selection is made based on the selector switching signal q from the memory access display control circuit 12 and output to the frame memory 13 as write data r.

FIG. 5 shows the display data timing selector 41.
3 shows a block diagram of an embodiment of FIG. In the figure, the display data timing selector 41 is a display data selector 5
1, a display timing selector 52, and a read setting register 53. The display data selector 51 selects _one display data from the display data h _{1 to} h _n read from the built-in display memory 23 of each of the display devices 20 _{1 to} 20 _n according to the set value of the read setting register 53. And output as display data j.

The display data timing selector 52 from among the display timing signals g ₁ to g _n inputted from the respective display device 20 ₁ to 20 _n, the read setting register 5
According to the setting of 3, one display timing signal is selected and output as the display timing signal k.

Next, the operation of the second embodiment shown in FIGS. 4 and 5 will be described with reference to the timing chart of FIG. 6, taking as an example the case of reading the display data being displayed on the display device 20 ₁ . First, the read setting register 53 is set to select the display data h ₁ and the display timing signal g ₁ of the display device 20 ₁ .

[0046] Thus, among the display data h ₁ to h _n to be inputted to the display data selector 51 (h ₁ in FIG. 6 (B), shows a h _n in FIG. (D)), the read setting register 5
Display data j shown in FIG. 6 (F) selected by No. 3
(Here, h ₁ ) is input to the data selector 16 in FIG. Further, the display data timing selector 52 is
Display device 20 ₁ to 20 _n of the display timing signals g ₁ to g _n inputted from the respective (g _1, FIG. FIG. 6 (A) (C)
Among illustrating a g _n) in accordance with setting of the read setting register 53, a display timing signal g shown in Fig. 6 (A)
₁ is selected and the display timing signal k shown in FIG.
Is output to the memory access display control circuit 12 of FIG.

The memory access display control circuit 12 normally outputs a selector switching signal q so that the data selector 42 selects the write data p from the memory access display control circuit 12. However, when the display data being displayed on the display device is written to the frame memory 13, the memory access display control circuit 12 switches the selector switching signal q as shown in FIG. 6G in accordance with the display timing signal k. The write address and the write clock signal corresponding to the display data j are output to the frame memory 13 via the bus 17 and the signal line 18.

By such a method, the display data r (here, h ₁ ) being displayed on an arbitrary display device (here, 20 ₁ ) is taken out from the data selector 42 as shown in FIG. The frame memory 13 is input to the memory 13 and based on the write clock signal shown in FIG.
Written in. After that, by switching the selector switching signal q, processing for display data of an arbitrary display device (for example, replacing a specific color with another color)
Is possible.

As described above, according to this embodiment, by providing the display data timing selector 41 and the data selector 42 in the main body 10, the display data being displayed on any display device can be displayed in the frame memory 13 in the main body 10. Can be read out and the display data can be processed.

[0050]

As described above, according to the present invention, a plurality of display devices share a single memory as a display data storage memory, and different display devices can simultaneously perform different displays. Therefore, the device can be made smaller than the conventional one.

Further, according to the present invention, when the write access to the memory does not occur, the display data is not transmitted to the display device, thereby eliminating the power consumption between the single memory and the display device. Therefore, when the number of display devices to be connected is the same, the power consumption can be reduced as compared with the conventional case, in combination with the fact that only one memory is required.

Furthermore, since the display data rewritten in the memory in the main body can be transmitted from the memory to the display memory of the display device in frame units in synchronization with the vertical synchronizing signal of the display device, write access is possible. Since it is performed at random in the memory, even if the display data of the address immediately after being read from the memory is rewritten, all the rewritten display data can be reflected in the display of the display device.

Furthermore, according to the present invention, since the display data being displayed on an arbitrary display device has a circuit structure capable of being read out to the memory in the main body, even if the main body has only one memory, the display data can be displayed. There is an effect that it is possible to process arbitrary display data inside.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of an access check circuit.

FIG. 3 is a timing chart for explaining the operation of the access check circuit.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of an embodiment of a display data timing selector.

FIG. 6 is a timing chart for explaining the operation of the second embodiment of the present invention.

[Explanation of symbols]

10 ... Information processing apparatus main body, 11 ... Central processing unit (CP
U), 12 ... Memory access display control circuit, 13 ... Frame memory, 14 ... Access check circuit, 15 ... Output mask circuit, 20 _{1 to} 20 _n ... Display device, 21 ... Display control circuit, 22 ... Write mask circuit, 23 ... display memory,
24 ... Display module, 31 ... Write access circuit, 3
2 ... Write control register, 41 ... Display data timing selector, 42 ... Data selector, 51 ... Display data selector, 52 ... Display timing selector, 53 ... Read setting register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Masahiro 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Imaging Information Systems Co., Ltd. Inside Hitachi Asahi Electronics (72) Inventor Koichi Isaji 810 Shimoimaizumi, Ebina City, Kanagawa Stock Company Hitachi Office Systems Division

Claims (4)

[Claims] 1. A single memory for storing display data to be written in each display memory of a plurality of display devices each having a built-in display memory, and monitoring the write access of the display data to the memory from a host device. Of the display memories in the plurality of display devices when the write access occurs, only the display memory in the specific one display device to which the display data is written is writable, and after being written in the memory, A display control device, comprising: display data write control means for writing the read display data and prohibiting writing to each display memory in another display device. 2. When display data write access to the memory is not made, transmission of read display data from the memory to the plurality of display devices is prohibited, and when display data write access to the memory occurs. 2. The display control device according to claim 1, further comprising an output circuit for transmitting the display data read out after being written in the memory to each display memory in the plurality of display devices. 3. The output circuit, when a write access of display data to the memory occurs, from the first leading edge input time point after the write access of the vertical synchronizing signals simultaneously supplied to the plurality of display devices. Transmitting the display data read from the memory to the display memory in the plurality of display devices for a period immediately before the second leading edge input time of the vertical synchronizing signal after the end of the write access. The display control device according to claim 2, wherein 4. The display data and the display data timing signal of each display memory are input from the plurality of display devices, and the display data and the display timing signal from any one display device are output according to the set value of the setting register. The first selection circuit to be selected, the display data selected from the display data from the first selection circuit and the display data from the host device according to the instruction of the host device, the display data selected from the host device or the first device. A second selection circuit for switching and outputting based on the display data timing signal from the selection circuit, wherein the display data selected by the second selection circuit is written in the single memory. Claims 1 to 3
The display control device according to claim 1.