JPH0629518A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0629518A
JPH0629518A JP4182591A JP18259192A JPH0629518A JP H0629518 A JPH0629518 A JP H0629518A JP 4182591 A JP4182591 A JP 4182591A JP 18259192 A JP18259192 A JP 18259192A JP H0629518 A JPH0629518 A JP H0629518A
Authority
JP
Japan
Prior art keywords
region
semiconductor
semiconductor device
electrode
cathode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4182591A
Other languages
Japanese (ja)
Inventor
Takuji Keno
拓治 毛野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP4182591A priority Critical patent/JPH0629518A/en
Publication of JPH0629518A publication Critical patent/JPH0629518A/en
Pending legal-status Critical Current

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  • Thyristors (AREA)

Abstract

PURPOSE:To provide a semiconductor device wherein it can avoid that a chip area is increased, it is suitable for being applied to a power electronics circuit and it is of a good-performance integration type. CONSTITUTION:A semiconductor device is constituted in the following manner: a cathode region and a gate region are formed on the surface part on one side of a semiconductor substrate 2; a cathode electrode 21 and a gate electrode 22 are formed on the semiconductor substrate; the gate electrode and the cathode electrode are composed respectively of a trunk in which a branch part and a branch part are connected; and a static-induction semiconductor element 3 wherein the electrodes come into contact by the branch parts and the electrodes are led out by the trunk part is provided. A first-conductivity-type junction isolation region 16 insulated and isolated from the circumference by interposing a second-conductivity-type semiconductor layer is formed at the lower part of the trunk of at least one electrode out of both electrodes on the semiconductor substrate; a semiconductor element 4 different from the static-induction semiconductor element is formed in the junction isolation region.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、パワーエレクトロニ
クス回路に応用するのに適している集積タイプの半導体
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated type semiconductor device suitable for application to power electronic circuits.

【0002】[0002]

【従来の技術】静電誘導サイリスタはパワーデバイスと
しての適性をもっている。この静電誘導サイリスタが設
けられている半導体基板にサイリスタと別に半導体素子
(例えば、静電誘導サイリスタを制御するためのトラン
ジスタ等の素子)も併設されているならば、非常に利用
し易くて実用性は高まることになる。
2. Description of the Related Art Static induction thyristors are suitable as power devices. If a semiconductor element (for example, an element such as a transistor for controlling the electrostatic induction thyristor) is also provided separately from the thyristor on the semiconductor substrate on which the electrostatic induction thyristor is provided, it is very easy to use and practical. Sex will be enhanced.

【0003】すなわち、図3に示す半導体装置31のよ
うに、一つの半導体基板32に静電誘導サイリスタ33
と共にトランジスタ34を設けるのである。この半導体
装置31の静電誘導サイリスタ33は、半導体基板32
の表側の表面部分に、不純物濃度の高いn+ 型(第1導
電型)のカソード領域41と不純物濃度の高いp+ 型
(第2導電型)のゲート領域42とが、カソード領域4
1がゲート領域42に挟まれる形で形成されていて、半
導体基板32の上に、前記カソード領域41にコンタク
トするカソード電極51とゲート領域42にコンタクト
するゲート電極52が形成されており、一方、半導体基
板32の裏側の表面部分は、p+ 型のアノード領域43
となっており、その表面にアノード電極(図示省略)が
くる。そして、半導体基板32におけるカソード領域4
1とアノード領域43の間がベース領域たるn- 型の高
比抵抗領域44になっている。
That is, like the semiconductor device 31 shown in FIG. 3, the electrostatic induction thyristor 33 is formed on one semiconductor substrate 32.
At the same time, the transistor 34 is provided. The electrostatic induction thyristor 33 of this semiconductor device 31 is a semiconductor substrate 32.
In the surface portion on the front side of the cathode region 4, an n + type (first conductivity type) cathode region 41 having a high impurity concentration and ap + type (second conductivity type) gate region 42 having a high impurity concentration are formed.
1 is formed so as to be sandwiched between the gate regions 42, and a cathode electrode 51 that contacts the cathode region 41 and a gate electrode 52 that contacts the gate region 42 are formed on the semiconductor substrate 32. The surface portion on the back side of the semiconductor substrate 32 has a p + -type anode region 43.
And the anode electrode (not shown) comes to the surface. Then, the cathode region 4 in the semiconductor substrate 32
A region between 1 and the anode region 43 is an n − type high specific resistance region 44 which is a base region.

【0004】一方、半導体装置31における別の半導体
素子たるトランジスタ34は、n-型の接合分離領域3
6に設けられている。図4にみるように、半導体装置3
1を上からみると、静電誘導サイリスタ33の形成域A
の隣に、トランジスタ34の形成域B、つまり、接合分
離領域36が並んで設けられているのである。接合分離
領域36はp+ 型の半導体層35の介在により周りと絶
縁分離されていて、この接合分離領域36の中に、p型
のベース領域45、n+ 型のエミッタ領域46およびコ
レクタ領域47が形成され、各領域それぞれにコンタク
トする電極55,56,57が形成されている。
On the other hand, the transistor 34 which is another semiconductor element in the semiconductor device 31 has an n -- type junction isolation region 3
6 is provided. As shown in FIG. 4, the semiconductor device 3
1 is viewed from above, the formation area A of the electrostatic induction thyristor 33
Next to that, the formation region B of the transistor 34, that is, the junction isolation region 36 is provided side by side. The junction isolation region 36 is insulated and isolated from the surroundings by the interposition of the p + type semiconductor layer 35. In the junction isolation region 36, a p type base region 45, an n + type emitter region 46 and a collector region 47 are provided. Are formed, and electrodes 55, 56, 57 are formed in contact with the respective regions.

【0005】しかしながら、上記半導体装置は、幾分は
小型化やコストダウンが図れても、十分と言うわけには
いかない。チップ面積が増加し、ウエハ1枚あたりとれ
る個数の減少で歩留りが低下し、実質的にコストダウン
が達成出来ない。チップ面積が、静電誘導サイリスタ3
3の形成域Aの面積に、トランジスタ34の形成域Bの
面積が加わった分だけ増加し、結構大きくなってしまう
のである。
However, the above semiconductor device cannot be said to be sufficient even if the size and cost thereof are reduced to some extent. The chip area increases and the number of wafers that can be taken per wafer decreases, so that the yield decreases and it is not possible to achieve a substantial cost reduction. Chip area is static induction thyristor 3
The area of the formation area A of 3 is increased by the area of the formation area B of the transistor 34, and the area is considerably increased.

【0006】[0006]

【発明が解決しようとする課題】上記事情に鑑み、この
発明は、チップ面積の増大を回避することが出来るとと
もに、パワーエレクトロニクス回路の応用に適した性能
のよい集積タイプの半導体装置を提供することを課題と
する。
SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides an integrated type semiconductor device which is capable of avoiding an increase in chip area and is suitable for application to power electronic circuits. Is an issue.

【0007】[0007]

【課題を解決するための手段】前記課題を解決するた
め、この発明にかかる半導体装置は、半導体基板の一側
の表面部分に、第1導電型のカソード領域と第2導電型
のゲート領域とがカソード領域がゲート領域に挟まれる
形で形成されていて、前記半導体基板の上に、前記カソ
ード領域にコンタクトするカソード電極と前記ゲート領
域にコンタクトするゲート電極が形成されており、これ
らゲート電極とカソード電極は、それぞれ、枝部と枝部
が接続されている幹部とよりなり、電極のコンタクトが
枝部でなされ電極の引き出しが幹部でなされている静電
誘導半導体素子を備えた構成において、前記半導体基板
における前記両電極の少なくとも一方の電極の幹部の下
方位置には、第2導電型の半導体層の介在により周りと
絶縁分離されている第1導電型の接合分離領域が設けら
れていて、この接合分離領域に上記静電誘導半導体素子
とは別の半導体素子を設けるようにしている。
In order to solve the above-mentioned problems, a semiconductor device according to the present invention has a cathode region of a first conductivity type and a gate region of a second conductivity type on a surface portion on one side of a semiconductor substrate. Is formed such that the cathode region is sandwiched between the gate regions, and a cathode electrode that contacts the cathode region and a gate electrode that contacts the gate region are formed on the semiconductor substrate. Each of the cathode electrodes is composed of a branch portion and a trunk portion to which the branch portion is connected, and in a configuration including an electrostatic induction semiconductor element in which electrode contact is made by the branch portion and electrode is led by the trunk portion, A semiconductor layer of the second conductivity type is provided at a position below a trunk portion of at least one of the electrodes on the semiconductor substrate so as to be insulated from the surroundings. Have junction isolation region of the first conductivity type is provided and be provided with a separate semiconductor element from the above static induction semiconductor device in this junction isolation region.

【0008】この発明の半導体装置の静電誘導半導体素
子としては、静電誘導サイリスタが挙げられるが、これ
に限らず、静電誘導トランジスタであってもよい。但
し、トランジスタの場合、普通、カソードはソース、ア
ノードはドレインと呼ばれる。この発明の半導体装置の
両電極の少なくとも一方の電極の幹部の下方にある接合
分離領域に設けられた別の半導体素子としては、バイポ
ーラトランジスタや電界効果トランジスタ、ダイオード
などの素子が挙げられ、これらが単独ないし複数併存の
形で設けられる。
The electrostatic induction semiconductor element of the semiconductor device of the present invention may be an electrostatic induction thyristor, but is not limited to this and may be an electrostatic induction transistor. However, in the case of a transistor, the cathode is usually called the source and the anode is called the drain. Examples of another semiconductor element provided in the junction isolation region below the trunk of at least one of the electrodes of the semiconductor device of the present invention include an element such as a bipolar transistor, a field effect transistor, and a diode. It is provided in the form of a single or a plurality of coexisting.

【0009】勿論、この発明の場合、第1導電型がn型
のときは第2導電型はp型であり、逆に、第1導電型が
p型のときは第2導電型はn型となる。
Of course, in the present invention, when the first conductivity type is n-type, the second conductivity type is p-type, and conversely, when the first conductivity type is p-type, the second conductivity type is n-type. Becomes

【0010】[0010]

【作用】この発明の半導体装置は、十分に電流を流せる
幹部でカソード電極の引き出しがなされているパワーデ
バイス適性のある静電誘導半導体素子を備えている上、
静電誘導半導体素子とは別の半導体素子も備えているた
め、パワーエレクトロニクス回路の応用に適している。
The semiconductor device of the present invention is provided with the electrostatic induction semiconductor element suitable for the power device in which the cathode electrode is drawn out by the trunk portion capable of sufficiently flowing the current.
Since it also has a semiconductor element other than the static induction semiconductor element, it is suitable for application to power electronic circuits.

【0011】それに、この発明の半導体装置における静
電誘導半導体素子とは別の半導体素子は、容量の大きな
静電誘導半導体素子とは接合分離により絶縁分離されて
いて、両素子の間の干渉が防止されているために性能も
良いのである。そして、最も特徴的なことは、この発明
にかかる半導体装置は、静電誘導半導体装置とは別の半
導体素子を設ける接合分離領域は、従来はデッドスペー
スになっていたカソード電極やゲート電極の幹部の下方
の半導体基板部分を利用して設けている。そのため、チ
ップ面積の増大を伴わずにすみ、ウエハ1枚あたりとれ
る個数は殆ど変わらず、集積化が図れた分、そのままコ
ストダウンにつなげられる。
In addition, the semiconductor element other than the electrostatic induction semiconductor element in the semiconductor device of the present invention is insulated and separated from the electrostatic induction semiconductor element having a large capacitance by the junction separation, so that the interference between the two elements is prevented. The performance is good because it is prevented. And, most characteristically, in the semiconductor device according to the present invention, the junction isolation region in which the semiconductor element different from the electrostatic induction semiconductor device is provided is a trunk portion of the cathode electrode or the gate electrode which has conventionally been a dead space. Is provided by utilizing the semiconductor substrate portion below. Therefore, the chip area does not need to be increased, and the number of wafers that can be obtained per wafer is almost the same, and the cost can be directly reduced by the amount of integration.

【0012】[0012]

【実施例】以下、この発明の実施例を、図面を参照しな
がら、詳しく説明する。図1は、実施例にかかる半導体
装置の要部構成を断面してあらわし、図2は、実施例に
かかる半導体装置の半導体基板の上に設けられたカソー
ド電極およびゲート電極の平面形状をあらわす。実施例
の半導体装置1は、図1にみるように、一つの半導体基
板2に静電誘導サイリスタ3と共にバイポーラトランジ
スタ4が設けられている。
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing the configuration of a main part of a semiconductor device according to an embodiment, and FIG. 2 is a plan view of a cathode electrode and a gate electrode provided on a semiconductor substrate of the semiconductor device according to the embodiment. As shown in FIG. 1, the semiconductor device 1 of the embodiment includes a bipolar transistor 4 on one semiconductor substrate 2 together with an electrostatic induction thyristor 3.

【0013】この半導体装置1の静電誘導サイリスタ3
は、半導体基板2の表側の表面部分に、不純物濃度の高
いn+ 型(第1導電型)のカソード領域11と不純物濃
度の高いp+ 型(第2導電型)のゲート領域12とが、
カソード領域11がゲート領域12に挟まれる形で形成
されていて、さらに、半導体基板2の上に、カソード領
域11にコンタクトするカソード電極21とゲート領域
12にコンタクトするゲート電極22が形成されてお
り、一方、半導体基板2の裏側の表面部分は、p + 型の
アノード領域14になっており、その表面にはアノード
電極(図示省略)がくる。そして、半導体基板2におけ
るカソード領域11とアノード領域13の間は、ベース
領域たるn- 型の高比抵抗領域15である。
The electrostatic induction thyristor 3 of this semiconductor device 1
Has a high impurity concentration on the front surface of the semiconductor substrate 2.
I n+Type (first conductivity type) cathode region 11 and impurity concentration
High degree p+Type (second conductivity type) gate region 12
Formed so that the cathode region 11 is sandwiched between the gate regions 12.
The semiconductor substrate 2 and the cathode region.
Cathode electrode 21 and gate region contacting region 11
A gate electrode 22 that contacts 12 is formed
On the other hand, the surface portion on the back side of the semiconductor substrate 2 is p +Type of
An anode region 14 is formed, and an anode is formed on the surface thereof.
An electrode (not shown) comes. And on the semiconductor substrate 2
Between the cathode region 11 and the anode region 13
Area n-This is the high resistivity region 15 of the mold.

【0014】半導体装置1における別の半導体素子たる
バイポーラトランジスタ4の方は、n- 型の接合分離領
域16に設けられている。この接合分離領域16はp+
型の半導体層17の介在により周りと絶縁分離されてい
る。そして、接合分離領域16の中に、p型のベース領
域18、n+ 型のエミッタ領域19およびコレクタ領域
20が形成されていて、それぞれに電極25,26,2
7がコンタクトしており、バイポーラトランジスタ構成
になっている。
The bipolar transistor 4, which is another semiconductor element in the semiconductor device 1, is provided in the n -- type junction isolation region 16. This junction isolation region 16 is p +
It is insulated from the surroundings by the interposition of the semiconductor layer 17 of the mold. Then, in the junction isolation region 16, a p-type base region 18, an n + -type emitter region 19 and a collector region 20 are formed, and electrodes 25, 26, 2 are respectively formed therein.
7 is in contact, and has a bipolar transistor configuration.

【0015】一方、カソード電極21は枝部21aと枝
部21aが接続されている幹部21bとからなり、枝部
21aでカソード領域11にコンタクトし、電流は幹部
21bに集まってボンディングパッド部(図示省略)ま
で導かれる電極の引き出し構成がとられている。他方、
ゲート電極22は枝部22aと枝部22aが接続されて
いる幹部22bとからなり、枝部22aでゲート領域1
2にコンタクトしていて、電流は幹部22bに集められ
ボンディングパッド部(図示省略)まで導かれる電極の
引き出し構成となっている。
On the other hand, the cathode electrode 21 is composed of a branch portion 21a and a stem portion 21b to which the branch portion 21a is connected. The branch portion 21a contacts the cathode region 11, and current is collected in the stem portion 21b to form a bonding pad portion (shown in the figure). The electrode has a lead-out structure that leads to (omitted). On the other hand,
The gate electrode 22 is composed of a branch portion 22a and a trunk portion 22b to which the branch portion 22a is connected.
2 is in contact therewith, and the current is collected in the trunk portion 22b and led to a bonding pad portion (not shown).

【0016】普通、ゲート電極22の幹部22bの下方
には、部分的にはゲート領域を兼ねる場合もある耐圧維
持用のp+ 型の半導体層13が設けられており、このp
+ 型の半導体層13に幹部22bが直にコンタクトして
いる。これに対し、従来、カソード電極21の幹部21
bの下方には、接合分離領域16が形成されており、こ
こにバイポーラトランジスタ4が形成されているのであ
る。従来、カソード電極21の幹部21bの下方には何
も設けられておらず、Siバルク部分がデッドスペース
となっていたのであるが、この発明の半導体装置の場
合、デッドスペースを有効利用するため、チップ面積の
増加を回避して、コストダウンが図れるようになったの
である。普通、バイポーラトランジスタ4の形成後、酸
化膜9を蒸着等により堆積形成し、その上に、2層配線
技術により、カソード電極21の幹部21bを形成する
ようにする。
Normally, a p + -type semiconductor layer 13 for maintaining the breakdown voltage is provided below the trunk portion 22b of the gate electrode 22 and may partially serve as a gate region.
The trunk portion 22b is in direct contact with the + type semiconductor layer 13. On the other hand, conventionally, the trunk portion 21 of the cathode electrode 21 is
A junction isolation region 16 is formed below b, and the bipolar transistor 4 is formed therein. Conventionally, nothing is provided below the trunk portion 21b of the cathode electrode 21, and the Si bulk portion becomes a dead space. However, in the case of the semiconductor device of the present invention, the dead space is effectively used. It has become possible to reduce costs by avoiding an increase in chip area. Usually, after forming the bipolar transistor 4, an oxide film 9 is deposited and formed by vapor deposition or the like, and the trunk portion 21b of the cathode electrode 21 is formed thereon by the two-layer wiring technique.

【0017】なお、p+ 型の半導体層17の両側のn-
型半導体層が電気的に絶縁分離されているのは、接合分
離領域16側のn- 型半導体層はバイポーラトランジス
タのコレクタ領域であり、静電誘導サイリスタ3側のn
- 型半導体層はサイリスタのベース領域であって、実使
用の際でも順方向バイアスがかからず導通しないからで
ある。
Note that n − on both sides of the p + type semiconductor layer 17 are formed.
The n - type semiconductor layer on the junction isolation region 16 side is the collector region of the bipolar transistor, and the n - type semiconductor layer on the static induction thyristor 3 side is electrically isolated.
This is because the- type semiconductor layer is the base region of the thyristor, and is not electrically conductive because it is not forward biased even in actual use.

【0018】この発明は、上記実施例に限らない。例え
ば、接合分離領域16が、カソード電極21の幹部21
b下方ではなく、ゲート電極22の幹部22b下方、あ
るいは、両電極21,22の幹部21b,22bの下方
に設けられるようであってもよい。勿論、ゲート電極2
2の幹部22b下方のp+ 型の半導体層13は、少なく
とも接合分離領域16を設ける位置には形成しないよう
にすることは言うまでもない。
The present invention is not limited to the above embodiment. For example, the junction isolation region 16 is the trunk portion 21 of the cathode electrode 21.
It may be provided below the trunk portion 22b of the gate electrode 22 or below the trunk portions 21b and 22b of the electrodes 21 and 22 instead of below the b portion. Of course, the gate electrode 2
It goes without saying that the p + type semiconductor layer 13 below the second trunk portion 22b is not formed at least at the position where the junction isolation region 16 is provided.

【0019】[0019]

【発明の効果】この発明にかかる半導体装置は、パワー
デバイス適性のある静電誘導半導体素子を備えている上
に別の半導体素子をも備えているため、パワーエレクト
ロニクス回路の応用に適しており、しかも、静電誘導半
導体素子と別の半導体素子は、接合分離により両素子間
の干渉が防止されているために性能も良く、加えて、別
の半導体素子はチップ面積の増大を伴わずにすむため
に、十分なコストダウンが見込め、したがって、この発
明の半導体装置は非常に実用的であるということができ
る。
The semiconductor device according to the present invention is suitable for the application of the power electronic circuit because it has the electrostatic induction semiconductor element suitable for the power device and also has another semiconductor element. Moreover, the semiconductor element different from the electrostatic induction semiconductor element has good performance because the interference between the elements is prevented by the junction separation, and in addition, the other semiconductor element does not increase the chip area. Therefore, a sufficient cost reduction can be expected, and therefore the semiconductor device of the present invention can be said to be very practical.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の半導体装置の要部構成をあらわす断面
図である。
FIG. 1 is a cross-sectional view showing a configuration of a main part of a semiconductor device of an example.

【図2】図1の半導体装置の半導体基板の上に設けられ
たカソード電極およびゲート電極をあらわす平面図であ
る。
2 is a plan view showing a cathode electrode and a gate electrode provided on a semiconductor substrate of the semiconductor device of FIG.

【図3】従来の半導体装置の要部構成をあらわす断面図
である。
FIG. 3 is a cross-sectional view showing a configuration of a main part of a conventional semiconductor device.

【図4】図3の半導体装置を上方から見た状態をあらわ
す平面図である。
FIG. 4 is a plan view showing a state of the semiconductor device of FIG. 3 viewed from above.

【符号の説明】 1 半導体装置 2 半導体基板 3 静電誘導サイリスタ(静電誘導半導体素子) 4 バイポーラトランジスタ(別の半導体素子) 21 カソード電極 21a 枝部 21b 幹部 22 ゲート電極 22a 枝部 22b 幹部DESCRIPTION OF SYMBOLS 1 semiconductor device 2 semiconductor substrate 3 electrostatic induction thyristor (electrostatic induction semiconductor element) 4 bipolar transistor (another semiconductor element) 21 cathode electrode 21a branch 21b trunk 22 gate electrode 22a branch 22b trunk

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の一側の表面部分に、第1導
電型のカソード領域と第2導電型のゲート領域とがカソ
ード領域がゲート領域に挟まれる形で形成されていて、
前記半導体基板の上に、前記カソード領域にコンタクト
するカソード電極と前記ゲート領域にコンタクトするゲ
ート電極が形成されており、これらゲート電極とカソー
ド電極は、それぞれ、枝部と枝部が接続されている幹部
とよりなり、電極のコンタクトが枝部でなされ電極の引
き出しが幹部でなされている静電誘導半導体素子を備え
た半導体装置において、前記半導体基板における前記両
電極の少なくとも一方の電極の幹部の下方位置には、第
2導電型の半導体層の介在により周りと絶縁分離されて
いる第1導電型の接合分離領域が設けられていて、この
接合分離領域に上記静電誘導半導体素子とは別の半導体
素子が設けられていることを特徴とする半導体装置。
1. A first conductivity type cathode region and a second conductivity type gate region are formed on a surface portion of one side of a semiconductor substrate such that the cathode region is sandwiched between the gate regions.
A cathode electrode contacting the cathode region and a gate electrode contacting the gate region are formed on the semiconductor substrate, and the gate electrode and the cathode electrode are connected to a branch portion and a branch portion, respectively. In a semiconductor device including an electrostatic induction semiconductor element, which comprises a trunk portion, the electrode contact is made at a branch portion, and the electrode is pulled out at the trunk portion, below a trunk portion of at least one of the electrodes on the semiconductor substrate. At the position, a first conductivity type junction isolation region is provided, which is insulated from the surroundings by interposing a second conductivity type semiconductor layer, and this junction isolation region is different from the electrostatic induction semiconductor element. A semiconductor device comprising a semiconductor element.
JP4182591A 1992-07-09 1992-07-09 Semiconductor device Pending JPH0629518A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4182591A JPH0629518A (en) 1992-07-09 1992-07-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4182591A JPH0629518A (en) 1992-07-09 1992-07-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0629518A true JPH0629518A (en) 1994-02-04

Family

ID=16120967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4182591A Pending JPH0629518A (en) 1992-07-09 1992-07-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0629518A (en)

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