JPH06295926A - Semiconductor device including field effect transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an FET with high gm without lowering the gate breakdown voltage. [Configuration] electrons supplied from the n-Al _0.15 Ga _0.85 As layer 5 travels i-In0 _.2 Ga _0.8 As layer 7a, a 7b. Due to the difference in Al composition ratio, i-Al _0.3 Ga _0.7 As
The height of the potential barrier of the layers 8a and 8b is n-Al.
_{The value} is higher than that of the _0.15 Ga _0.85 As layer 5, the effect of confining electrons is increased, and gm is increased. In addition, the gate electrode 45
Semiconductor layer is in contact is because it is i-Al _0.3 Ga _0.7 As layer 8b, the gate breakdown voltage is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed semiconductor device, and more particularly to improvement of mutual conductance.

[0002]

2. Description of the Related Art Japanese Patent Publication No. 59-53714 discloses a high electron mobility transistor (High Ele) having excellent high frequency characteristics.
ctron Mobility Trangistor (HEMT) is disclosed. The HEMT uses the difference in electron affinity to supply electrons from the electron supply layer to the channel layer, and the electrons travel in the channel layer formed of an undoped semiconductor layer to obtain high electron mobility. It is a thing.

The HEMT will be described with reference to FIGS. 5A and 5B. As shown in FIG. 5A, the HEMT 41 includes an undoped GaAs layer 43, n on a semi-insulating GaAs substrate 42.
^{A +} type AlGaAs layer 44 and a gate electrode 45 are sequentially formed. The energy band diagram of HEMT41 is shown in FIG.
Shown in B. This kind of energy band diagram is
Since the AlGaAs layer 44 has a smaller electron affinity than the GaAs layer 43, the electrons in the AlGaAs layer 44 are GaAs.
This is because it is supplied to the layer 43. The supplied electrons are A
Undoped Ga at the interface between the 1GaAs layer 44 and the GaAs layer
Since it travels on the side of the As layer 43, high electron mobility can be obtained.

Further, Japanese Unexamined Patent Publication No. 1-173760 discloses a double heterojunction FET 34. The double heterojunction FET 34 includes an n-type AlGaAs layer 47, which is an electron supply layer, on the semiconductor substrate side of the HEMT.
Is provided. The double heterojunction FET 34 is
With the energy band structure shown in FIG. 5C, the areal density of electrons supplied to the GaAs layer 43 can be increased more than that of HEMT.

However, the double heterojunction FET3
In No. 4, there is a problem that some of the electrons accelerated in the GaAs layer 43 travel in the AlGaAs layer 47 which is the electron supply layer on the substrate side, and the electron moving speed is reduced.

In order to solve such a problem, the publication also discloses a double heterojunction FET 35 which is an improvement of the double heterojunction FET 34. The double heterojunction FET 35 is an n-type A of the double heterojunction FET 34.
The lGaAs layer 47 is thinly formed, and an undoped GaAs layer 48, a p-type GaAs layer 49 and an undoped GaAs layer 50 are provided on the substrate side thereof.

Thus, the undoped G is formed on the semiconductor substrate side.
By providing the aAs layer 48 and the p-type GaAs layer 49, the double heterojunction FET 35 has the energy band structure shown in FIG. 5D. Therefore, Ga
It is possible to prevent some of the accelerated electrons in the As layer 43 from traveling in the AlGaAs layer 47, which is the electron supply layer on the substrate side, and to travel in the undoped GaAs layer 48. This makes it possible to avoid a decrease in the electron transfer speed.

[0008]

However, the above semiconductor device has the following problems. In any of the semiconductor devices, the semiconductor layer below the gate electrode 45 is
Since it has a role as an electron supply layer, a high concentration of donor impurities is added. In order to improve the mutual conductance (gm = (ΔI _DS / ΔVg)) of the semiconductor device, it is necessary to increase the donor impurity concentration of the AlGaAs layer 44 which is the electron supply layer. Increasing the concentration causes an increase in gate leakage current and a decrease in breakdown voltage. That is, the gate breakdown voltage decreases.

An object of the present invention is to solve the above problems, and to provide a semiconductor device which has a high electron transfer speed and can increase the transconductance without lowering the gate breakdown voltage. To do.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: A) an electron supply layer, B) an electron supply layer sandwiched therebetween, an electron affinity higher than that of the electron supply layer, and a donor. Two channel layers to which no impurities are added, C) Of the two channel layers, the channel layer on the semiconductor substrate side is the first channel layer, and a semiconductor formed between the first channel layer and the semiconductor substrate. A first barrier layer which has a lower electron affinity than the electron supply layer and is not doped with a donor impurity; and D) a channel layer on the gate electrode side of the two channel layers, A semiconductor layer formed as a channel layer between the second channel layer and the gate electrode, the electron affinity of which is smaller than that of the electron supply layer, and a donor impurity is added. And a second barrier layer which is not provided, and the electron supply layer is doped with a donor impurity, and by supplying electrons to the first and second channel layers, a charge is distributed over the entire area. It is characterized by being depleted.

[0011]

In the semiconductor device according to the first aspect, the electron affinity is larger than that of the electron supply layer, and two channel layers to which the donor impurity is not added are formed so as to sandwich the electron supply layer. The electron supply layer is doped with a donor impurity and is
By supplying electrons to the second channel layer, a charge depletion layer is formed in the entire area. In this way, the electron supply layer is made into a charge depletion layer in the entire region, and the electrons supplied from the electron supply layer to the two channel layers travel in the channel layer to which the donor impurity is not added. High mobility.

Further, between the channel layer on the semiconductor substrate side and the semiconductor substrate, a first barrier layer having an electron affinity smaller than that of the electron supply layer and no donor impurity added is formed, and the first barrier layer on the gate electrode side is formed. A second barrier layer having an electron affinity smaller than that of the electron supply layer and containing no donor impurity is formed between the channel layer and the semiconductor substrate. Therefore, the first and second barrier layers can trap electrons traveling in the channel layer in the channel layer.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

[Correspondence between each part of the embodiment and the wording of the claims] "Semi-insulating semiconductor substrate" ... "Semi-insulating Ga
"As substrate 42""Acceptor impurity-doped semiconductor layer" ... "p-GaAs
Layer 10 "" First barrier layer "..." i-Al _0.3
Ga _0.7 As layer 8a "" first channel layer "..." i-In _0.2
Ga _0.8 As layer 7a "" donor impurity-free region "..." i-Al _0.15
Ga _0.85 As layer 6a "" donor impurity existing region "..." n-Al _0.15
Ga _0.85 As layer 5 "" donor impurity-free region "..." i-Al _0.15
Ga _0.85 As layer 6b "" second channel layer "..." i-In _0.2
Ga _0.8 As layer 7b "" second barrier layer "..........." i-Al _0.3
Ga _0.7 As layer 8b "Ohmic contact formation layer" ... "n-GaAs
Layer 47 "" Implantation part "..." Si ion implantation layers 11 and 12 "[Structure of FET1] As shown in Fig. 2, in FET1, the semiconductor substrate is a semi-insulating semiconductor substrate. On the semi-insulating GaAs substrate 42, an undoped buffer layer (hereinafter (i-)
Abbreviated) GaAs layer 43, P-GaAs layer 10 as an acceptor impurity-added semiconductor layer, and i as a first barrier layer
-Al _0.3 Ga _0.7 As layer 8a, the first is a channel layer i-In _0.2 Ga _0.8 As layer _{7a, i-Al 0.15 Ga 0.} 8 5 As layers 6a is a donor impurity absence regions, donor impurity existing region N-Al _0.15 Ga _0.85 As layer 5, i-Al _0.15 Ga _0.85 As layer 6 b which is a donor impurity absent region, and i-In _0.2 Ga _0.8 As which is the second channel layer.
Layer 7b, a second barrier layer i-Al _0.3 Ga _0.7 As
Layer 8b, n-GaAs layer 4 which is an ohmic contact formation layer
7 are sequentially formed.

A source electrode 4 and a drain electrode 3 are formed on the n-GaAs layer 47 by ohmic contact. A recess structure is formed on the n-GaAs layer 47 between the source electrode 4 and the drain electrode 3, and a gate electrode 45 is formed.

In this embodiment, the i-Al _{0.15 Ga0.85} As layers 6a and 6 which are the donor impurity absent regions are formed.
b and donor impurity existing region n-Al _0.15 Ga
_The electron supply layer is formed of _0.85 As layer 5.

The data of the respective semiconductor layers shown are shown below.

(1) About i-GaAs layer 43 Thickness: 2000 Å (2) About p-GaAs layer 10 Thickness: 300 Å Impurity concentration: 1 × 10 ¹⁷ cm ⁻³ (3) i-Al _0.3 Ga _0.7 As layer 8a Thickness: 250 Å (4) i-In _0.2 Ga _0.8 As layer 7a Thickness: 70 Å (5) i-Al _0.15 Ga _0.85 As layer 6a Thickness: 20 Å (6) n- Al _0.15 Ga _0.85 As layer 5 Thickness: 60 Å Impurity concentration: 4 × 10 ¹⁸ cm ⁻³ (7) i-Al _0.15 Ga _0.85 As layer 6 b Thickness: 20 Å (8) i-In _0.2 Ga _0.8 As layer 7b to the thickness: 70 Å _{(9) i-Al 0.3 Ga} 0.7 As layer 8b for thickness: 13 Angstrom (10) n-GaAs layer 47 thickness for: 300 Å impurity concentration: 5 in the present embodiment [Production method of FET1] × 10 ¹⁷ cm ^-3, each of the semiconductor layers, molecular beam epitaxy (molecularbeam epit
axy: MBE) method. MOCVD (metal organic chemical vapor depositi) is not used.
on) method.

The Si ion-implanted layers 11 and 12 which are impurity-implanted portions make contact between the source electrode 4 and the drain electrode 3 and the i-Al _0.15 Ga _0.85 As layers 6a and 6b. Therefore, the electrons traveling in the channel layer can be taken out via the source electrode 4 and the drain electrode 3. In this example, ion species: ²⁸ Si was formed by ion-implanting Si ⁺ from the substrate surface under the conditions of an acceleration energy of 150 KeV and a dose amount of 2 × 10 ¹³ cm ⁻² .

[Energy band of FET1] FET1
The energy band diagram of is shown in FIG. As shown in the figure, the electrons supplied from the n-Al _0.15 Ga _0.85 As layer 5 are
Since it travels through the i-In _0.2 Ga _0.8 As layers 7a and 7b,
The electron moving speed is high. The n-Al _0.15 Ga _0.85 As layer 5 is turned into a charge depletion layer in the entire area by supplying electrons to the i-In _0.2 Ga _0.8 As layers 7a and 7b.

The Al composition ratio of the barrier layer i-
In the case of Al _0.3 Ga _0.7 As layers 8a and 8b, it is 0.3, whereas n-A which is the donor impurity existing region of the electron supply layer.
In l _0. 1 ₅ Ga _0.85 As layer 5 is 0.15. Therefore, the i-Al _0.3 Ga _0.7 As layer 8a, which is a barrier layer,
The height of the potential barrier of 8b is higher than that of the n-Al _0.15 Ga _0.85 As layer 5, which is the donor impurity existing region of the electron supply layer, and the electron confinement effect can be enhanced. Therefore, the current flowing through the substrate side can be prevented and the mutual conductance (gm) increases.

Further, since the semiconductor layer in contact with the gate electrode 45 is the i-Al _0.3 Ga _0.7 As layer 8b, the gate breakdown voltage is improved.

Further, the i-Al _0.3 Ga _0.7 As layer 8b and i
The p-GaAs layer 10 to which the acceptor impurity is added is formed between the -GaAs layers 43. Therefore,
The electron confinement effect can be further enhanced, and gm can be further enhanced. The arrow α in FIG. 1 indicates the P-GaAs layer 1.
0 is formed, and the arrow β in FIG. 1 shows the case where the P-GaAs layer 10 is not formed.

In addition, i-
The Al _0.15 Ga _0.85 As layers 6a and 6b are made of n-Al _0.15 G.
a _{0.85 The} donor impurity existing in the As layer 5 is i-In _0.2.
Ga _0. 8aS layer 7a, to prevent scattering electrons traveling 7b. Therefore, a higher electron velocity can be obtained and gm can be improved.

In this embodiment, as described above, the n-Al _0.15 Ga _0.85 As layer 5 has a thickness of 60 angstroms, and the i-Al _0.15 Ga _0.85 As layers 6a and 6b each include 20 layers.
Since it is Angstrom, i-In _0.2 Ga _0.8 As
The electrons traveling in the layers 7a and 7b are coupled by the tunnel effect, and the two channel layers substantially operate as one channel. Thereby, gm can be made higher.

[Other Embodiments] FIG. 4 shows an FET 21 as another embodiment. In the FET 21, the donor impurity existing region has a structure in which a high concentration of the donor impurity is added only to the surface of one atomic layer (hereinafter referred to as a δ-doped structure). Therefore, the electron supply layer can be thinned, and the distance between the layer to which the donor impurity is added and the gate electrode 45 can be reduced. Thereby, a higher gm can be obtained.

In this example, Si (silicon) was used as the donor impurity. In addition, i-Al _0.15
The Ga _0.85 As layers 6a and 6b are substantially the same except that they are both 30 angstroms thick, and the description thereof is omitted. The donor impurity concentration in the donor impurity existing region was 3 × 10 ¹² cm ⁻² .

FIG. 3 shows an energy band diagram of the FET 21. As shown in the figure, also in this embodiment, the electron moving speed, the electron confinement effect, the improvement of the gate breakdown voltage,
Like the FET 1, the scattering of electrons traveling in the i-In _0.2 Ga _0.8 As layers 7a and 7b is prevented, and the channel layer operates substantially as one channel.

In the FET 21, since the thickness of the electron supply layer (the total thickness of the i-Al _0.15 Ga _0.85 As layers 6a and 6b) is about 60 angstroms, the i-In
_A higher tunnel effect can be expected while preventing scattering of electrons traveling in the _0.2 Ga _0.8 As layers 7a and 7b. Also,
Since it has a δ-doped structure, the donor impurity concentration can be easily increased by using the MBE method.

[Other Application Examples] In the FET 1, i-Al _0.15 Ga0 which is a donor impurity absent region.
_.85 As layers 6a and 6b and an n-Al _0.15 Ga _0.85 As layer 5 which is a donor impurity existence region were used to form an electron supply layer.
The Al _0.15 Ga _0.85 As layers 6a and 6b may not be provided. As a result, the layer thickness of the electron supply layer becomes thin and the tunnel effect is likely to occur.

In each of the above embodiments, no impurity is added to the second barrier layer in contact with the gate electrode 45, but the entire area of the second barrier layer is a charge depletion layer due to Schottky contact with the gate electrode. It is possible to add as much donor impurity as possible to the second barrier layer. This facilitates the flow of current between the source electrode 4 and the channel layer and between the drain electrode 3 and the channel layer.

It should be noted, it is provided with the Si ion implantation layer 11, 12 for making contact with the source electrode 4 and drain electrode 3 i-Al0 _.15 Ga _0.85 As layer 6a, 6b in each of the above embodiments When the donor impurities are added to the second barrier layer as described above, the Si ion implantation layers 11 and 12 may be omitted. This simplifies the manufacturing process.

In each of the above embodiments, the same material is used for the i-In _0.2 Ga _0.8 As layer 7a which is the first channel layer and the i-In _0.2 Ga _0.8 As layer 7b which is the second channel layer. Composed of. However, the material of the second channel layer 7b is larger than that of the first channel layer 7a in the low electric field mobility, and the material of the first channel layer 7a is larger than that in the second channel layer 7b in the saturation electron velocity. You may use the thing of. This can provide a FET with a higher gm.

In each of the above embodiments, the barrier layer is made of AlGaAs, the channel layer is made of InGaAs, and the electron supply layer is made of AlGaAs. However, the present invention is not limited to this. Other combinations may be used as long as they are larger than the layers and the barrier layer has an electron affinity smaller than that of the electron supply layer.

Further, in each of the above embodiments, the transistor is described as a single unit, but it may be configured as an integrated circuit including an FET, for example, a high speed digital IC or a microwave monolithic integrated circuit.

[0036]

In the semiconductor device according to the first aspect of the present invention, the electron affinity is larger than that of the electron supply layer, and two channel layers to which the donor impurity is not added are formed so as to sandwich the electron supply layer. . Also,
A donor impurity is added to the electron supply layer, and electrons are supplied to the first and second channel layers to form a charge depletion layer in the entire region. In this way, the electron supply layer is formed into a charge depletion layer in the entire area, and the electrons supplied from the electron supply layer to the two channel layers travel in the channel layer to which the donor impurity is not added, and The moving speed is high.

Further, between the channel layer on the semiconductor substrate side and the semiconductor substrate, a first barrier layer which has an electron affinity smaller than that of the electron supply layer and is not added with a donor impurity is formed. A second barrier layer having an electron affinity smaller than that of the electron supply layer and containing no donor impurity is formed between the channel layer and the semiconductor substrate. Therefore, the first and second barrier layers can trap the traveling electrons in the channel layer and prevent the traveling electrons in the other semiconductor layers on the substrate side. That is, it is possible to provide a semiconductor device capable of increasing the mutual conductance without lowering the gate breakdown voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing an energy band structure of a FET 1 according to the present invention.

FIG. 2 is a cross-sectional view of a main part of FET1.

FIG. 3 is a diagram showing an energy band structure of an FET 21, which is another embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a FET 21.

FIG. 5 is a diagram showing a conventional semiconductor. A is a sectional view of a main part of the HEMT, B is an energy band diagram of the HEMT, and C and D.
FIG. 4 is an energy band diagram of a double heterojunction FET.

[Explanation of symbols]

3 ... Drain electrode 4 ... Source electrode 5 ... n-Al _0.15 Ga _0.85 As layer 6a, 6b ... i-Al _0.15 Ga _0.85 As layer 7a, 7b ... i-In _0.2 Ga _0.8 As layer 8a, 8b ... i-Al _0.3 Ga _0.7 As layer 10 ... p-GaAs layer 11, 12 ... Si ion implantation layer 42・ ・ ・ Semi-insulating GaAs substrate 43 ・ ・ ・ ・ ・ i-GaAs layer 45 ・ ・ ・ ・ Gate electrode 47 ・ ・ ・ ・ ・ ・ n-GaAs layer

Claims (1)

[Claims] 1. A semiconductor device comprising: a plurality of semiconductor layers provided on a semi-insulating semiconductor substrate; and a gate electrode provided on the plurality of semiconductor layers, wherein the plurality of semiconductor layers include at least A ) Electron supply layer, B) Two channel layers that are formed so as to sandwich the electron supply layer and have an electron affinity higher than that of the electron supply layer and no donor impurity is added, C) Of the two channel layers A semiconductor layer formed between the first channel layer and the semiconductor substrate, wherein the electron affinity is smaller than that of the electron supply layer, and the donor impurity is First barrier layer not added, D) Of the two channel layers, the channel layer on the gate electrode side is the second channel layer, and the second channel layer and the gate electrode A second barrier layer having an electron affinity smaller than that of the electron supply layer and having no donor impurity added, and the electron supply layer has a donor impurity A semiconductor device, characterized in that the charge depletion layer is formed in the entire region by being supplied with electrons to the first and second channel layers.