JPH06311152A - Data discrimination circuit and optical receiver using the same - Google Patents

Abstract

(57) [Abstract] [Purpose] With respect to a data identification circuit for identifying a signal, it is possible to output identification data in which the phase relationship between data and a clock is determined in an appropriate state with a simple circuit configuration. A clock distribution unit (4) for generating clock signals having different phases and first and second data identification / determination units (1 ,, 2) to which different clock signals are respectively input and data is commonly input. 2) and the identification data and the identification determination result based on the phase relationship between the data and the first clock signal, and the identification data and the data and the second clock signal identified by the second clock signal. And an identification data selection unit (3) for inputting an identification determination result based on the phase relationship with and selecting either the first identification data or the second identification data based on the both identification determination results.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Field of the Related Art (FIG. 22) Problem to be Solved by the Invention Means for Solving the Problem Action Example (FIG. 1) Operation Principle of the Invention (FIG. 2, FIG. 3) ) Description of operation of the embodiment (FIGS. 4 to 9) Specific examples of each part of the embodiment (FIGS. 7 to 20) Application examples of the present invention (FIGS. 21 and 22)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data discriminating circuit for discriminating digital signals and an optical receiver using the same.
In particular, the present invention relates to a data identification circuit capable of accurate identification with a simple configuration and an optical receiver using the same.

With the development of optical communication technology, optical transmission technology has been introduced to lay an optical fiber not only in the trunk line system but also in the subscriber's house to transmit broadband information such as moving images. The Home (FTTH) etc. have been noticed and studied. Thus, low cost is a very important requirement when introducing an optical transmission system to a subscriber system. For this reason, it is necessary to greatly simplify the structure of the transmitter and the receiver as compared with the one used in the trunk line system, and to reduce the number of adjustment parts as much as possible.

Particularly, in a receiver, in a data discriminating circuit which discriminates a digital "1" or "0" after converting an optical signal transmitted through an optical fiber into an electric signal, the data and the discrimination clock are distinguished. It is necessary to keep the phase between them in an appropriate relationship.

It is important to simplify this part as well so as to be suitable for an LSI so that individual adjustment is not necessary. Further, even in the case of LSI, it is necessary to solve some problems such as reduction of circuit scale or reduction of power consumption in order to introduce into subscriber system by making the configuration as simple as possible.

[0006]

2. Description of the Related Art The configuration of an optical receiver according to the prior art is shown in FIG. 23 (1) in the case of an optical repeater for transmission between terminal stations in a trunk system. In a conventional optical receiver,
The light receiving element 21 receives the optical signal transmitted through the optical fiber 20.
Converts the optical signal into an electrical signal, and the equalizing and amplifying circuit 22
The signal is amplified to a level that can be discriminated by and applied to the discrimination reproduction circuit 23 and timing circuit 24.

The timing circuit 24 extracts the identification clock and inputs it to the identification reproduction circuit 23. At this time,
Signals input to the identification reproduction circuit 23 and the timing circuit 2
The phase relationship with the clock from 4 is not uniquely determined due to variations in propagation time in each circuit, etc. Therefore, in order to ensure an appropriate phase relationship, a phase relationship adjusting unit is usually provided in some form. Is.

In the case of the above-mentioned optical receiver or the like, a coaxial cable 25 or the like is used between the timing circuit and the identification / reproduction circuit,
In many cases, a desired phase relationship is obtained by appropriately adjusting the length of the coaxial cable 25.

Further, with the recent progress of IC technology, there is an optical receiver provided with a circuit for automatically adjusting the phase relationship. FIG. 23 (2) shows an example of such a phase automatic adjustment circuit (Source: Peter Cochrane et al.,
IEEE Journal on Selected Areas in Communications,
Vol. SAC-4, No. 9, December, 1986).

In the circuit shown in FIG. 23 (2), the signal before identification and the signal after identification are respectively output to the SR latches 26 and 2 respectively.
7, the signal pulse output is integrated, the difference voltage between the level and the reference level is fed back to the voltage control phase shifter 28, and the phase of the clock is kept at a predetermined value. .

In the circuit shown in FIG. 23 (2), the circuit shown in FIG.
Compared to the case where the coaxial cable of 3 (1) is used, even if the optimum phase relationship changes due to the temperature characteristics of the circuit or the characteristic changes with time, a constant phase relationship can be maintained by feedback.

Such a circuit attempts to maintain the proper phase by continuously controlling the clock phase, but the circuit becomes complicated and in many cases the power consumption increases. For this reason, it is difficult to introduce it into the subscriber system unless the configuration is simplified and the power consumption is reduced.

By the way, in the subscriber system, since the transmission distance is very short (about 1 to several Km) as compared with the transmission between terminal stations, the optical level input to the optical receiver can be systematically high. Is.

As a result, the discriminating circuit has a phase margin enough to ensure the desired characteristics of the received signal. Therefore, instead of the continuous phase control described above,
For example, it is possible to obtain a desired identification characteristic by selecting a clock having one phase from a plurality of clocks having several different phases and performing identification using the clock.

As an example of the configuration of such a data identification circuit, there are "JP-A-1-233850" and "JP-A-1-1-1".
88050 "and the like. Among these, "Japanese Patent Laid-Open No. 1-233"
In "850", the same data is identified by two types of clocks having slightly different timings, and if the results are different, it is determined that the clock phase is not appropriate and the clock phase is inverted.

Further, in Japanese Unexamined Patent Publication No. 1-188050, a clock having a frequency twice that of the data rate is prepared, and when data is input, the T-F / F is reset at the rising edge of the data to generate a clock having the double frequency. The frequency is divided and the data is identified by a clock having a certain time delay from the rising edge of the data.

In any of these, the clock phase adjusting circuit itself can be configured by a logic circuit, for example, a gate array, so that the circuit can be simplified and the cost can be reduced.

However, in Japanese Patent Laid-Open No. 1-233850, for example, even when data of which two types of clocks are both "0" are mistakenly identified as "1", it is determined as an appropriate clock, and the two types of clocks are used. Since the time difference between the clocks and the time difference when the input data is branched and input to the two identification units (D-F / F), the identification result is affected,
It has drawbacks such as requiring very delicate timing design.

Further, in Japanese Patent Laid-Open No. 1-188050, 2
In order to handle a clock having a double frequency, a clock having a frequency twice as high as the transmission speed of the transmission system must be prepared, which not only lacks affinity for the entire system configuration but also has a clock multiplication circuit. As a result, there is a drawback that the circuit becomes large in scale.

[0020]

Therefore, in the prior art, it is impossible or impossible to construct a system for performing identification while maintaining a stable and reliable phase relationship between data and clocks. It has the problem that the drawbacks of circuit complexity and scale increase are inevitable.

The present invention, which has a relatively simple circuit configuration, determines a phase relationship between data and a clock in an appropriate state, and makes it possible to output correctly identified data, and the data identification circuit. An object is to provide an optical receiver using a circuit.

[0022]

In a data discriminating circuit according to the present invention, a clock distributor for generating first and second clock signals having different phases, and a first and a second clock signal from the clock distributor, respectively. It has the 1st and 2nd data identification / judgment part by which data is inputted and data is inputted in common. The first data identification / determination unit determines the first identification data identified by the first data identification / determination unit based on the first clock signal, and the phase relationship between the input data and the first clock signal. One identification determination result is generated. Further, the second data identification / determination unit determines the second identification data identified by the second data identification / determination unit by the second clock signal and the phase relationship between the data and the second clock signal. A second identification determination result is generated.

Further, it has an identification data selecting section for selecting and outputting either the first identification data or the second identification data based on the first and second identification determination results.
Further, in the data discriminating circuit of the present invention, each of the first and second data discriminating / determining units has a data discriminating unit, a data / clock phase relation detection discriminating unit and a phase relation discrimination result processing unit. The data identification unit identifies the data input from the data input unit using the clock input from the clock distribution unit. The data / clock phase relationship detection determination unit detects and determines the phase relationship between the input data and the clock using the phase relationship between the identified data and the input data from the data input unit.

The phase relationship determination result processing section applies an identification data selection control signal to the identification data selection section based on the phase relationship detection determination result output by the data / clock phase relationship detection determination section and the input data. To generate.

The optical receiver according to the present invention further comprises an optical signal receiving section, an equalizing amplifier for amplifying the received signal converted into an electric signal from the optical signal receiving section to a predetermined level, a timing extraction circuit and the above data. It has an identification circuit. The output of this equalization amplifier is used as the data input of the data identification circuit, and the output of the timing extraction circuit is used as the clock input of the data identification circuit.

[0026]

In the data discriminating circuit of the present invention, the input data commonly input by the first and second clock signals having different phases are discriminated by the first and second data discriminating / determining sections. Further, the first and second data identification / determination units generate identification determination results based on the identified first identification data and the phase relationship between the input data and the clock signal.

Based on the first and second identification determination results, the identification data selection section selects and outputs either the first identification data or the second identification data. Therefore, according to the present invention, the correct phase relationship between the input data and the identification clock can be obtained in either the first or second data identification / determination unit, and the identification data properly identified can be output.

Further, in order to detect and determine the phase relationship between the input data and the identification clock, each data identification / determination section includes a data identification section, a data / clock phase relationship detection determination section, and a phase relationship determination result processing section. have. Each of these functional units can be realized by a logic circuit that identifies and detects data by using a clock.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the data discriminating circuit of the present invention. Reference numerals 1 and 2 are preferably data identification / determination units having the same configuration. 3 is an identification data selection unit, and 4
Is a clock distribution unit. Reference numeral 5 is a data input unit, and 6 is a clock signal (CLK) input unit.

The input data input from the data input section 5 is, for example, an optical signal received by a light receiving section of an optical receiver, which will be described later, converted into an electric signal and further amplified to a discriminable level.

This input data is input to the data identification / determination units 1 and 2. The data identification / determination units 1 and 2 include
Further, a clock of a predetermined phase generated by the clock distribution unit 4 based on the clock signal input from the clock signal input unit 6 is input.

Here, the data identification / determination units 1 and 2 identify the input data that has been input by the clock supplied from the clock distribution unit 4, and are generated based on the identification data and the phase relationship between the input data and the clock. The identification data and the determination result are output.

Reference numeral 3 is an identification data selection unit, which inputs identification data and determination results from each of the data identification / determination units 1 and 2. Then, the identification data output unit 7 validates the identification data from one of the data identification / determination units 1 and 2.
Output to.

Next, the detailed configuration of the data identification / determination units 1 and 2 will be described by taking the data identification / determination unit 1 as an example. The data identification / determination unit 1 includes a data identification unit 10, a data / clock phase relationship detection determination unit 11, and a phase relationship determination result processing unit 12.
And a determination clock phase control unit 13.
The data input from the data input unit 5 is input to the data identification unit 10. In the embodiment of FIG. 1, the data identification section 10 is composed of a delay flip-flop D-FF, and data is input to its D terminal. Further, the clock of the first phase is input from the clock distribution unit 4 to the C terminal.
Therefore, in the D-FF 10, the "1" and "0" levels of the data are identified by the clock of the first phase.

The data identified by the D-FF 10 is
It is input to the data / clock phase relationship detection determination unit 11. The data / clock phase relationship detection determination unit 11 detects the phase relationship between the identification data identified by the data identification unit 10 and the input data from the data input unit 5. Furthermore,
Based on the information about the phase relationship, it is determined whether the phase relationship between the input data and the clock of the first phase for identifying the input data is appropriate.

Next, the output of the data / clock phase relation detection / judgment unit 11 is processed in the phase relation judgment result processing unit 12. The phase relationship determination result processing unit 12 causes the identification data selection unit 3 to perform data identification / discrimination based on the processing result.
A control signal for validating one of the identification data of the determination units 1 and 2 and outputting it to the identification data output unit 7 is generated.

The configuration of the data identification / determination unit 2 in FIG. 1 is the same as that of the data identification / determination unit 1. Therefore, the symbols in the data identification / determination unit 2, 13 (2), 111
(2), 10C (2) and 10D (2) respectively,
13, 111, 10C and 10 of the data identification / determination unit 1
It means that it is connected to the part corresponding to D.

2 and 3 are diagrams for explaining the operation principle of the present invention, which is prepared in order to better understand the operation of the embodiment of FIG. First, the rising phase of the clock from the clock distribution unit 4 (identifying data at this phase) is typically in the first half, the second half, or the first half of the data, or It is possible to assume four phase relationships, that is, in the first half or in the second half of the latter half.

On the other hand, the data has a period in which the identification is uncertain before and after the data switching phase due to the setup / hold time of the D-FF 10, the clock, and the jitter of the data. The hatched portions at the front / back of the input data shown in FIGS. 2 and 3 (1) are the identification indetermination period. When the clock rises during such an identification indetermination period, the data may not be identified.

FIG. 2 shows (2) CL for (1) data.
This is the case where the rising phase of K is in the indefinite period of the front part of the data, and FIG. 3 shows that (2) CL for (1) data.
This is the case where the rising phase of K is in the final period of the latter half of the data.

In FIG. 2, (2) CLK indicates the rising edge of the first phase clock input from the clock distribution unit 4 to the data identification / determination unit 1, and (3) 1 / 2TS-CL
K indicates the rising edge of the second phase clock input from the clock distribution unit 4 to the data identification / determination units 1 and 2.

Clock signals (2) CLK and (3)
1 / 2TS-CLK has a predetermined phase difference, and the embodiment of FIG. 1 is an example having a phase difference of 1/2 time slot. (2) The data input to the data identification / determination unit 1 is identified at the rising edge of CLK. The identified data is as shown in FIG.

Then, the EXOR logic of the (4) identification data and the (1) data is taken. Depending on the result,
The phase relationship between (1) data and (2) CLK is detected,
A pulse output having a pulse width as shown in FIG. 2 (5) is obtained. The detection result at this time shows the phase relationship by the magnitude of the pulse width. This can be easily understood by comparing with FIG. 3 (5) described later.

Further, FIG. 2 (5) showing the phase relationship detection result.
Pulse is the second phase clock (3) 1 / 2TS-CLK
Is determined by the rising phase of. The logic level of this discrimination determination result is "L" [see (6) A in FIG. 2],
(2) It means that the rising phase of CLK is in the first half of the input data (1).

In this case, the third phase clock (7) 3 / 4TS-CLK, which is delayed from the second phase clock (3) 1 / 2TS-CLK by 1/4 cycle, again has a phase relationship. The pulse of FIG. 2 (5), which is the detection result, is identified and determined. The logic level of this discrimination judgment result is also "L" [Fig.
(8) B], (2) It means that the rising edge of CLK is in the first half of the first half of the input data (1), that is, in the unidentifiable period. Therefore, the data identified by the clock having such a phase cannot be adopted.

Next, referring to FIG. 3, a case where the rising edge of the identification clock is in the final half period of the data will be described. (2) CLK and (3) 1 / 2TS-CLK are the same as those described with reference to FIG.

The input data input to the data identification / determination unit 1 is identified at the rising phase of the identification clock (2) CLK, and the identification data is as shown in FIG. 3 (4). Then, the EXOR logic of the (4) identification data and the (1) data is taken. As a result, a pulse output having the pulse width shown in FIG. 2 (5) is obtained.

Further, FIG. 2 (5) showing the result of the phase relation detection.
Pulse is the second phase clock (3) 1 / 2TS-CLK
Identification is made at the rising edge of. The logic level of this discrimination determination result is "H", unlike the case of FIG. 2 [FIG.
(6) See A].

Therefore, in this case, (2) the rising edge of CLK is in the latter half of (1) data.
And in this case, the second phase clock (3) 1 / 2TS-
Judgment clock (7) advanced by 1/4 cycle from the CLK phase
Fig. 3 which is the result of phase relation detection by 1 / 4TS-CLK.
The pulse of (5) is identified and determined. The logic level of this discrimination determination result is "L" [see (8) B in FIG. 3]. Therefore, in this case, it means that the rising edge of the clock (2) CLK is in the first half of the latter half of the input data (1).

Different from the case of FIG. 2, the two discrimination judgment results A are logic "H" and B are logic "L", and the rising phase of the discrimination clock (2) CLK is a square in the latter half of the input data. Means you are in a period. The data identified by the clock of such a phase can be adopted as being correctly identified.

An embodiment of the present invention which operates based on the above-described operation principle will be described with reference to the time charts of FIGS. 4 and 5 by returning to FIG. 1 again. FIG. 4 shows a case where the rising edge of the identification clock (2) CLK of the first phase is (1) in the definite period of the first half of the data, and FIG. 5 shows (1).
It shows the case in the uncertain period at the rear of the data. Therefore, including the case of the operation principle explanatory diagrams of FIGS. 2 and 3,
As described above, four typical phase relationships are shown as the relationship between (1) data and (2) rising edge of CLK.

Returning to FIG. 4, (1) data is input from the data input unit 5 to the data identifying unit 10 of the data identifying / determining unit 1 and the corresponding data identifying unit 10 of the data identifying / determining unit 2.
Input to (2).

The clock input from the clock input unit 6 to the clock distribution unit 4 is adjusted to a predetermined phase and supplied to each unit. The identification clock of the first phase having the phase shown in FIG. 4B is input from the clock distribution unit 4 to the C terminal of the data identification unit 10. On the other hand, a clock having a predetermined phase difference from the first phase clock shown in FIG. 4 (2) is input to the C terminal of the data identification section 10 (2) of the data identification / determination section 2. The predetermined phase difference is typically as can be seen from the description given below with respect to FIG.
It has a phase difference of 1/2 time slot (1 / 2TS).

Therefore, FIG. 5 (2) is an identification clock of a phase delayed by 1/2 time slot from the identification clock of the first phase shown in FIG. 4 (2). In the following description, FIG. The clock of (2) is the data identification unit 10
It is supposed to be input in (2).

In the data identifying section 10, CLK (2)
The (1) data is identified at the rising timing of, and becomes the identification data of (3) in FIG. This identification data is shown in FIG.
In this embodiment, it is guided to the selection circuit 30 in the identification data selection unit 3. At the same time, (1) data is obtained by the phase relationship detection / determination unit
It is input to the data / clock phase relation detecting unit 110 (hereinafter, abbreviated as phase relation detecting unit) 110 in the No. 1 unit.

Here, the phase relationship detecting section 110 may have various configurations. Specifically, in order to output the phase relationship as a pulse width, as shown in FIGS. 10 (1) to 10 (5), an inverter is used. 71 and EXOR logic circuit 72 [FIG. 10 (1)], NOR circuit 73 [FIG. 10 (2)],
Combination of inverter 74 and AND circuit 75 [Fig.
(3)], AND circuit 76 [FIG. 10 (4)] or EX
It is possible to selectively employ any combination of the OR logic circuit 77 and the inverter 78 that inverts the clock of the D-FF 111 [FIG. 10 (5)]. Further, although not shown, it is also possible to configure by an SR-FF (set / reset flip-flop).

In the detailed description of the operation of the embodiment shown in FIG. 1, an example using the configuration of FIG. 10 (3) as the phase relationship detecting section 110 will be described below. In addition, A in FIG.
The input data is passed through the inverter 74 to one input of the ND circuit 75, and the Q output of the data identification unit 10 is input to the other input. The data (1) in FIGS. 4 and 5 indicates data that is not inverted.

In such a relationship, the phase relationship detecting section 110 detects the phase relationship between (1) data and (3) identification data, and thus the phase relationship between (1) data and (2) CLK. This detected phase relationship is indicated by the pulse width. That is, in FIG. 4, (4) phase relation pulse 1 is output from the phase relation detection unit 110 as a detection result.

As can be understood from the description based on FIGS. 2 and 3, the pulse width of the (4) phase-related pulse 1 changes according to (2) the rising phase of CLK with respect to (1) data. .

(4) Phase-related pulse 1 is further D-FF1
11 is input. The second-phase clock (5) CLK2 is input to the D-FF 111. This (5) CL
K2 has a phase difference of ½ time slot from (2) CLK in FIGS. 4 and 5.

In the D-FF 111, (4) phase-related pulse 1 is identified by (5) the rising phase of CLK2. The identification result is shown in FIG. 4 (6). That is, the logic level is "L". On the other hand, the output from the phase relationship detecting unit 110 is input to the D input terminal of another D-FF 112. To the C input terminal of the D-FF 112, the determination clock (7) CLK3 of the third phase whose phase is controlled via the determination clock phase control circuit 13 is input.

This (7) CLK3 is further delayed by 1/4 time slot from (5) CLK2 by the discrimination result in the D-FF 111, that is, the clock phase control signal shown in FIG. 4 (6). Is the given clock.
That is, (6) when the logic level of the judgment clock phase control signal is "L", (2) the rising edge of CLK2 is (1).
1 based on the results detected as being in the first half of the data
The determination clock phase control circuit 13 controls the phase delay of / 4 time slots.

Therefore, the D-FF 112 discriminates (4) phase-related pulse 1 by (7) the rising phase of CLK3. The identification result is (8) phase-related pulse 2
Is output as. This (8) phase-related pulse 2 is D
The EXOR circuit 12 of the phase relation determination result processing unit 12 together with the (6) determination clock phase control signal from the FF 111
Input to 1.

In the EXOR circuit 121, (6) the judgment clock phase control signal and (8) the phase related pulse 2 EX
When the OR logic is taken, the logic output is as shown in FIG. Next, this (9) EXOR is DF
It is input to the D input terminal of F122.

The C input terminal of the D-FF 122 has (1)
The inverted data (10) which is inverted by giving a predetermined delay to the data is input. Therefore, the E of the EXOR circuit 121
The XOR logic output (9) is identified by the rising phase of the inverted data (10), that is, the falling phase of the data (1).

The result identified by the D-FF 122 is (1
1) It becomes an identification data selection signal. This signal is applied to the S input terminal of the SR-FF 31, which is the switching control unit of the identification data selection unit 3. Further, the identification data selection unit 3
Is a selection switch 30 including a multiplexer or the like.
And receives identification data from the first and second data identification / determination units 1 and 2.

The two (3) identification data input to the selection switch 30 are controlled by the switching control unit 31, and one of them is selected and output. In the example of FIG. 4, since the phase of (2) CLK is the phase at which (1) data can be properly identified, the first data identification / determination unit 1
(3) identification data from (3) is output from the selection switcher 30 [see (12) in FIG. 4].

In FIG. 5, (2) CL is added at the rear of (1) data.
7 is an operation time chart when there is a rising phase of K. In this case, as in the case described with reference to FIG. 2, (1) is a case where the data cannot be normally identified.

As described with reference to FIG. 4, the phase relationship between (3) identification data (3) and (1) data identified by (2) the rising phase of CLK is detected. This phase relationship is indicated by (4) phase relationship pulse 1. Further, this phase-related pulse 1 is identified by (5) CLK2.

In the case of FIG. 5, since (2) the rising phase of CLK is different from the case of FIG. 4, (5) the judgment clock phase control signal output by the discrimination by CLK2 is the same as that in the case of FIG. Differently, the logic level can be "H". In this case, the determination clock phase control unit 1 uses the (6) determination clock phase control signal from the D-FF 111.
3 advances the clock phase by 1/4 time slot.

(7) C advanced by ¼ time slot
The LK3 identifies (4) the phase relationship detection pulse 1 in the D-FF 112. This identification result is DF
It is the output (8) of F112, and similarly, there is a period when the logic level becomes "H". Therefore, the output of the D-FF 111 is (6) the judgment clock phase control signal and the D-FF 1
12 output (8) EXOR output with the phase-related pulse 2 (9) EXOR is output from the EXOR circuit 121.

This (9) EXOR is identified by the (10) inverted data in the D-FF 122 of the phase relation determination result processing section 12. This result is the (11) identification data selection signal, and its logic level is "L", unlike the case of FIG.

(11) When the logical level of the identification data selection signal is "L", (3) the identification data is not adopted,
The identification data selection unit 3 is controlled so that the identification data from the other data identification / determination unit is output.

Here, the logic levels of the results identified by (5) CLK2 and (7) CLK3 are compared in the same manner as described with reference to FIGS. In the case of FIG. 4, A =
“L” and B = “H”, and in the case of FIG. 5, A =
“H” and B = “H”.

Therefore, when the logic levels of A and B are different, the rising phase of the identification clock has a relationship with which data can be correctly identified. On the other hand, when the logic levels of A and B are the same at "L" or "H", the rising phase of the identification clock is in the identification indetermination period at the front or the rear of the input data (1), and the data is correctly written. There is a relationship that cannot be identified.

In the embodiment of the present invention, the phase relation determination result processing unit 12 having the configuration shown in FIG. 4 determines the above relation and outputs the identification data of either the data identification / determination unit 1 or 2. I have to. Therefore, it is possible to adopt a configuration other than that shown in FIG. 1 by utilizing the above-mentioned logical level relationship.

FIG. 6 shows a second embodiment of the data discriminating circuit of the present invention. In FIG. 6, parts having the same configuration as in FIG. 1 will be indicated using the same reference numerals. 1 (2) is a data identification / determination unit, and 4 (2) is a second clock distribution unit. Reference numeral 5 is a data input unit, 6 is a clock signal input unit, and 7 (2) is an identification data output unit. Also, 8
Is a clock selection control unit.

The above-mentioned data identification / determination unit 1 (2) comprises a data identification unit 10, a phase relationship detection determination unit 11, a phase relationship determination result processing unit 12 (2), and a determination clock phase control unit 13. It

The data discriminating unit 10 is composed of a D-FF, and the phase relation detecting / judging unit is constituted by the phase relation detecting unit shown in FIG. 10 and two D-FFs 111 and 112. The result processing unit includes an inverting circuit 120 that inverts data with a predetermined delay, and the two DFs.
EXOR that takes the EXOR logic of the outputs of F111 and 112
The circuit 121 and the D-FF 122 are included.

Further, the clock selection control unit 8 uses the D-FF
It has an SR-FF 81 that operates by receiving the output of 122, an AND circuit 82 that ANDs the inverted data and the output of SR-FF 81, and a T-FF 83 that receives the output of the AND circuit and performs a toggle operation. Composed.

The configuration of FIG. 6 is characterized in that in the configuration of FIG. 1, two identification data are generated by two clocks of different phases in the two data identification / determination units, and the phase of the input data and the phase of the two clocks are generated. The identification data selecting section selects and outputs the identification data having the proper relationship, while the identification clock selection control section determines the proper phase relationship by determining the phase relationship between the clock and the data having two different phases. The point is to control so as to select the clock of and identify the data. Therefore, although the circuit is simplified in the configuration of FIG. 1, the configuration of FIG. 6 has an advantage that it can be further simplified.

As is clear from comparison between FIG. 6 and FIG. 1, the data identification / determination unit 1 (2) of FIG. 6 has almost the same configuration as the data identification / determination unit 1 of FIG. Since the operation of the embodiment of the present invention has been described in detail above,
The operation of the second embodiment of the present invention in FIG. 6 will be described while avoiding duplication as much as possible.

FIG. 7 is an operation time chart of the second embodiment of the present invention, which is an identification clock as in FIG. 4 (2).
It shows a case where the rising phase of CLK is in the definite period of the first half of the data. In this case, the operation from (1) to (10) in FIG. 7 is exactly the same as that in FIG.
(9) When the output identified by EXOR at the rising edge of inverted data (falling edge of data) is input to the SR-FF 81, the Q output of the SR-FF 81 is (11) the phase relation determination result is "L". Will be confirmed. Since the AND of the Q output of the SR-FF 81 and the inverted data is still “L”, the T-FF 83 does not toggle, and therefore, the clock switching control signal is not output to the clock distribution unit 4 (2). . That is, since the phases of the data and the identification clock are proper, the identification is continued with the current phase of the clock.

FIG. 8 is a time chart of the second embodiment of the present invention, and shows the case where the rising edge of the identification clock is in the indefinite period of the latter half of the data as in FIG. Also in this case, the process is the same as that in FIG. 5 until the D-FF 122 identifies (9) EXOR with (10) inverted data.
In this case, since the Q output of the D-FF 122 is "L", the (11) phase relation determination result which is the Q output of the SR-FF 81 is "H". Then, by ANDing the (11) phase relation determination result and (10) inverted data, (12)
Waveform is obtained and is input to the T-FF 83. As a result, the T-FF 83 toggles and outputs the "H" output to the clock distribution unit, and controls so as to select the identification clock having the proper phase.

Therefore, the identification clock is set at the rising timing with T1 added to the waveform of FIG. 8 (12).
CLK changes in 1/2 time slot phase. Accordingly, the second phase clock (5) CLK2
Then, (7) CLK3, which is a clock delayed by 1/4 time slot from the clock of the second phase, also changes the 1/2 time slot phase. After that, the operation shifts to the same operation as in FIG. 7, and the discrimination and the phase relation determination are performed. Then, as shown in FIG.
At the rising timing of T2 added to the waveform of (0), (11) Since the phase relation determination result falls to "L", AND
The output (12) of the circuit 82 continues to be "L", and TF
The output of F83 remains in the state of being controlled so as to select the discrimination clock having the proper phase.

In the above description, the phase relationship between the identification clocks of the first phase in the first data identification / determination units 1 and 2 of the embodiment of the present invention and the second embodiment of the present invention. The phase relationship between the first clock and the second clock in (1) is typically a phase difference of ½ time slot, but the phase relationship is not specifically described. Therefore, consideration will be given here with reference to FIG.

In the configuration of FIG. 1 or 6, the data identification section 1
The rate of data input to 0 depends on the phase relationship of the identification clock to the data. For example, as shown in FIG. 9, assuming that one time slot (clock cycle) is T and the phase difference between two clocks with respect to input data is Δtc, it is impossible to identify due to the above-mentioned jitter and setup / hold time. At least one of the two clocks must be out of the indetermination period, where tu is the time length of the region. That is, tu ≦ Δtc is required because the rising edges of the two clocks do not enter the same uncertain period, and tu ≦ T because the rising edges of the two clocks do not simultaneously enter the uncertain period before and after the data. -Δtc is required.

Therefore, from these two expressions, the condition that tu ≦ Δtc ≦ T−Δtu for Δtc is obtained.

Since the highest data rate is determined by the condition that gives the smallest T, 2tu ≦ Δtc + tu ≦ T, so that T becomes the smallest when tu = Δtc, and is given twice the uncertain period.

That is, when the present invention is applied to the identification of a signal as fast as possible, the above-mentioned unidentifiable area is 1
Assuming less than 1/2 of time slot,
A relative phase difference between the identification clocks input to the data identification units 10, 10 (2) in the first data identification / determination unit 1 and the second data identification / determination unit 2 in the embodiment of the present invention; The condition is that the phase difference between the first clock and the second clock in the second embodiment of the present invention is at least 1/2 time slot or more with respect to the maximum bit rate of the data to be identified. For example, 622Mb
1/622 (M
It is necessary to have a phase difference of only b / s) × 1/2 = 804 ps.

In addition, in FIG. 4 or FIG. 7, the (2) CLK which is the identification clock and the (5) CLK2 which is the second phase clock which identifies the (4) phase related pulse 1 by the D-F / F 111. As for the phase relationship of (1), the phase difference between the rising edge of CLK and the change point of (1) data is
The phase relationship between (2) CLK and (5) CLK2 is a criterion for determining whether or not the phase relationship is greater.

Therefore, as shown in FIG. 1, in this configuration having two systems of the same configuration, the two systems operate symmetrically with each other, and in the configuration of FIG. 6, the two clocks operate symmetrically with each other. So (2) CLK and (5) CL
The phase relationship with K2 is (1) set to be different by at least 1/2 time slot with respect to the maximum bit rate of the data to be identified when viewed as the relative relationship of the phase to the change point of the data. Is.

In this case, the D-F / F 112 is the third phase clock for identifying the phase-related pulse 1 (7) CL
K3 is (5) identification based on CLK2, and (2) CLK determines whether it is in the first half or the second half of one time slot of (1) data.

Therefore, as described above, in order to more finely determine the phase relationship in the first half or the second half, (5) identification by CLK2, that is, DF / F111
The determination clock phase control unit 13 changes the phase in accordance with the identification result of 1. and the phase-related pulse 1 is identified by the D-F / F 112.

In this case, the phase of the clock that changes according to the identification result of the D-F / F 111 is as follows: (1) When viewed as a relative relationship of the phase to the change point of the data, By setting at least 1/2 time slot different from the highest bit rate of the data to be identified, the clocks of the two phases can be operated symmetrically.

Further, depending on the identification in the D-F / F 111, (2) CLK which is the identification clock of the first phase
Is (1) for one time slot of data, it is determined whether it is in the first half or the second half. Similarly, in the identification in the DF / F 112, the first half or the second half of the time slot is identified. The phase relationship between the identification clock and the data in the
Judgment will be made on the basis of the difference in the phase relationship with respect to the change point of data between the clock input to / F112.

Therefore, (5) CLK2 and D-F / F1 which are the clocks of the second phase input to the D-F / F111.
(7) CL which is the third phase clock input to 12
The difference in the phase relationship with respect to the change point of the data with respect to K3 is at least another 1/2 of the 1/2 time slot with respect to the maximum bit rate of the data to be identified, that is, 1
If the / 4 time slots are set differently, the clocks of the two phases act symmetrically with respect to the identification in the DF / F 112, so that the highest design bit rate can be achieved.

The clock distribution unit 4 in the embodiment of the present invention and the clock distribution in the second embodiment of the present invention which generate a plurality of clocks having a predetermined phase difference as described above. Various circuits are conceivable as the circuit forming the unit 4 (2).

In the embodiment of the present invention, for example, FIG.
In No. 1, the clock distribution unit 4 has a clock input buffer 41, a clock buffer 42, and an inverter 43. Utilizing the fact that the signals output from the clock buffer 42 and the inverter 43 are in an inverse relationship to each other, the first data identification determination unit is used as an identification clock having a phase difference of 1/2 time slot. The first and second data identification / determination units 2 are configured to be input to the data identification unit 10 and the first data / clock phase relationship determination unit D-F / F111.

Further, in the configuration shown in FIG. 12 (1), instead of using the inverter 43, the first data identification / determination unit 1 and the second data identification / determination unit 2 are configured to have the delay means 44. Data identification 10, 10 (2)
And a first data / clock phase relationship determination unit D-
The phase difference between the clocks input to the F / F 111 is given by the delay time corresponding to the delay means 44.

Further, in the configuration shown in FIG. 12B, the first data identification / determination unit 1 and the second data identification / determination unit 2 are included.
Data identification section 10, 10 (2) and DF / F in
The drive circuit for the clock input to 111 has a delay means 44 and inverters 46 and 47 so that they are symmetrical to each other. The phase relationship between the clocks input to the data identifying units 10 and 10 (2) is delayed by the delay unit 44, and the data identifying unit 10 and the first data / clock phase relationship determining unit D.
The mutual relationships of the clocks input to the -F / F 111 are given by the inverters 46 and 47, respectively.

The second embodiment of the present invention is basically the same as the above, but is different in that the function of outputting the identification clocks of different phases according to the output of the identification clock selection control section is required. ing.

The structure shown in FIG. 13A corresponds to the structure shown in FIG. 11 and includes buffer gates 41 and 42 and an implanter 43.
In addition to this, it has an identification clock phase control unit 48. Then, the output of the identification clock phase control unit 48 that controls the phase of the identification clock is branched by the output of the identification clock selection control unit, the output of the buffer gate 41 is supplied to the data identification unit 10, and the output of the inverter 43 is output to the D-FF 111. Supply to.

The configuration shown in FIG. 13B is the same as that shown in FIG.
Corresponding to the above configuration, instead of using the inverter 43, the delay unit 44 is provided to realize the same function as described above.

Here, as the delay means 44 shown in FIGS. 12 and 13, either a logical gate element or a fixed or variable delay element (passive element) is used. When it is realized by a logical gate element, for example, an MB-810 series OR-NOR gate element manufactured by Fujitsu can be used. About 400 when using this element
A delay amount of ps is obtained, which is optimum for the signal speed of 622 Mb / s mentioned above.

A circuit shown in FIG. 14 can be considered as a circuit constituting the identification clock phase control section in FIG. FIG. 14 (1) shows an example of an EXOR circuit, and FIG. 14 (2) shows an example of an OR-NOR circuit and a selector or multiplexer. Here, FIG.
To explain as applied to (1), FIG. 14 (1)
Applies the output of the buffer gate 41 to one input terminal of the EXOR circuit 481 and the output of the identification clock phase selection control unit to the other input terminal. If the output of the identification clock phase selection control unit is “L”, the phase of the output of the puffer gate 41 is output as it is from the EXOR circuit,
If it is "H", the phase of the output of the buffer gate 41 is inverted and output.

In FIG. 14 (2), the OR-NOR circuit 482 generates an output in phase with the output of the buffer gate 41 and an output in anti-phase, and the selector or multiplexer 48.
In 3, the two outputs are selected and output by the output of the identification clock phase selection control section.

Next, in the first data identification / determination unit 1 and the second data identification / determination unit 2 in the embodiment of the present invention, the third data input to the second data / clock phase relation determination unit 112 is input. The configuration of FIG. 15 and FIG. 16 can be adopted as the determination clock phase control unit 13 that controls the phase of the determination clock that is the phase clock based on the determination result in the first data / clock phase relationship determination unit 111.

In the configuration shown in FIG. 15A, the delay means 1
30 and 130 (2), a clock phase input to the second phase relationship determining unit 112 is given a predetermined phase difference with respect to a clock input to the first phase relationship determining unit 111. As shown in 15 (2), the inverters 132 are made to have mutually inverted phases and are different by 1/2 time slot.

Then, EXOR is performed according to the determination result ("L" or "H") in the first phase relation determining unit 111.
The gates 131 and 131 (2) control whether or not to invert the polarity of the clock input to each.

In the configuration shown in FIG. 16, instead of the EXOR gate, a multiplexer or selector 135,
135 (2) and delay means 133 and 133 (2)
Then, two kinds of clocks each having a predetermined phase set are selected and output according to the determination result (“L” or “H”) in the first phase relation determination unit 111.

As the decision clock phase controller in the second embodiment of the present invention, the circuit having the configuration shown in FIG. 17 can be adopted. In the configuration shown in FIG. 17 (1), the data identification unit 1
0 and the second data / clock phase relationship determination section 112 has a delay means 130 corresponding to the phase difference between the clocks input to the respective sections, and the EXOR circuit 131 outputs the determination result of the first data / clock phase relationship determination section 111. Applied to one of the input terminals to switch the phase of the clock input to the second data / clock phase determination unit.

In the configuration shown in FIG. 17 (2), according to the phase difference between the two types of clocks input to the data identification section 10,
The first data / clock phase relationship determination unit 111 is selected from the output of the delay unit 130 and the output delayed by the delay unit 136 according to the phase difference between the two types of identification clocks input to the data identification unit. The determination result in (1) is input to the selector or multiplexer 137 to select one of the clocks.

Further, in the configuration shown in FIG. 17C, the determination result of the first data / clock phase relation determining section 111 is determined from the output of the delay means 130 and the output obtained by inverting the output by the inverter 138. Is input to the selector or multiplexer 137 to select either clock.

Here, the delay means 130, 130 (2), 133, 133 (2) and 136 shown in FIGS. 15 to 17 are logical gate elements similar to those described in FIGS. 12 and 13. Alternatively, it can be configured by using either a fixed or variable delay element (passive element).

In the above description, all logic processing is used. Further, since the determination is made only when the data “1” exists, it is not necessary to consider a countermeasure when the data “0” is mistaken as “1”.

In the embodiment of the present invention described above,
According to the principle of the present invention, an identification circuit that selectively outputs data identified by a clock having an appropriate phase can be realized. However, in a logic circuit used in an actual receiver or the like, for example, in a frame synchronization circuit, a frame is A sync protection circuit is provided for detection. Therefore, also in the data identification circuit according to the present invention, a synchronization protection circuit may be provided as in the case.

FIG. 18 is a conceptual diagram in which the synchronization protection circuit 32 is provided in the identification data selection unit 3 in the embodiment of the present invention. Here, as the synchronization protection circuit, a circuit using a shift register is usually used, and the identification data of the clock of the phase determined to be appropriate is continuously output a predetermined number of times.

However, high-speed signal identification processing, or
Considering that it is necessary to take into consideration the case where the determination is not determined a predetermined number of times consecutively due to variations and instability of the internal circuit, the configuration shown in FIG. 19 is preferable. That is, a counter is used for the synchronization protection circuit, and the identification data of the system that is judged to be appropriate a predetermined number of times is selected even if the counter is not continuous.

In the configuration shown in FIG. 19, two systems of synchronization protection circuits 320, 320 (2) correspond to the configuration shown in FIG.
Is shown. Here, D-F / F 122 and 122
Corresponding to (2), the synchronization protection circuits 320 and 32 are provided.
0 (2), each having counters 325, 326.

The two counters 325 and 326 count the contradictory data of the D-F / F 122 and 122 (2), respectively. This not only determines that it is appropriate,
It also counts the determination results that are improper. If the result is incorrect for a predetermined number of times, the NOR gate 327, the OR gate 329, and the OR / NOR gate 3 are set so as to output the data identified by the clocks of the opposite phases.
It is controlled by the identification data selection signal processing section 330 constituted by 28. As a result, the discrimination phase is always fixed for a data length less than a certain number.

Further, four counters 325, 326, 325 (2), 326 in total, two in each of the two systems.
When the Q output of any one of (2) becomes "H", the output of the AND gate 331 becomes "L", and the AND gate 3 stops the pulse input to the counter.
21, 322, 323. As a result, the once stabilized phase is maintained as it is.

The configuration shown in FIG. 20 is the same as the configuration shown in FIG. 6 except that a synchronization protection circuit 84 is provided in the identification clock selection control unit corresponding to the D-FF 122. Basically, the configuration shown in FIG. Is the same. The synchronization protection circuit 84 has counters 844 and 845. These two counters count not only the determination that they are proper but also the determination that they are incorrect by counting the contradictory outputs of the D-FF 122, and if the result that they are incorrect for a predetermined number of times is output. In order to select the identification clock of the opposite phase, the inverter 846 and the OR-NOR circuit 847 are combined to obtain the selection signal of the clock phase with the polarity of the signal input to the SR-FF 81. With this configuration, the identification phase can be definitely determined for a data length of a certain number or less. Further, when the Q output of either one of the two counters becomes "H", the output of the AND gate 848 becomes "L", and the pulse input to the counter is stopped.
The phase of the identification clock once determined to be proper is held.

As described above, in the data identification circuit portion of the receiver, only the logic circuit is formed,
A data discriminating circuit is realized which realizes a function of discriminating data by using two kinds of clocks which are in a mutually inverted relation and outputting the data discriminated by either one of the clocks which is more appropriate.

FIG. 21 is a block diagram of an embodiment in which the embodiment of the present invention is applied to an optical receiver, and shows a block structure of the optical receiver. In the figure, the same parts as those in FIG. 1 are indicated by the same numbers. Therefore, the first and second data identification / determination units 1 and 2 operate in the same manner as the configuration of the identification data selection processing unit, the identification data output unit 3 and the clock distribution unit 4 described in FIG.

The difference from FIG. 1 is that the photodiode (P
D) 8, the equalizing amplifier 9, and the clock extracting unit 61. The optical signal input to the PD 8 is converted into an electric signal and amplified by the equalizing amplifier 9 to a level that can be identified. The output of the equalizing amplifier 9 is input from the data input unit 5 to the data identification units 10 and 10 (2), and at the same time, to the clock extraction unit 61, which is a timing circuit, the clock is extracted, and the clock input unit 6 identifies the output. Input to the department.

The data and clock input from the data input section 5 and the clock input section 6 are based on the above-mentioned principle.
The identification data selected by the appropriate clock phase is output from the identification data selection unit 3.

It should be noted that in the embodiment of FIG.
It is, of course, possible to add a synchronization protection circuit similar to that described with reference to FIG. It is also possible to arrange a plurality of optical receivers shown in FIG. 21 in parallel to configure a parallel optical receiver that receives optical signals input in parallel from a plurality of transmission lines.

In that case, the timing circuit may be associated with at least one receiving circuit. In some cases, separate clock line transmission may be performed in which the clock is transmitted in parallel with the data through another optical transmission line.

When it is necessary to further align the bit phases of parallel data, as shown in FIG. 22, the D-FF arranged corresponding to the channel output in the bit synchronizing section 14 is driven by the clock from the common clock generating section 15. Bit synchronization is performed by using. In FIG. 22, R1, R2 ...
Rn is n parallel receivers arranged in parallel.

Alternatively, only the data identified by one of the clocks may be identified by the inverted clock to realize the processing for aligning the bit phases.
In addition, depending on the system configuration, there may be a system clock that is completely different and that is input from the clock input unit 5.

The above is an example in which the embodiment of the present invention is applied to an optical receiver and an optical parallel receiver. However, the second embodiment of the present invention similarly applies to the optical receiver and the optical parallel receiver. It goes without saying that it can be applied.

[0133]

As described above, according to the present invention,
In the receiver that constitutes the digital signal transmission system, the data identification circuit that identifies the signal can be configured by only the logic circuit. This makes it possible to provide a low-cost data identification circuit using a gate array or the like and an optical receiver having a simple configuration using the identification circuit. For example, a circuit configuration in a short-distance optical transmission system such as an optical subscriber system. It greatly contributes to the realization of a simple optical receiver.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram (part 1) of the operation principle of the present invention.

FIG. 3 is an explanatory view (No. 2) of the operation principle of the present invention.

FIG. 4 is an operation time chart (No. 1) of the embodiment of the present invention.

FIG. 5 is an operation time chart (No. 2) of the embodiment of the present invention.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is an operation time chart (No. 1) of the second embodiment of the present invention.

FIG. 8 is an operation time chart (No. 2) of the second embodiment of the present invention.

FIG. 9 is a relationship diagram between an identification clock (CLK) phase and input data.

FIG. 10 is an example of a data / CLK phase relationship detection unit.

FIG. 11 is an embodiment (No. 1) of the clock distribution unit in the embodiment of the present invention.

FIG. 12 is an embodiment (No. 2) of the clock distribution unit in the embodiment of the present invention.

FIG. 13 is an embodiment of a clock distribution unit in the second embodiment of the present invention.

FIG. 14 is an embodiment of an identification clock phase controller in the second embodiment of the present invention.

FIG. 15 is an embodiment (No. 1) of the determination clock phase control unit in the embodiment of the present invention.

FIG. 16 is an embodiment (No. 2) of the determination clock phase controller in the embodiment of the present invention.

FIG. 17 is an embodiment of a decision clock phase controller in the second embodiment of the present invention.

FIG. 18 is an embodiment using a synchronization protection circuit in the embodiment of the present invention.

FIG. 19 is an example of a synchronization protection circuit.

FIG. 20 is a second example of the synchronization protection circuit.

FIG. 21 is a block diagram of an embodiment in which the present invention is applied to an optical receiver.

FIG. 22 is a configuration example of a parallel receiver.

FIG. 23 is a conventional example.

[Explanation of symbols]

 1 First data identification / determination unit 2 Second data identification / determination unit 3 Identification data selection unit 4 Clock distribution unit 5 Data input unit 6 Clock (CLK) input unit 10 Data identification unit 11 Data / clock phase relation detection determination Part 12 Phase relationship judgment result processing part 13 Judgment clock phase control part

Claims (34)

[Claims] 1. A clock distribution unit (4) for generating first and second clock signals having different phases, and the first and second clock signals respectively inputted from the clock distribution unit (4), First and second data identification / determination units (1, 2) to which input data is commonly input from the data input unit (5), and the first data identification / determination unit (1) based on the first clock signal. 1) the first identification data identified in 1), the first identification determination result generated based on the phase relationship between the input data and the first clock signal, and the second data identification by the second clock signal / The second identification determination result generated based on the second identification data identified by the determination unit (2) and the phase relationship between the input data and the second clock signal is input, and the first and second identification data are input. Based on the identification judgment result, Data identification circuit, characterized in that the having identification data selection unit for selecting and outputting one of the identification data or said second identification data (3). 2. A second clock distribution unit (4 (2)) for generating first and second clock signals having different phases, and the second clock distribution unit (4 (2)) for generating the first clock signal. Of the third data identification / determination unit (1) to which the clock signal of (1) is input and the input data is input from the data input unit (5).
(2)), based on the identification data identified by the third data identification / determination unit (1 (2)) by the first clock signal and the phase relationship between the input data and the first clock signal. An identification clock selection control section (8) for inputting the generated identification determination result and outputting a signal for selecting either the first clock signal or the second clock signal based on the identification determination result. A data identification circuit characterized by the above. 3. The clock distribution unit (4) according to claim 1, wherein each of the first and second data identification / determination units (1, 2) receives input data input from the data input unit (5). From the data identifying unit (10) for identifying using the clock input from (1), and the phase relationship between the data identified by the data identifying unit (10) and the input data from the data input unit, From the data / clock phase relationship detection determination section (11), which detects and determines the phase relationship with the clock, the phase relationship detection determination result output by the data / clock phase relationship detection determination section (11), and the input data. And a phase relation determination result processing section (12) for generating a selection control signal for the identification data selection section (3). 4. The third data identification / determination unit (1 (2)) according to claim 2, wherein the input data input from the data input unit (5) is input to the second clock distribution unit (4 (4). 2)) using the clock input from the data identification unit, and the phase relationship between the data identified by the data identification unit (10) and the input data, the input data and the clock are identified. The data / clock phase relationship detection / determination unit (11), and the identification based on the detection result of the phase relationship output by the data / clock phase relationship detection / determination unit (11) and the input data. A data discrimination circuit, comprising: a phase relation determination result processing unit (12) for outputting a signal for generating an identification clock selection control signal in the clock selection control unit (8). 5. The data / clock phase relationship detection determination unit (11) according to claim 3, wherein the data / clock phase relationship detection determination unit (110) and the first and second phase relationship determination units (111, 112), the data / clock phase relationship detection unit (110) generates a pulse width corresponding to a phase difference between the data identified by the data identification unit (10) and the input data, In one data / clock phase relationship determination unit (111),
Based on the result of determining the phase relationship between the input data and the clock from the pulse width, the phase of the clock input to the second data / clock phase relationship determining unit (112) is controlled. Characteristic data identification circuit. 6. The data identifying section (10) and the first and second data clock phase relationship determining sections (111, 112) according to claim 3 to 5, wherein
A data discriminating circuit comprising F. 7. The inverter according to claim 3, wherein the phase relation determination result processing unit (12) inverts a signal obtained by delaying input data by a predetermined delay.
0) and the outputs of the first and second data / clock phase relationship determination units (111, 112)
A circuit (121) and the EXOR circuit (12
The output of 1) is input, and the inverter (1
20) The D-FF (122) to which the output of 20) is input. 8. The multiplexer or selector (30) according to claim 3, wherein the identification data selection unit (3) receives the outputs of the first and second data identification / determination units (1, 2), and SR-FF (31)
And an output of the first data identification / determination unit (1) is connected to the S-input terminal of the SR-FF (31).
At the R input terminal of F (31), the second data identification /
The output of the judging section (2) is inputted, and the SR-FF (31) is inputted.
Depending on the output of the multiplexer or selector (30)
The data identification circuit is configured to control and output the output of the first data identification / determination unit (1) or the second data identification / determination unit (2). 9. The identification clock selection control unit (8) according to claim 4,
The R terminal is connected to the positive phase output terminal of (122), and the DF
SR-in which the S terminal is connected to the negative phase output terminal of F (122)
An FF (81), an AND circuit (82) to which the output of the SR-FF (81) and the output of the inverter (120) are input, and an output of the AND circuit (82) to the C terminal. A data identification circuit having a T-FF. 10. The phase difference between the first and second clocks input to the first and second data identification / judgment units (1, 2) differs from each other by at least ½ time slot. A data identification circuit characterized in that. 11. The first, second and third data identification / determination units according to claim 1, 2, or 3.
2, 1 (2)) the first phase clock input to the data identification section (10) and the second input to the D-FF (111) in the data / clock phase relationship detection and determination section (11). The phase difference of the clocks of the phase of at least ½ time slot is different, and D in the data / clock phase relationship detection / judgment unit (11)
-The clock of the third phase input to the FF (112) is
First and second clocks having two types of clocks different from each other by at least ½ time slot and selectively outputting one of the two types of clocks according to the identification result of the D-FF (111). In the second data identification / determination unit (1, 2), the first determination clock phase control unit (13, 13)
(2)) and the second determination clock phase control section (13 (3)) in the third data identification / determination section (1 (2)).
A data identification circuit having: 12. The first, second and third data identification / determination unit (1,
2, 1 (2)), the phase difference between the clocks input to the D-FF (111) and the D-FF (112) with respect to the input data is set to differ from each other by ¼ time slot, and Judgment clock phase controller (1
3, 13 (2), 13 (3)), the D-FF
According to the identification result of (111), the D-FF (112)
A data identification circuit characterized in that the phase of a clock input to the control circuit is controlled so as to be delayed or advanced by ¼ time slot. 13. The clock distribution unit (4) according to claim 1, comprising at least one input buffer (41) for inputting a clock from a clock input unit (6) and an inverter (43). Clocks inverted from each other are input to the data identification unit (10) of the first and second data identification / determination units (1, 2) and the first data / clock phase relationship determination unit (111). A data identification circuit characterized by comprising. 14. The clock distribution unit (4) according to claim 1, wherein at least one input buffer (41) for inputting a clock from the clock input unit (6), a clock buffer (42), and a delay unit (4).
4) and a clock buffer (45) corresponding to the delay clock output from the delay means (44), and the data identification section (10) of the first and second data identification / determination sections (1, 2). ) And the first data / clock phase relationship determination unit (111), the phase difference between the clocks corresponds to the delay time in the delay means (44). circuit. 15. The clock distribution unit (4) according to claim 1, wherein at least one input buffer (41) for inputting a clock from the clock input unit (6), a clock buffer (42), and a delay unit (4).
4) has a clock buffer (45) and inverters (46, 47) corresponding to the delayed clock output from the delay means (44), and includes the first and second data identification / determination units (1, 2) ) Data discriminating unit (10) and the first data / clock phase relation judging unit (111), the phase difference between the respective clocks corresponds to the delay time in the delay means (44), and Clocks inverted from each other are input to the data identification unit (10) of the first and second data identification / determination units (1, 2) and the first data / clock phase relationship determination unit (111). A data identification circuit characterized by being configured. 16. The clock distribution unit (4 (2)) according to claim 2, wherein at least one input buffer (41) for inputting a clock from the clock input unit (6), and the input buffer (41). An identification clock phase control unit (48) for controlling the output phase by a predetermined amount according to the output of the identification clock selection processing unit, and a buffer gate (42) connected to the output terminal of the identification clock phase control unit (48). An inverter (43), the data identification unit (10), and the D-FF (111).
A data identification circuit, characterized in that it is configured to supply clocks of opposite phases to and. 17. The clock distribution unit (4 (2)) according to claim 2, wherein at least one input buffer (41) for inputting a clock from the clock input unit (6) and the input buffer (41). An identification clock phase control unit (48) that controls the output phase by a predetermined amount according to the output of the identification clock selection processing unit (8), and a buffer gate (42) connected to the output terminal of the identification clock phase control unit (48). ), A delay means (44) and a buffer gate (45), the data identification section (10) and the D-FF (111).
A data identification circuit, characterized in that it is configured to supply clocks of opposite phases to and. 18. The data identification circuit according to claim 14, wherein the delay means (44) is composed of a semiconductor gate element or a delay element having a fixed or variable delay amount. 19. The identification clock phase control unit (48) according to claim 16, further comprising an EXOR circuit (481), wherein the output of the identification clock selection processing unit (8) is the EXOR circuit.
Applied to one input terminal of the circuit (481),
A data identification circuit, characterized in that it is configured to input a clock to the other input terminal of the circuit (481). 20. The identification clock phase controller (48) according to claim 16 or 17, and an OR-NOR circuit (482) which receives a clock, and the OR-NO.
A multiplexer or a selector (48) which receives two outputs of the R circuit (482) and selects one of the two inputs by the output of the identification clock selection processing unit (8).
3) A data discriminating circuit having: 21. The determination clock phase control unit (13, 13 (2)) of the first and second data identification / determination units (1, 2) according to claim 11, wherein the clock input unit (6). A buffer (40) to which a clock from is input, first and second delay means (130, 130 (2)) to which an output of the buffer (40) is input, and the first to one input terminal, respectively. And second delay means (13
0, 130 (2)) are input to the first and second EXOR circuits (131, 131 (2)), and the first phase relation determination unit (111, 111 (2)) A data discrimination circuit, characterized in that the determination result is inputted to the other input terminals of the corresponding first and second EXOR circuits (131, 131 (2)). 22. The clock phase control section (13, 13 (2)) of the first and second data identification / determination sections (1, 2) according to claim 11, further comprising a clock input section (6). (40) to which the clock of (1) is input, delay means (44) to which the output of the buffer (40) is input, an inverter (132) to which the output of the delay means (44) is input, and one input each. First and second EXOR circuits (131, 131) to which the outputs of the inverter (132) and the delay means (44) are input at the ends.
(2)), and the first phase relationship determination unit (111,
111 (2)) is inputted to the other input terminal of the corresponding first and second EXOR circuits (131, 131 (2)). 23. The determination clock phase control section (13, 13 (2)) of the first and second data identification / determination sections (1, 2) according to claim 11, wherein: (40) to which the clock from is input, first and second delay means (133, 133 (2)) to which the output of the buffer (40) is input, and the first and second delay means ( 133 and 133 (2) output is input to the first and second clock buffers (13
4, 134 (2)) and first and second multiplexers or selectors (135, 1) to which outputs of the first and second clock buffers (134, 134 (2)) are input.
35 (2)), and the first phase relationship determination unit (11
1, 111 (2)) corresponds to the first and second multiplexers or selectors (135, 135)
(2)), and the first and second clock buffers (134, 134) corresponding to the respective judgment results.
A data identification circuit characterized in that the output of (2)) is selectively output. 24. The clock from the clock input unit (6) according to claim 11, wherein the determination clock phase control unit (13 (3)) of the third data identification / determination unit (1 (2)) receives the clock from the clock input unit (6). The input buffer (40),
Delay means (13) to which the output of the buffer (40) is input
0), the output of the delay means has an EXOR circuit (131) input to one input terminal, and the other input terminal of the EXOR circuit has a determination result of the first phase relation determination unit (111). Is input, and the phase of the clock supplied to the second phase relationship determination section (112) is controlled by the output of the first phase relationship determination section (111). Identification circuit. 25. The determination clock phase control unit (13 (3)) of the third data identification / determination unit (1 (2)) according to claim 11, wherein the clock from the clock input unit (6) is used. The input buffer (40),
Delay means (13) to which the output of the buffer (40) is input
0), the output of the delay means (130) is input to one input terminal, and the output of the delay means (136) that delays the output of the delay means (130) by a predetermined amount is input to the other input terminal. A multiplexer or a selector (137) is provided, and by the output of the first phase relation determination unit (111),
A data identification circuit, characterized in that it is configured to select one of the two inputs of the multiplexer or selector (137). 26. The determination clock phase control unit (13 (3)) of the third data identification / determination unit (1 (2)) according to claim 11, wherein the clock from the clock input unit (5) is used. The input buffer (40),
Delay means (13) to which the output of the buffer (40) is input
0), a multiplexer or a selector in which the output of the delay means (130) is input to one input terminal and the output of an inverter (138) that inverts the output of the delay means (130) is input to the other input terminal (137), and by the output of the first phase relationship determination unit (111),
A data identification circuit, characterized in that it is configured to select one of the two inputs of the multiplexer or selector (137). 27. The delay means (44, 103, 130 (2), 133,
Reference numeral 133 (2), 136) is a data identification circuit characterized by comprising a semiconductor gate element or a delay element having a fixed or variable delay amount. 28. The data / clock phase relation detecting section (110) according to claim 5, wherein the inverter (71) and the EXOR circuit (72), the NOR circuit (73), the inverter (71) and the AND circuit (7).
4) or a combination of an AND circuit (74), and one input terminal of the EXOR circuit (72) is connected to the NOR circuit (7) via the inverter (71).
3) The input data from the data input section (5) is directly input to one of the input terminals, and the other input terminal of the EXOR circuit (72) and the other input terminal of the NOR circuit (73) The reverse phase output of the identification data from the data identification section (10) is input to the inverter, and the input data from the data input section (5) is input to one of the input terminals of the AND circuit (74) by the inverter ( 71) or directly, and a positive phase output of the identification data from the data identification unit (10) is input to the other input terminal of the AND circuit (74). Data identification circuit. 29. The data / clock phase relationship detection unit (110) according to claim 5,
An XOR circuit (72) is provided, the input data from the data input unit (5) is input to one input terminal of the EXOR circuit (72), and the data identification unit is input to the other input terminal. The configuration is such that the reverse phase output of the identification data from (10) is input, and the force of the determination clock phase control section (13) is inverted and input to the first phase relationship determination section (111). Data identification circuit characterized by. 30. The synchronization protection circuit (3) according to claim 1, wherein the identification data selection unit (3) inputs an output from the phase relation determination result processing unit (12).
A data identification circuit comprising 2). 31. Data according to claim 2, wherein said identification clock selection control section (8) comprises a synchronization protection circuit (84) for receiving an output from said phase relation result processing section (12). Identification circuit. 32. The synchronization protection circuit (32) according to claim 29, further comprising a counter (320), the counter (320) counting the output of the phase relationship result processing section (12) at least a predetermined number of times. The data identification circuit is configured to selectively output the identification data from the corresponding first or second data identification / determination unit (1, 2) on the condition that the above has been done. 33. The synchronization protection circuit (84) according to claim 30, wherein counters (844, 84) are provided.
5), the counters (844, 845) count the positive phase output and the negative phase output of the D-FF (122) of the phase relationship result processing unit (12), and the counter (844) of the counter (844). OR-NOR to the positive phase output via the inverter (846)
Connect one input terminal of the circuit (847), connect the other input terminal of the OR-NOR circuit to the positive phase output of the counter (845), and output the NOR side of the OR-NOR circuit (847). Is connected to the R terminal of the SR-FF (81), and the OR side output of the OR-NOR circuit (847) is connected to the S terminal.
The SR-F is connected to the S terminal of the R-FF (81) and has been counted at least a predetermined number of times.
A data discriminating circuit configured to output a control signal for selecting a discriminating clock from F (81). 34. An optical signal receiving section (8), an equalizing amplifier (9) for amplifying a received signal converted into an electric signal from the optical signal receiving section (8) to a predetermined level, a timing extraction circuit (61). And the data identification circuit according to claim 1 or 2, wherein the output of the equalization amplifier (9) is used as a data input of the data identification circuit, and the output of the timing extraction circuit (61) is provided to the data identification circuit. An optical receiver having a configuration for clock input.