JPH05110514A - Optical receiver circuit - Google Patents

Abstract

PURPOSE:To reduce the increase of parts caused by phase adjustment. CONSTITUTION:The input signal of an identification circuit 7 and a clock signal outputted from a selective circuit 5 in accordance with a phase difference quantity of the clock signal are switched to an opposite phase and in accordance therewith, the combination of phases of three kinds of clock signal lines outputted from a limiter circuit 6 is governed. The output signal of the limiter circuit 6 is all inverted simultaneously when the phase of the clock signal supplied thereto is inverted, therefore, the phase correction of two kinds of signal lines is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical receiver circuit, and more particularly to an optical receiver circuit for adjusting the phase of an identification circuit and the phase of an output logic signal / output clock signal.

[0002]

2. Description of the Related Art In a conventional circuit, as shown in FIG. 2, a received optical signal is branched and output as an EQ1 and an EQ2 through an optical / electrical conversion circuit 1 and an equalizing / amplifying circuit 2.
The equalized signal EQ1 is input to the identification circuit 7 and is equalized.
2 is input to the clock extraction circuit 4 via the delay line 3.

The clock extraction signal S extracted by the clock extraction circuit 4 is input to a limiter circuit 6, where rectangular wave clock signals CLK1 and CLK3 having the same phase and rectangular wave clock signals CLK2 and CLK4 having the opposite phase are inputted. Made The rectangular wave CLK1 is selected by the signal selection circuit 5 that selects either CLK2, and the selected clock signal CSL is selected.
Is input to the identification circuit 7 at the timing of
Identify.

The delay line 3 and the selection circuit 7 adjust the phases of the equalized signal EQ1 and the clock signal CSL so that the timing of identification becomes the optimal identification point. When the delay time of the delay line 3 does not satisfy one cycle of the clock signal, it is possible to increase the range of phase adjustment by selecting the clock signals having opposite phases by the selection circuit.

The identification circuit 7 outputs a positive logic signal DATA and a negative logic signal DATB in response to the equalization signal EQ1.

The output clock CLK3 of the limiter circuit 6
Each of CLK4 is delayed so that the output clock signals CKP and CKN have one of the phase relationships shown in FIG. 3 or FIG. 4 with respect to the logic signals DATA and DATB regardless of the phase adjustment of the identification point of the identification circuit 7. The delay time of lines 8 to 11 was adjusted.

[0007]

In the conventional method, when the delay time of the delay line does not satisfy one cycle of the clock signal, it is necessary to select the normal / inversion of the clock signal by the selection circuit. With clock CLK3, CLK
Since it is necessary to invert the phase of 4 as well, the delay lines 8 to 11 must be selected according to the phase of the logic signal output selected by the selection circuit 5 and the delay line 3, and the phase of the output clock signal Adjustment requires multiple delay lines, increasing cost and mounting area. Moreover, the man-hour for adjusting the phase by the delay line is also required.

The present invention has been made in view of such a situation, and reduces the increase in the number of parts due to the phase adjustment.

[0009]

In order to solve such a problem, the present invention provides an optical / electrical signal conversion circuit for converting light into an electric signal, and a delay line for delaying the signal converted into the electric signal. , A clock extraction circuit for extracting a clock extraction signal from the delay line output signal, a selection circuit for generating signals having mutually opposite phases from the clock extraction signal and selecting and outputting one of them, and a clock extraction signal output from the selection circuit The output of the optical / electrical conversion circuit from the limiter circuit that outputs first to third clock signals that are rectangular waves and opposite in phase to each other depending on the phase of the signal and their combinations change. And an identification circuit for

[0010]

The clock signal output from the selection circuit is switched to the opposite phase according to the phase difference amount between the input signal of the identification circuit and the clock signal, and the phases of the three types of clock signal lines output from the limiter circuit are correspondingly changed. The combination of is dominated.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The received optical signal is branched and output as equalized signals EQ1 and EQ2 via the optical / electrical conversion circuit 1 and the equalization amplifier circuit 2.

The equalized signal EQ1 is input to the discrimination circuit 7,
The equalized signal EQ2 passes through the delay line 3 and the clock extraction circuit 4
Is input to. The clock extraction signal S extracted by the clock signal extraction circuit 4 is output via the selection circuit 5,
One of the clock signals having opposite phases of the selection circuit 5 is selected and the signal is output, and the other is in the non-output state.

The limiter circuit 6 having a differential input circuit is
When the clock extraction signal S is input to the positive logic side, a rectangular wave clock signal CLK having the same phase as the clock extraction signal S
1, CLK2, a clock extraction signal S, and a clock signal CLK3 having an inverted phase. Conversely, when the clock extraction signal S is input to the negative logic side, a rectangular wave clock signal CLK3 having the same phase as the clock extraction signal S and a rectangular wave clock signal CLK having the opposite phase to the clock extraction signal S.
1 and CLK2 are output.

Equalized signal EQ1 input to the discrimination circuit 7
Are identified by the clock signal CLK1. Then, the equalized signal EQ whose identification timing is an optimum identification point
The delay line 3 and the selection circuit 5 adjust the phase between 1 and the clock signal CLK1.

When the delay time of the delay line 3 does not satisfy one cycle of the clock signal, the selection circuit 5 switches the signal input of the differential input section of the limiter circuit 6 to invert the phase of the clock signal CLK1 and adjust the phase. It is possible to increase the range of.

The discrimination circuit 7 outputs a positive logic signal DATA and a negative logic signal DATB in response to the equalization signal EQ1. The output clock signal CLK2 of the limiter circuit 6
In CLK3, the identification point of the identification circuit 7 is the clock signal CLK.
The output signals CKP and CKN are output in either of the phase relationships shown in FIG. 3 when identifying by the rising edge of 1 and by the phase relationships in FIG. 4 when identifying by the falling edge of the clock signal CLK1.

When the selection circuit 5 is thus inserted on the input side of the limiter circuit and the output of the selection circuit is supplied to the limiter circuit 6, the output signal phase of the limiter circuit 6 is entirely governed by the limiter circuit input signal. As described above, the output signal phase of the identification circuit 7 and the limiter circuit output do not become inconsistent each time the clock signal is selected by the selection signal, and the delay line required for the limiter circuit output for the conventional phase matching is unnecessary. become.

[0018]

The phase relationship between the output logic signal and the output clock signal is always constant regardless of the phase adjustment of the identification point of the identification circuit. Further, since the phase relationship is constant, the delay lines of a plurality of output clock signals, which were required in the conventional technology, can be reduced, and the cost and the mounting area can be reduced. Moreover, since the number of phase adjustment points is reduced, the number of adjustment steps required for phase adjustment can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional technique.

FIG. 3 is a diagram showing a phase relationship of output signals.

FIG. 4 is a diagram showing a phase relationship of output signals.

[Explanation of symbols]

 1 Optical / electrical conversion circuit 2 Equalization amplifier circuit 3 Delay line 4 Clock signal extraction circuit 5 Selection circuit 6 Limiter circuit 7 Identification circuit 8-11 Delay line EQ1 · EQ2 Equalization signal S Clock extraction signal CLK1-4 Clock signal DATA output Positive logic signal DATB output Negative logic signal CKP, CKN output clock signal

Claims (1)

[Claims] 1. An optical / electrical signal conversion circuit for converting light into an electric signal, a delay line for delaying the signal converted into the electric signal, and a clock extraction circuit for extracting a clock extraction signal from the delay line output signal. A selection circuit that generates signals having opposite phases from the clock extraction signal and selects and outputs one of the signals; and a signal that is a rectangular wave and has opposite phases depending on the phase of the clock extraction signal output from the selection circuit. And a limiter circuit that outputs first to third clock signals whose combinations change, and an identification circuit that identifies the output of the optical / electrical conversion circuit according to the timing of the first clock signal. Optical receiver circuit.