JPH06314968A - Counter read control method - Google Patents

Abstract

(57) [Summary] [Object] Regarding a read control method of a counter that can be read from a program, it is possible to directly read data directly from the counter 10 and to reduce the number of save registers. [Structure] A counter control means 13 for controlling the counting operation of the counter 10 is provided, and when it is detected that the reading operation of the counter 10 is completed, the counting operation is stopped until the reading operation is completed, and after the reading operation is completed, counter
Update 10

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter read control method for reading a counter value.

Generally, an information processing apparatus is provided with a counter accessible by a program in order to realize a function of generating an interrupt at every set time by setting a cycle, a function of counting a real time, and the like. There is. It is desirable that such a counter be capable of stable output and be configured with the smallest possible quantity.

[0003]

2. Description of the Related Art FIG. 6 is a block diagram of a general information processing apparatus, FIG. 7 is an explanatory view of problems in a read operation of a counter, and FIG. 8 is a configuration diagram of a conventional example.

As shown in a simplified form in FIG. 6, the information processing apparatus includes a central processing unit (CPU) 60, a main memory 61,
It is composed of a module 62 having a counter and other control registers accessible by a program operating on the CPU 60. These are the system bus 1
Combined at 2.

In FIG. 7, System CLK is a system clock signal, -AS is an access signal to the counter, ADDR is an address for reading the counter value, -ACK is a read response signal, and 16 MHz CLK is for counter control. The clock signal and DATA indicate the counter value.

Conventionally, the timer control module 62 shown in FIG. 6 is provided with the counter 10 and its read control circuit as shown in FIG. 8, for example. Counter 10
Performs a counting operation by the clock signal 16 MHz CLK or a count enable signal (not shown). In FIG. 8, 11 is an output selector, 12 is a system bus, 80
Is a register for saving the value of the counter 10 to read it, 81 is a decoder for decoding the address, 82 is an AND circuit, and 83 is a D-type flip-flop (D-FF) indicating that the counter 10 is being accessed. Numeral 84 indicates a D-type flip-flop for synchronization control, numeral 85 indicates a flag indicating whether a value is stored in the register 80, and numeral 86 indicates an AND circuit for outputting a write signal to the register 80.

In the prior art, the register 80 for saving the value of the counter 10 is required to stably read the data of the counter 10. The reason is as follows. When reading the value from the counter 10, FIG.
If the read value changes during the read operation, the data becomes uncertain, as indicated by point 1 of. Therefore, it is necessary to fix the value so that it does not change during the read operation. That is, unless fixed, the count value is updated during the read operation, and the element receiving the read data samples incorrect data. Conventionally, in order to solve the problem, at the time of reading, the value of the counter 10 is fetched into the register 80 and the register 8
The value of 0 is fixed and the value is read out.

[0008]

In the counter read control method according to the prior art, the value of the counter is temporarily saved in the register and the data is read from the saved register. Therefore, the register has the same number of bits as the counter length. There must be. Therefore, there is a drawback that the quantity becomes large and the cost becomes high.

[0009]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1A, 10 is a counter, which is directly accessed (read), 11 is an output selector which selects read data and sends it to the system bus,
12 is a system bus, 13 is a counter control means,
The update of the counter 10 is controlled. The counter control unit 13 suppresses the updating of the counter 10 during the read operation and controls the counter 10 to be updated only when the read operation is not performed.

In FIG. 1B, 10 to 12 are shown in FIG.
It corresponds to the one shown in (a). The counter control means 14 shown in FIG. 1B has an update count recording means 15. When the counter control means 14 detects that it is a read operation of the counter 10, it stops the counting operation of the counter 10 until the read operation is completed, and stores the number of times to be updated during that time by the update number recording means 15. And keep it. When the read operation is completed, the counting operation of the counter 10 is restarted and the count value recorded in the update number recording means 15 is controlled to be updated.

[0011]

According to the present invention, when the update signal of the counter is input during the reading of the counter 10, the update is suspended and the update is controlled after the read, so that the value of the counter 10 can be directly read. . As a result, it is not necessary to have a register for saving, and it is possible to reduce the amount of material.

[0012]

2 is a block diagram of the first embodiment of the present invention. The first embodiment corresponds to the invention shown in FIG. Reference numeral 20 is a decoder for decoding an address designating the counter 10, 21 is an AND circuit, 22 is a flag composed of a D-type flip-flop (D-FF) indicating that the counter 10 is being accessed, and 23 is a synchronous control. Is a D-type flip-flop, 24 is a D-type flip-flop for holding the update of the counter 10 during the read operation, 25 and 26 are AND circuits, and 27 is an OR circuit. The counter 10 is a 64-bit counter. Here, it is assumed that the counter 10 counts up every 16 μs.

A time chart of this circuit is shown in FIG.
2 and 3, System CLK is a system clock signal, -AS is an access signal to the counter 10, ADDR
Is the address for reading the value of counter 10, AS_Bu
f is a signal indicating that the counter 10 is being accessed,
AS_Sync is a synchronized signal indicating that the counter 10 is being accessed, En_Buf is a signal indicating that updating during access is pending, 16 MHz CLK is a clock signal for counter control, and Enable is the count of the counter 10. A signal for enabling the operation, Count Enable is a signal which is synchronized with the clock signal 16 MHz CLK in advance and is for updating the counter 10, Counter is the data state of the counter 10, System Bus is the system bus 12
In this state, the data read from the counter 10 is represented.

In this embodiment, the count enable signal is used.
The cycle of Count Enable needs to be longer than the read operation.
The time chart shown in FIG. 3 shows two accesses. The read access operation in the first half is when the access signal -AS and the count enable signal Count Enable do not overlap, and the read access operation in the second half is when the count enable occurs during the read operation.
In the former case, since the count operation does not affect the reading of the counter 10, the counter 10 is updated at the timing next to the count enable signal Count Enable.

In the latter case, when a count enable (Count Enable) occurs during the read operation, the AND circuit 27
Via the count-up hold flag (D-FF24)
Is set. Then, it waits for the end of the read access, and when the read access is completed, the AND circuit 27
The count-up timing is reconfigured by and the count-up is performed by the enable signal Enable of the counter 10. At the same time, the count-up hold flag (DF
Reset F24). That is, the update of the counter 10 is suspended for the time T shown in FIG. 3, and then the value of the counter 10 is corrected correctly.

In either case, a stable counter 10
Is output to the system bus 12 by the output enable of the output selector 11. In the first embodiment, the cycle of the count enable signal Count Enable needs to be longer than the read operation. If it is shorter than the read operation, the count timing may be lost and the count value may decrease. In the case of the second embodiment, by having means for recording the number of times of the count enable signal Count Enable during the read operation, the counter is collectively updated after the read operation by the number of times. By this,
Even if the cycle of the count enable signal Count Enable is shorter than the read operation, accurate counting is guaranteed.

FIG. 4 is a block diagram of the second embodiment of the present invention. The second embodiment corresponds to the invention shown in FIG. The other parts of the counter control means 14 are the same as in the first embodiment. Reference numerals 40 and 41 denote D-type flip-flops for recording the number of times the counter is updated during the read operation, 42 to 45 denote AND circuits, and 46 to 48 denote OR circuits.

A time chart of this circuit is shown in FIG.
Each signal is almost the same as that of the first embodiment, but the signal of En_Buf is divided into En_Buf1 and En_Buf2. When the access signal -AS to the counter 10 does not come, the counter 10 continues the counting operation by the count enable signal Count Enable.

For example, as shown in FIG. 5, when the access synchronization signal AS_Sync becomes "High" by the access signal -AS, the enable signal Enable for the counter 10 is "High" with respect to the count enable signal Count Enable.
Therefore, the update of the counter 10 is suspended. At this time, the D-FF 40 is set. Count enable (Count Enabl
When e) occurs, the update of the counter 10 is held pending and the D-FF 41 is also set. That is, the number of updates for two times is held. During this time, counter 1
Since the count operation of 0 is stopped, the data output from the counter 10 is stably performed.

When the read access is completed, the access synchronization signal AS_Sync becomes "Low", and the updating operation of the counter 10 is restarted. Especially after the read operation, D-FF
Enable signal En for the number of times recorded in 40 and 41
The able is collectively output to the counter 10, and the held count value is corrected. The D-FFs 40 and 41 are reset with the update of the counter 10 for the number of recorded times.

In the example shown in FIG. 4, two updates can be held, but of course more updates can be held by increasing the number of flip-flops or the like for storing and holding the number of updates. It is also possible to do so.

[0022]

As described above, according to the present invention,
Since updating of the counter is stopped during the read operation, the value of the counter can be read directly and the saving of the value of the counter is unnecessary. Therefore, the number of save registers can be reduced, and stable data reading can be realized with a small amount of material.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of the second embodiment of the present invention.

FIG. 6 is a block diagram of a general information processing apparatus.

FIG. 7 is a diagram illustrating a problem during a read operation of the counter.

FIG. 8 is a configuration diagram of a conventional example.

[Explanation of symbols]

 10 Counter 11 Output Selector 12 System Bus 13, 14 Counter Control Means 15 Update Count Recording Means

Claims (2)

[Claims] 1. A program-readable counter (1
In a method of controlling reading of a counter in a system including (0), counter control means (13) for controlling the counting operation of the counter (10) is provided, and the counter control means (13)
When it is detected by the counter that the read operation of the counter (10) is performed, the counter is continued until the read operation is completed.
A read control method for a counter, characterized in that the count operation of (10) is stopped, and after the read operation is completed, the count operation of the counter (10) is restarted to update the count value. 2. A program-readable counter (1
0) In a read control method of a counter in a system, a counter control means (14) for controlling the counting operation of the counter (10) is provided, and the counter control means (14)
When it is detected by the counter that the read operation of the counter (10) is performed, the counter is continued until the read operation is completed.
The counting operation of (10) is stopped, and the number of times the counter (10) should be updated during the read operation is recorded by the means (15) for recording the number of updates during that time, and the counter is read after the read operation is completed. A read control method of a counter, characterized in that the counting operation of (10) is restarted and the count value recorded in the updating number recording means (15) is updated.