JPH06350656A - Fsk modulator - Google Patents

Abstract

PURPOSE:To make a frequency shift accurate through consecutive phases, to improve an adjacent channel leakage power characteristic and to block the production of jitter. CONSTITUTION:A PLL loop comprising a variable frequency divider 17, a phase comparator 13, a loop filter 14, analog switches 15, 16 and a VCO 12 is used for a mark signal and a space signal in digital data Sd to obtain an FSK modulation output signal So whose frequency shift is accurate. When there is any signal change between the mark signal and the space signal, the VCO 12 is replaced with a VCO 11 by the changeover of the analog switches 15, 16. An output signal of an inverting amplifier 18 is given to the LPF 19 and its control voltage is fed to the VCO 12 to execute direct FM modulation. The timing by the modulation by the PLL loop and a waveform of direct FM modulation is matched through a delay circuit 21 and an analog switch control circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK modulator which is used in a wireless communication device and has a continuous phase in frequency shift.

[0002]

2. Description of the Related Art FIG. 3 shows this type of FSK (Frequency Shift).
FIG. 3 is a block diagram showing the configuration of a Keying) modulator. In FIG. 3, this FSK modulator has, for example, a frequency of 2OM.
A voltage controlled oscillator (VCO) 1 that oscillates in the Hz band, a phase comparator 3 to which a reference frequency signal having a frequency of 50 KHz is input, a loop filter 4 that removes unnecessary signal components, and an oscillation signal from the voltage controlled oscillator 1 It has a variable frequency divider 7 which divides the frequency by digital data.

Next, the operation of this conventional configuration will be described. The voltage controlled oscillator 1 has a frequency of 20 MHz
The band oscillation signal is input to the variable frequency divider 7. In the variable frequency divider 7, the oscillation signal according to the digital data, for example,
Frequency division by 418 (at the time of space signal) or frequency division by 382 (at the time of mark signal) is performed. The phase comparator 3 performs a phase comparison between the frequency-divided signal of the variable frequency divider 7 and a reference frequency of a frequency of 50 KHz, generates a control voltage according to this phase difference, and controls the voltage controlled oscillator 1. That is, the frequency of the frequency-divided signal from the variable frequency divider 7 is controlled by the closed loop control so as to match the reference frequency. The loop filter 4 removes unnecessary signal components.

In this operation, when the digital data is a mark signal, the oscillation frequency of the voltage controlled oscillator 1 is 50 KH.
z × 382 = 19.1 MHz, and when one digital data is a space signal, the oscillation frequency of the voltage controlled oscillator 1 outputs 50 KHz × 418 = 20.9 MHz.

In this case, when the frequency division number is changed and the frequency of the voltage controlled oscillator 1 is changing, the frequency is divided by the reference frequency.
Jitter occurs. That is, when the frequency division of the variable frequency divider 7 is changed and the frequency of the voltage controlled oscillator is changed,
Jitter of 1 / reference frequency is generated. This is because, as shown in FIG. 4, the time for phase comparison is required to be about 1 / reference frequency.

As a proposal for improvement of this kind, JP-A-63-1
"Wideband FM modulator" disclosed in Japanese Patent Publication No. 98406,
The "modulator" disclosed in JP-A-58-048507 and the "phase continuous FSK modulation circuit" disclosed in JP-A-57-135555 can be mentioned. In the example of Japanese Patent Laid-Open No. 63-198406, the frequency division ratios of the variable frequency dividers of the FSK signal generation circuit and the PLL loop are controlled according to the settings to obtain frequency stability over a wide band. .

An example of Japanese Patent Laid-Open No. 58-048507 is
One voltage controlled oscillator (VCO) is shared, and the outputs of the low-pass filters of the two PLLs each including the FSK modulation loop and the FM modulation loop are switched to eliminate the interference between the FSK modulation and the FM modulation. JP-A-57-1355
In the example of Japanese Patent Publication No. 55, a frequency division ratio setting circuit that changes the frequency division ratio of the variable frequency divider according to the mark and space of the modulated data signal is provided to facilitate adjustment with a simple configuration.

[0008]

However, in each of the above-described conventional FSK modulators, a jitter of 1 / reference frequency is generated, and this jitter increases the error rate of the code at the time of demodulation, which causes a communication error. It has the disadvantage of degrading quality.

The present invention has been made in consideration of the above-mentioned circumstances, and an FSK modulator which has a continuous phase, a precise frequency shift, an excellent adjacent channel leakage power characteristic, and a generation of jitter can be prevented. For the purpose of providing.

[0010]

In order to achieve the above object, an FSK modulator of the present invention has a variable frequency dividing means, a phase comparing means, a loop filter, and a first voltage controlled oscillating means to perform FSK modulation. A PLL loop circuit that obtains an output signal, an inverting unit that inverts and outputs digital data indicating frequency division to a predetermined voltage, and a low-pass for processing rising and falling of data from the inverting and amplifying unit into a smooth curve. A filter, a first switching means for selecting one of control voltages from the loop filter and the low-pass filter, and characteristics of the first voltage-controlled oscillation means are equal to each other, The second voltage controlled oscillation means to which the control voltage is applied and one of the output signals from the first or second voltage controlled oscillation means are selected and varied. Second switching means for outputting to the frequency means, delay means for delaying and outputting digital data, and switching control means for controlling the switching timing of the first and second switching means in accordance with the extended digital data from the delay means. Is provided.

In this configuration, as the inverting means, when the mark signal in the digital data for instructing the frequency division is input, the first voltage controlled oscillator oscillates the first frequency signal and the space signal. Second when is entered
In this configuration, an inverting amplifier set to an amplification degree that supplies a control voltage that oscillates the frequency signal is used.

Further, the delay means is configured to set the delay amount such that the control voltages output from the loop filter and the low-pass filter respectively have the same time.

[0013]

The FSK modulator of the present invention having the above structure is
The PLL loop obtains the FSK modulation output signal with accurate frequency shift. Further, when there is a signal change between the mark signal and the space signal, the second voltage controlled oscillation means and the first
The voltage-controlled oscillation means is switched by the first and second switching means. Further, the output signal of the inverting amplifier is applied to the second voltage controlled oscillation means through the low pass filter, and the FM voltage is directly modulated. Furthermore, the timing of the waveform of the FM loop is directly matched with the modulation of the PLL loop through the delay means and the switching control means. Therefore, the control voltage of the voltage controlled oscillator is smoothly switched, the phase of the FSK modulated output signal is continuous, and the mark signal and the space signal are locked by the PLL to the oscillation frequency of the voltage controlled oscillator, so that the frequency shifts accurately. To do. Further, due to the effect of the low pass filter, the change between the mark signal and the space signal is smoothed, the adjacent channel leakage power characteristic is improved, and moreover, when the signal changes between the mark signal and the space signal, the voltage control oscillation means is provided. The FM modulation is applied directly so that jitter does not occur.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the FSK modulator of the present invention will be described with reference to the drawings. FIG. 1 shows the FS of the present invention.
It is a block diagram which shows the structure of the Example of a K modulator. In FIG. 1, this FSK modulator has a frequency of 19.1M.
Voltage controlled oscillator (VCO) 11 that oscillates Hz or frequency 20.9 MHz, voltage controlled oscillator (VCO) 12 that oscillates at the same frequency as voltage controlled oscillator 11, input reference frequency signal Sa, and voltage controlled oscillator 11 , And a phase comparator 13 for comparing the phases of the oscillation signals from the voltage controlled oscillator 12.

The FSK modulator further includes a loop filter 14 for outputting a control voltage, and an analog for selecting the control voltage from the loop filter 14 or the low pass filter (LPF) 19 and outputting it to the voltage controlled oscillator 12. Analog switch 1 for selecting an oscillating signal from the switch 15, the voltage controlled oscillator 11, and the voltage controlled oscillator 12.
6 and the oscillation signals from the voltage controlled oscillator 11 and the voltage controlled oscillator 12 are frequency-divided by the delayed digital data Sd as described later, and the frequency-divided signals are divided by the phase comparator 1
3 and a variable frequency divider 17 for outputting to 3). further,
This FSK modulator includes an inverting amplifier 18 that inverts digital data Sd into a predetermined voltage and outputs the voltage, and an inverting amplifier 1.
A low-pass filter 19 for generating and outputting an output signal from the control signal for the voltage-controlled oscillator 11 or the voltage-controlled oscillator 12, and an analog switch control circuit 20 for controlling selection switching between the analog switch 15 and the analog switch 16. , And delay circuit 21 for delaying digital data Sd and supplying it to variable frequency divider 17 and analog switch control circuit 20.

Next, the operation of the configuration of this embodiment will be described. The inverting amplifier 18 is an analog switch 1
When the mark signal in the digital data is input when the fixed contact b is selected by 5, the voltage controlled oscillator 12
The amplification degree is set in advance so as to supply a control voltage that oscillates a frequency of 19.1 MHz. In addition, the amplification degree is set in advance so as to supply a control voltage that oscillates at a frequency of 20.9 MHz when the space signal is input.

The output signal from the loop filter 14 or the low pass filter 19 is selected by the analog switch 15 and input to the voltage controlled oscillator 12. In this case, a delay of, for example, about 200 μs occurs in the low-pass filter 19, which is compared with the operation of the PLL loop including the variable frequency divider 17, the phase comparator 13, the loop filter 14, the analog switch 15, and the voltage controlled oscillator 12. Then, the timing will be shifted. Therefore, the delay circuit 2
1 also delays the operation of the PLL loop. Then, the delay amount of the delay circuit 21 is set so that the output timings of the loop filter 14 and the low-pass filter 19 are matched.

FIG. 2 is a waveform diagram showing the output waveform of each part in FIG. In FIG. 2, each operation in section 1, section 2, section 3, and section 4 will be described. First, in the section 1, when the mark signal is input to the digital data input, the analog switch 15 and the analog switch 16 select the fixed contact a. The frequency division number of the variable frequency divider 17 is “382”. The oscillation signal from the voltage controlled oscillator 12 is divided by the variable frequency divider 17.

The phase comparator 13 compares the frequency of the frequency-divided signal from the variable frequency divider 17 with the reference frequency of 50 KHz, generates a control voltage according to the phase difference, and causes the voltage-controlled oscillator 12 to operate. Control. With this control, the variable frequency divider 17
The frequency of the frequency-divided signal is controlled so as to match the reference frequency signal Sa. The loop filter 14 removes unnecessary signal components. In this case, the frequency of the oscillation signal from the voltage controlled oscillator 12 is locked at 50 KHz × 382 = 19.1 MHz and maintains an accurate and stable frequency. The characteristics of the voltage controlled oscillator 11 are the same as those of the voltage controlled oscillator 12, and since the same control voltage is applied, the oscillation frequency of the voltage controlled oscillator 11 is also 19.1 MHz.

In the section 2 in FIG. 2, when the signal of the digital data Sd shown in FIG. 2A changes from the mark to the space, the frequency division number of the variable frequency divider 17 is switched to "418". Further, the analog switch 15 and the analog switch 16 select the fixed contact b. As a result, the variable frequency divider 17, the phase comparator 13, the loop filter 14,
A PLL loop composed of the voltage controlled oscillator 11 is formed so that the oscillation frequency of the voltage controlled oscillator 11 is 50 KHz × 4.
18 = 20.9 MHz. During this transition, the jitter described above occurs as shown in FIG.

On the other hand, since a control voltage for oscillating a frequency of 20.9 MHz is applied from the inverting amplifier 18 to the voltage controlled oscillator 12 through the low pass filter 19 shown in FIG. 2 (c), the FSK modulation output signal So is , The frequency shifts to 20.9 MHz. The change in this case is smoothed by the effect of the low-pass filter 19. Further, since it is different from the control voltage supplied from the phase comparator 13, no jitter occurs.

In section 3 in FIG. 2, when the oscillation frequency of the voltage controlled oscillator 12 shifts to 20.9 MHz, the analog switches 15 and 16 respectively select the fixed contact a. In this case, the control voltage shown in FIG. 2 (b), which is already locked to the frequency of 20.9 MHz, is the loop filter 14
, The oscillation frequency of the voltage controlled oscillator 12 is accurately locked to 20.9 MHz, and the FSK modulation output signal So also has this frequency of 20.9 MHz.

In the section 4 in FIG. 2, when the digital data Sd changes from the space signal to the mark signal, the frequency division number of the variable frequency divider 17 is switched to "382". Further, the fixed contact b is selected in the analog switch 15 and the analog switch 16. As a result, the variable frequency divider 1
7, a phase comparator 13, a loop filter 14, and a voltage controlled oscillator 11 form a PLL loop, and the oscillation frequency of the voltage controlled oscillator 11 is 50 KHz × 382 = 19.
Move to 1 MHz. During this transition, jitter occurs as described above.

On the other hand, the voltage controlled oscillator 12 has a frequency of 1
Since a control voltage for oscillating and outputting 9.1 MHz is applied, the FSK modulation output signal So has a frequency of 19.1 MHz.
Move to. The change at this time is smoothed by the effect of the low-pass filter 19. Further, since it is different from the control voltage supplied from the phase comparator 13, no jitter occurs. The operations of the section 1 to section 4 are repeated by the change of the input signal to obtain the jitter-free FSK modulation output signal S shown in FIG.
o is obtained.

[0025]

As described above, according to the FSK modulator of the present invention, the control voltage of the voltage controlled oscillating means is smoothly switched, the phase of the FSK modulated output signal is continuous, and
The mark signal and the space signal have the effect that the oscillation frequency of the voltage controlled oscillation means is locked by the PLL, and the frequency shifts accurately.

In addition, due to the effect of the low-pass filter, the change between the mark signal and the space signal is smoothed, the adjacent channel leakage power characteristic is improved, and the voltage is changed when the signal is changed between the mark signal and the space signal. FM oscillation is directly applied to the control oscillating means, so that the jitter is not generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an FSK modulator of the present invention.

FIG. 2 is a waveform diagram showing an output waveform of each part in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional FSK modulator.

FIG. 4 is a waveform diagram for explaining jitter in the operation of the conventional FSK modulator shown in FIG.

[Explanation of symbols]

 11, 12 Voltage-controlled oscillator 13 Phase comparator 14 Loop filter 15, 16 Analog switch 16 Analog switch 17 Variable frequency divider 18 Inverting amplifier 19 Low-pass filter 20 Analog switch control circuit 21 Delay circuit

Claims (3)

[Claims] 1. A PLL loop circuit having a variable frequency dividing means, a phase comparing means, a loop filter, and a first voltage controlled oscillating means to obtain an FSK modulated output signal, and digital data of frequency division instruction to a predetermined voltage. Inverting means for inverting and outputting, low-pass filter for processing rising and falling of data from the inverting-amplifying means into a smooth curve, and one of control voltage from the loop filter and low-pass filter are selected. First switching means and second voltage controlled oscillation means having characteristics equal to those of the first voltage controlled oscillation means, and to which control voltages from the loop filter and the low pass filter are applied through the switching means; Second switching for selecting one of the output signals from the first or second voltage controlled oscillating means and outputting it to the variable frequency dividing means A stage, delay means for delaying and outputting the digital data, and switching control means for controlling switching timing of the first and second switching means in accordance with the extended digital data from the delay means. FSK modulator. 2. As the inverting means, when the mark signal in the digital data for instructing the frequency division is input, the first frequency controlled oscillator oscillates the first frequency signal and the space signal is input. The FSK modulator according to claim 1, wherein an inverting amplifier set to an amplification degree that supplies a control voltage for oscillating the second frequency signal is used. 3. The FSK modulator according to claim 1, wherein the delay means is set to a delay amount in which the control voltages output from the loop filter and the low-pass filter are matched in time.