JPS647519Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an erasable programmable read-only memory device that can be written to and read from without the need for an address signal generator.

Conventionally, an erasable programmable read-only memory (hereinafter abbreviated as EPROM) device has an EPROM element array 8, an address decoder circuit 4, an input/output buffer 6, and a write/read control circuit 3, as shown in FIG. It consists of the main elements. The data write operation of the EPROM element is carried out by giving a write address from the outside to multiple address terminals 2, giving a write pulse signal to terminal 1, and inputting write data to data input/output terminal 5, which corresponds to the write address. Data is written to the EPROM element. The read operation has the function of inputting a read address and a read pulse signal to terminals 2 and 1, respectively, and outputting data of the EPROM element determined by the read address from terminal 5.

Generally, writing and reading of an EPROM device is performed at the timing shown in FIGS. 2 and 3.

FIG. 2 is a waveform diagram of write pulses of the EPROM device.

In FIG. 2, a is write address data,
b and c are waveforms of included data, d is included pulse, A
is the set-up time for the data write pulse, B is the hold time for the data write pulse, C is the set-up time for the address write pulse, and D is the hold time for the address write pulse.

When the write pulse is "high" (e.g. 24V),
Writing is performed when active, and inactive when “low” (0V). When the write pulse is "high", the specified address is fixed and the write data is fixed. If the write data of b is contained in the fixed address of a, "0" data will be written, and if the write data of c is contained, the data of "1" will be written. .

FIG. 3 is a waveform diagram of read pulses of the EPROM device.

In FIG. 3, a is the read address waveform, b
is the read pulse waveform, c is the read data when the level is "high", d is the read data when the level is "low", E is the setup time for the read pulse of the read address, and F is the read address of the read address. Hold time for pulse, G is delay time of read data from read pulse, H
is the data hold time from the read pulse.

Read pulse is at “high” level (e.g. 5V)
When it is active, reading is performed, and when it is at a "low" level (0V), it is inactive. The address specified when the read pulse is at the "high" level is fixed, and the read data at that address is output.
Data is read from the fixed address a, and if the address contains data of "1" at that time, the waveform of c is output and the data becomes "0".
If data is included, the waveform d is output. Note that since the write pulse and the read pulse have different "high" level voltage values, it is possible to easily distinguish between data write and data read modes. This method of identifying writing and reading using different voltage values is known, for example, from Japanese Patent Laid-Open No. 51-54788.

Conventionally, it was necessary to externally set the write address and read address with a set-up and hold time for the write/read pulse, so the user had to set the write address and read address when writing.
It was necessary to have a device that generates an address signal with up and hold times.

That is, each address terminal 2 is connected to an address line for inputting an address from the outside.
As a result, it has a fairly large parasitic capacitance. Since the address of the address signal to each address terminal 2 is fixed by charging or discharging such a large parasitic capacitance, the charging/discharging time of the parasitic capacitance is longer than the setup and hold time of the write address and read address. Was. Furthermore, since memory elements are selected only by external addresses, it is necessary to control the timing of addresses and write/read pulses.

An object of the present invention is to provide an EPROM device that can shorten the time required to determine an address and eliminates the need for timing control with write and read pulses.

The present invention is characterized in that a counter circuit for counting write/read pulses is provided inside, and a switching terminal and a multiplexer are provided so that the counted contents of this counter circuit are supplied to an address decoder instead of an external address. .

Hereinafter, the present invention will be described by way of examples with reference to the drawings.

FIG. 4 is a circuit diagram of an EPROM device according to an embodiment of the present invention.

A binary counter 9 that uses a read pulse signal or a write pulse signal as a count-up input is added to an EPROM device configured in the same way as the conventional one.
The parallel outputs A′ ₀ , A′ ₁ , ...A′ _N of the decimal counter 9 are
Used as the second address of the EPROM device (hereinafter referred to as internal address), and from external terminal 2 of the device.
Addresses inputted as A ₀ , A ₁ , _. . . That is, in addition to the data reading and writing functions of the EPROM element 8 by external address designation, the EPROM element 8 has burst read and burst write functions by internal addresses that are increased by read pulses or write pulses without external address designation. be able to. An external address/internal address switching signal for switching control of multiplexer 10 is supplied to terminal 11.

The burst write and burst read operations will be described below with reference to FIGS. 4 to 6.

In the burst write shown in FIG.
When the switching signal to 1 is inverted from the "low" level to the "high" level, a clear signal is given to the counter 9 by the inverter 12, so that its content becomes "0" as shown. Since this content "0" is supplied to the address decoder circuit 4 via the multiplexer 10, the memory element at address 0 is selected. On the other hand, data to be written to data input/output terminal 5
D ₀ is applied, and in this state the write pulse to terminal 1 changes from a "low" level (0V) to a "high" level (24V). Thus, data D ₀ is written to the memory element at address 0. The count content of the counter 9 becomes "1" in synchronization with the change of the write pulse from "high" to "low" level, and this content is supplied to the address decoder circuit 4 via the multiplexer 10, so that the count at address 1 is A memory element will be selected. Also, the data to be written is changed to _D1 . Then, by changing the write pulse from "low" to "high", data D ₁
is written to the memory element at address 1. Thereafter, each time the write pulse changes to the "low" level, the counter 9 counts up and the count contents are supplied to the address decoder 4, and the desired data D ₂ , D ₃ ,
...is written.

In the burst read shown in FIG.
Due to the switching signal to 1, the contents of the counter 9 become "0" and are applied to the address decoder 4 via the multiplexer 10. A read operation is performed by changing the read pulse from a "low" level (0V) to a "high" level (5V), and data D ₀₀ of the memory element at address 0 is output. The counter 9 counts up in synchronization with the change of the read pulse from the "high" level to the "low" level, and the count becomes "1". This content "1" is supplied to the address decoder 4 via the multiplexer 10. The data of the first memory element is read out as D ₀₁ by supplying the read pulse.
Thereafter, each time the read pulse changes to the "low" level, the contents of the counter 9 are changed and supplied to the address decoder 4 as address data.
D ₀₂ , D ₀₃ , . . . are read out sequentially.

In FIGS. 5 and 6, the count contents of the counter 9 change automatically each time a write or read pulse is supplied, and the output load capacity is small, so the address setup as explained in the conventional example is not possible. , hold time becomes unnecessary or becomes extremely short, allowing high-speed data writing and reading. Furthermore, timing control of write and read pulses and address changes is also unnecessary.

In the EPROM device of the present invention, the above-mentioned functions are effective when writing or reading all bits of the EPROM element array 8, and there is no need to input an external address. Setting the address for
There is an advantage that there is no need to consider timing such as up and hold times. In other words, during this burst mode writing, by simply providing a write pulse and write data, the write pulse is reduced to N.
Then, data can be written to EPROM elements from address 0 to address N.

Further, when reading data, by simply applying a read pulse, and assuming that the number of read pulses is M, data of the EPROM elements from address 0 to address M can be sequentially obtained in synchronization with the read pulse.

As explained in detail above, according to the present invention,
The effect is great because it is possible to obtain an EPROM device that can be written to and read from without requiring a device that generates address signals.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional EPROM device, Figure 2 is a waveform diagram to explain the write operation of the EPROM device, Figure 3 is a waveform diagram to explain the read operation of the EPROM device, and Figure 4 is a waveform diagram to explain the read operation of the EPROM device. FIGS. 5 and 6, which are circuit diagrams of an EPROM device according to an embodiment of the present invention, are timing charts showing burst write and burst read operations, respectively, in the EPROM device shown in FIG. 4. 1... Control signal external terminal, 2... Address input terminal, 3... Write/read control circuit, 4... Address decoder circuit, 5... Memory/data input terminal, 6... I/O buffer, 7... R/W sense amplifier, 8...EPROM element array, 9...2
Numerical counter, 10...Multiplexer, 11...
...External address/internal address switching signal input terminal.

Claims (1)

[Scope of utility model registration request] an array of memory elements; an address decoder circuit for selecting a predetermined memory element in response to applied address data; a first terminal to which a write pulse or a read pulse is applied; In an erasable programmable read-only memory device comprising a write/read control circuit for writing data to or reading data from a memory element, and a plurality of second terminals to which address signals are supplied from the outside, the memory device is coupled to the first terminal. a counter circuit that counts the write pulses or read pulses, a third terminal to which a switching signal is supplied, an external address signal supplied to the plurality of second terminals, and one of the count contents of the counter circuit. a multiplexer that selects the data in response to the switching signal supplied to the third terminal and supplies the selected data to the address decoder circuit as address data, and writes burst data or writes the counted contents of the counter circuit as an internal address. An erasable programmable read-only memory device characterized by enabling burst data reading.