JPH0638499B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a MOSFET in which the length of the electric field strength relaxation layer on the drain side is longer than that on the source side, and the length of the electric field strength relaxation layer on the drain side and the source side. The present invention relates to a method of manufacturing a semiconductor device that can be manufactured without increasing the number of MOSFETs and masks and the number of steps that are substantially equal.

2. Description of the Related Art A bootstrap circuit as shown in FIG. 6 is often used in a dynamic clock buffer circuit used in a dynamic random access memory (DRAM).

When voltage pulses (clocks) A and B as shown in FIG. 6B are applied to each of the force terminals A and B of the circuit having the transistors Q _{1 to} Q ₄ shown in FIG. 6A. , A voltage higher than the power supply voltage (5V) is applied to the drain (node C) of the transistor Q ₂ .

When the drain of the MOSFET is connected to such a high voltage node, the internal electric field of the MOSFET becomes high, and hot carriers are generated especially near the drain exposed to the high electric field, which forms a trap in the gate oxide film. It is also known that a level is formed at the interface of the silicon gate oxide film to deteriorate the characteristics of the MOSFET, and as a result, the operation speed of the circuit is slowed.

The double-diffused drain MOSFET is self-aligned with the gate oxide film 22 and the polysilicon gate 23 formed on the p-type silicon substrate 21, and the polysilicon gate 23, as shown for the n-channel type in FIG. The n ^- diffusion layer 24 having a low impurity concentration doped with phosphorus and the n ⁺ diffusion layer 25 having a high impurity concentration doped with arsenic formed inside the n ⁻ diffusion layer.

In the double diffused drain MOSFET, the electric field strength near the drain is relaxed by the electric field strength relaxation layer in the n ⁻ region represented by the length X shown in FIG. 7, and the generation of hot carriers is significantly suppressed.

Problems to be Solved by the Invention However, when an integrated circuit is constituted by the conventional double diffused drain MOSFET as shown in FIG. 7, a high voltage is applied to the drain like the transistor Q ₂ shown in FIG. It is difficult to make only the applied MOSFET into a structure having particularly excellent hot carrier resistance (that is, a structure in which the length of the n ⁻ diffusion layer X of the drain is long), and therefore it is possible to sufficiently secure the reliability of the integrated circuit. could not.

The present invention has been made in order to solve the above-mentioned drawbacks that occur when an integrated circuit is composed of conventional double diffused drain MOSFETs, and is disclosed in an integrated circuit including a bootstrap circuit for generating a voltage higher than a power supply voltage. This was done to greatly improve reliability.

Means for Solving the Problems In order to solve the above problems, the present invention provides a step of forming a gate oxide film on a semiconductor substrate, a polysilicon film is formed on the gate oxide film, and a photoresist is used as a mask. A step of forming a gate electrode of the first MOSFET and a gate electrode of the second MOSFET arranged in a relationship rotated by approximately 90 degrees with the first MOSFET by anisotropic etching; First, using the gate electrode as a mask
Draining the first MOSFET from a diagonal direction in which the drain region of the MOSFET does not shade the gate electrode, and implanting a second impurity into the semiconductor substrate. In the semiconductor device manufacturing method, the side electric field strength relaxation layer on the side is longer than that on the source side of the MOSFET, and the electric field strength relaxation layers on the drain side and the source side of the second MOSFET are set to be substantially equal in length.

Effect According to the present invention, when the first impurity for forming the drain and source regions and the second ion implantation are performed, the drain side and the source side of the first MOSFET in which a part of the ions are blocked by the gate electrode The lengths of the electric field strength relaxation layers are made different, and the electric field strength relaxation layers on the drain side and the source side of the second MOSFET in which implanted ions are not blocked by the gate electrode are substantially equal.

Embodiment An embodiment in which the present invention is applied to an n-channel type MOS integrated circuit is shown in FIGS.

FIG. 1 shows an embodiment of a MOSFET made by the present invention in which the drain side electric field strength relaxation layer is longer than that on the source side. 2 is an embodiment in which a MOSFET is arranged on a chip of a semiconductor substrate in carrying out the present invention, FIG. 3 is a sectional view taken along line xx ′ in FIG. 2, and FIG. 4 is yy. FIG.

In an integrated circuit, a MOSFET whose drain is connected to a node at which a voltage higher than the power supply voltage is generated is a p-type silicon substrate 1 and a gate formed on the same substrate as shown in FIG. The gate electrode 3 made of polysilicon formed on the oxide film 2 and the gate oxide film, and the n ⁻ diffusion layer 4 formed in a self-aligned manner with respect to the gate electrode and formed inside the n ⁻ diffusion layer 4 and n ⁺ diffusion layer 5.

Further, the length X _D on the drain side is longer than the length X _S on the source side on the gate surface of the n ⁻ region 4 to be the electric field strength relaxation layer, and even if a high voltage is applied to the drain. It has a structure that can suppress the generation of hot carriers.

Next, FIG. 2 shows a state in which a part of the MOSFETs forming the integrated circuit is arranged on the chip.

In Figure 2, MOSFET Q A power supply voltage or more to the drain is _{applied, Q B,} Q _C is the direction from the source region 13 to drain region 14, are selected in the x-direction of the chip. Moreover, as can be seen from the cross-sectional view taken along line x-x 'shown in FIG. _{3, MOSFET Q A, Q B,} Q C is formed by MOSFET shown in FIG. 1, the drain region 14
The length of the electric field strength relaxation layer at the surface is longer than that of the source region 13.

On the other hand, only the voltage below the power supply voltage is applied to the drain
MOSFET Q _{D, Q E} is _{MOSFET Q A, Q B, Q} C is arranged in a direction that is rotated 90 degrees, the direction from the source region 13 to the drain region 14 is disposed in the -y and y direction of the chip There is.

The MOSFETs Q _D and Q _E are connected to the drain region 14 and the source region 1 as shown in the cross-sectional view taken along the line yy ′ in FIG.
3 has the same shape as the conventional double diffused drain MOSFET (see FIG. 7) having the same length on the surface of the electric field strength relaxation layer.

Next, a method of manufacturing the integrated circuit of the present invention will be described with reference to FIG.

Chip 1 made of p-type silicon as shown in FIG.
After forming a gate oxide film on the first layer, a polysilicon film having a thickness of about 5000Å is formed by a well-known CVD method, and the first impurity phosphorus is doped into the polysilicon by thermal diffusion, and then a photoresist is used as a mask. Then, anisotropic etching of polysilicon is performed to form the gate electrode 12.
After that, the first impurity (phosphorus) is accelerated with an acceleration energy of 80 Ke by ion implantation using the gate electrode 12 as a mask.
v, dose amount about 1 × 10 ¹⁴ cm ^{-2 is} implanted. At the time of this phosphorus implantation, the implantation direction is tilted in the xz plane with respect to the surface of the chip 11 by about 7 degrees in the x direction, that is, the direction in which the entire drain region 14 shown in FIG. In other words, the gate electrode 12 is the drain region 14
Io is injected from the spine's back.

Next, the implanted phosphorus atoms are activated and diffused by heat treatment at 1000 ° C. for 10 minutes to form an n ⁻ diffusion layer, and this time, as shown in FIG. 5B, the second impurity ( Arsenic) is ion-implanted using the gate electrode 12 as a mask under conditions of a smaller dose amount and a lower acceleration energy, for example, a dose amount of 5 × 10 ¹⁵ cm ⁻² and an acceleration energy of 40 Kev, as compared with the above-described phosphorus ion implantation. .

Contrary to the phosphorus ion implantation, the implantation of arsenic ions is performed with an inclination of about 7 degrees in the −x direction with respect to the surface of the chip 11 in the xz plane.

Finally, heat treatment is performed at 900 ° C. for 30 minutes to activate and diffuse the implanted arsenic to form an n ⁺ diffusion layer.

According to the above manufacturing method, the MOSFET Q _A ,
Length at Q _B, for phosphorus ions at a concentration and a high acceleration energy lower that (dose) as compared to the source side to the drain side of the Q _C is injected, the electric field intensity relaxation layer surface of the drain region 14 Is longer than that of the source region. On the other hand, in the MOSFETs Q _D and Q _E , when the ions of phosphorus and arsenic are ion-implanted, a part of the implanted ions is not blocked by their gate electrodes, and the drain side and the source side are irradiated almost uniformly. As shown in FIG. 4, the lengths of the electric field strength relaxation layers in the source region 13 and the drain region 14 are equal.

Although the maskless manufacturing method is described in this embodiment, it is obvious that the MOSFET having the structure obtained in the present invention can be manufactured by using an appropriate mask.

Advantageous Effects of Invention According to the present invention, MOSFETs that form an integrated circuit are provided with a high voltage applied to the drain and a high voltage not applied to the drain in consideration of the layout of the mask.
Proper selection of the slope has the effect of significantly improving the reliability of the entire integrated circuit.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a MOSFET manufactured according to an embodiment of the present invention, FIG. 2 is a view showing a layout of MOSFETs arranged on a semiconductor substrate for carrying out the present invention, and FIG. Is a cross-sectional view taken along the line xx 'shown in FIG. 2, and FIG.
5 is a cross-sectional view taken along line y ', FIGS. 5 (a) and 5 (b) are views showing the main part of the manufacturing method of the present invention, and FIGS. 6 (a) and 6 (b) are bootstrap circuits and voltage waveforms during operation. FIG. 7 is a cross-sectional view of a main part showing a conventional double diffused drain MOSFET. 1 ... p-type silicon substrate, 2 ... gate oxide film, 3 ...
Gate electrode, 4 ... N ^- diffusion layer, 5 ... N ⁺ diffusion layer, 1
1 ... Chip, 12 ... Gate electrode, 13 ... Source region, 14 ... Drain region.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9170-4M H01L 27/08 102 B 9170-4M 27/10 325 V

Claims (2)

[Claims] 1. A step of forming a gate oxide film on a semiconductor substrate, a polysilicon film is formed on the gate oxide film, and anisotropic etching is performed by using a photoresist as a mask. Forming a gate electrode of the second MOSFET arranged in a relationship of approximately 90 degrees rotation with the first MOSFET, and using the gate electrodes of the first and second MOSFET as a mask, the drain region of the first MOSFET is the gate region. And a step of ion-implanting a second impurity into the semiconductor substrate from an oblique direction that does not shade the electrode, and a step of ion-implanting a second impurity into the semiconductor substrate. A method of manufacturing a semiconductor device, characterized in that it is longer than that on the source side of the MOSFET, and the electric field strength relaxation layers on the drain side and the source side of the second MOSFET are substantially equal in length. 2. The manufacturing of the semiconductor device according to claim 1, wherein the second impurity ions are implanted from an oblique direction in which the source region of the first MOSEFT does not shade the gate electrode. Method.