JPH0638797B2 - Ultrasonic diagnostic equipment - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an ultrasonic diagnostic apparatus for displaying an ultrasonic image by radial scanning.

[Technical background of the invention and its problems]

An image display method in an ultrasonic diagnostic apparatus that performs a conventional radial scan uses an XY monitor and sets an X, Y coordinate and a luminance signal in an analog manner with respect to radial scan data and sweeps them to display an image. It was a thing. Such an image display method has problems that the rasters are displayed apart from each other, that the display image is difficult to see if the sweep time is slow, and that the display image is difficult to freeze (still).

On the other hand, in an ultrasonic diagnostic apparatus which displays an ultrasonic image by sector scanning, scan data converted into a digital signal by a DSC (Digital Scan Converter) circuit is written in a storage unit (frame memory) in the same vector as an ultrasonic raster, and this is written on a TV. A method is adopted in which the monitor is read in the scanning direction and an image is displayed.

By the way, considering the reason why the DSC circuit is not used when displaying an image of the radial scan data,
In the case of sector scan data, when blank pixels between rasters are read out, interpolation processing is performed in the horizontal direction of the TV monitor to fill it, whereas in the case of radial scan data, as shown in FIG. This is because there are many empty pixels in the horizontal direction in the raster close to the horizontal direction and it is difficult to interpolate the pixels.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and when the radial scan data is interpolated and written in each pixel of the storage unit, a small amount of vector data information is appropriately converted to perform a zoom display or a moving display. It is an object of the present invention to provide an ultrasonic diagnostic apparatus that enables writing.

[Outline of Invention]

The outline of the present invention for achieving the above object is to store radial scan data obtained by radial scanning an ultrasonic probe in a storage means and display a radial scan image based on the radial scan data on a display means. In the ultrasonic diagnostic apparatus, an interpolation processing unit that performs a predetermined interpolation process on the radial scan data and sends the interpolation result data to a storage unit, and a plurality of pixel areas on the storage unit that should store the interpolation result data are provided. Conversion processing for setting data corresponding to all areas based on vector data indicating the raster direction in one of the divided areas, addition processing of predetermined bias values for these vector data, and area determination of addition processing results Processing is performed and the interpolation result data is transmitted from the interpolation processing unit to the storage means. Write address signal corresponding to each area divided in synchronization with the writing or a write address signal determined by the area determination processing is sent to the storage means. .

Example of Invention

Examples of the present invention will be described in detail below. The apparatus of the embodiment shown in FIG. 1 includes an ultrasonic probe 1 such as a mechanical sector scan probe capable of performing a radial scan on a subject, and a controller 30 (details will be described later) for controlling each part of the apparatus. A transmitting / receiving circuit 2 for exciting the ultrasonic probe 1 at a predetermined timing based on a control signal and receiving radial scan data obtained by the ultrasonic probe 1, and the radial scan data sent from the transmitting / receiving circuit 2 for the radial scan data An interpolation processing unit 4 that performs interpolation processing based on a control signal from the controller 30 and a frame memory 6 that is controlled by the controller 30 and that stores the interpolation processing result of the radial scan data by the interpolation processing unit 4 as a storage unit.
Writing address designating means 5 for designating a writing address for writing to each pixel, and the radial scan data and interpolation processing data (hereinafter referred to as "interpolation processing result data") written in the frame memory 6 are read out and displayed. And a read circuit 7 for sending to the TV monitor 8 and a trackball for changing the state of the display image on the TV monitor 8 by controlling the read circuit 7 by sending an input signal to the controller 30. And input means 9.

The write address designating means 5 is a controller 30.
A circular area P (third area) formed by radial scan data to be stored on the frame memory 6
(See the drawing) is divided into four blocks, for example, A block to D block, and a vector data generator 31 for generating vector data x _A , y _A corresponding to the A block and the vector data x _A , y _A are accumulated. The basic address generating unit 32 which generates the address of the A block shown in FIG. 4 (a) by adding and the address of the A block generated by the basic address generating unit 32, which is controlled by the controller 30, are rotated to generate the address shown in FIG. Addresses to be written in the frame memory 6 as shown in FIGS. 4 (b) and 4 (c), which are controlled by the coordinate conversion unit 33 that generates the addresses of the B, C, and D blocks shown in FIG. To obtain a predetermined bias value (α for the x direction, β for the y direction) to the address of each block, If each address after calculation, it is determined whether or not corresponding to the address on the frame memory 6, it is judged if not the address on the frame memory has an address discrimination unit 35 for prohibiting the writing.

Considering the addresses of the blocks A to D, the vector data x _B , y _B of the B block is the vector data x _A , y _A of the A block 90 ° clockwise as shown in FIG. 4 (a). It is rotated, and x _B = y _A , y _B =
It can be expressed as -x _A.

The vector data x _C , y _C of the C block is obtained by rotating the vector data x _A , y _A in the clockwise direction.
_C = -x _A, can be expressed by y _C = -y _A.

Similarly, the vector data x _D , y _D of the D block is obtained by rotating the vector data x _A , y _A by 270 ° in the clockwise direction, and can be expressed as x _D = -y _A , y _D = x _A.

Each of these vector data x _A , y _A , x _B , y _B , x _C ,
y _C , x _D , y _D will have only the values in their respective blocks A, B, C, D.

Next, the bias value addition processing of the bias addition unit 33 will be considered. When the frame memory 6 is located on the x and y coordinates as shown in FIG. 4 (b), the area P can be represented as the shaded area in FIG. For the output, for example, the bias value α ₁ is set for the x direction and the bias value β ₁ is set for the y direction.

That is, the setting of the bias values α ₁ and β ₁ means that all the addresses corresponding to the write address signals X and Y designated through the discrimination by the address discriminating unit 35 exist in the frame memory 6. .

Meanwhile, the bias value alpha _1, a bias value that is different from the beta ₁ alpha
₂ and β ₂ are set, and when the addition result by the bias addition unit 34 becomes a portion corresponding to the actual address on the frame memory 6 and a portion other than that as shown by the hatched portion in FIG. 4 (c). The address discrimination unit 35 sends the write address signal of only the portion corresponding to the shaded portion to the frame memory 6, and performs the write prohibition process for the portion within that.

As a result, in this case, only the interpolation processing result data from the interpolation processing unit 4 corresponding to a part of the B block and a part of the C block and a central part of the A block and the D block in the area P is the write address. The write address signals X and Y from the designating means 5 are written in the corresponding pixels on the frame memory 6.

Next, details of the interpolation processing unit 4 and the controller 30 will be described with reference to FIG.

The interpolation processing unit 4 is an A / D that converts radial scan data, which is a reflected ultrasonic echo signal, into a digital signal.
A converter (ADC) 12, a high-speed buffer memory group 13 which includes a plurality of high-speed buffer memory 13A~13N for storing each line by line through the switch SW ₁ of the digital data of the beams scanned, the high-speed buffer The outputs of the filter calculators 15A to 15N are added to the filter calculator group 15 including a plurality of filter calculators 15A to 15N for multiplying the data read through the switch SW ₂ to the memory by a coefficient for filter calculation. The adder 6 sends the addition result to the frame memory 6 as interpolation processing result data.

The interpolation processing of the radial scan data by the interpolation processing unit 4 is performed based on a first basic address signal (described in detail later) of three types from the controller 30.

That is, the controller 30 counts the clock signal CK ₁ of the clock generator 17 for generating a basic clock of each circuit based on the input signal from the input means 9 and outputs a Y address selection signal. X address (n) for inputting the clock signal CK ₁ similarly and accumulatively adding the predetermined X direction unit address signal ΔX _n
+1 counter 22 which counts the second clock signal CK ₂ by +1 by using the first clock signal CK ₁ as a clear signal and generates an output of + δ out of the two clock signals from the accumulator 19 and the clock generator 17.
And an adder 21 for adding the output + δ of the +1 counter 22 and the output ΔX from the X-address cumulative adder 19 and outputting an X-direction selection signal, the X-address selection signal and the Y-address. The selection signal is sent to the write address designating means 5 as the second basic address signal.

Here, the principle of the interpolation processing of the radial scan data by the interpolation processing unit 4 will be described.

Conventionally, as shown in FIG. 6, the beam BM passing through the pixel P is set to sample points (large black circles in the figure) at almost pixel intervals, and the data is written to the write point (white circle in the figure) at the center of the pixel. In the present invention, an additional sample point (small black circle in the figure) is provided by further dividing the sample point, and the filter calculation is performed based on the data of the sample point whose starting point of the beam is at the same distance as the distance to the center position of the pixel P. The center of the pixel (white circle) is filled according to the result. The filter calculation in this case is performed by the following equation (1).

As is clear from the above equation (1), it is the shape of the filter function h (x) and the convolution range N that determine the filter operation. In this case, the filter function varies innumerably according to the design method and can be arbitrarily determined without being specified. Further, the convolution range N can be changed infinitely according to the scale of the scan and hardware configuration. Since it is a thing, it can be arbitrarily determined.

Although the above description is for writing data to a pixel through which the beam BM passes, writing (embedding) into a pixel through which the beam BM does not pass will be described with reference to FIG. 7. In the figure, for example, the pixels P ₂ , P ₃ , and P ₄ are areas where the beam does not pass. In this case, the arcs l ₂ , which correspond to the distances from the beam generation points of the center points O ₂ , O ₃ , O ₄ of each pixel,
The adjacent beams BM _n intersecting each line by subtracting l ₃ and l ₄
And BM _n-1 at sampling points S ₂ , S ₂ ′ S ₃ ,
A filter operation is performed based on the data of each combination of S ₃ ′, S ₄ and S ₄ ′, and the result is the center position O ₂ of each pixel,
O _3, are to be written to O _4. Similarly, for the pixel P ₁ through which the beam passes, similarly, the pixel P ₁ may be written at the center position O ₁ based on the data of the sample points S ₁ and S ₁ ′ on the same arc l ₁ .

Here, the principle of selection of sample points which is the basis of the above filter calculation will be described with reference to FIG. The interval between the adjacent beams BM _n and BM _n-1 is L, the writing target pixel is P ₃ , the center position is O _3, and the sample point S located at the intersection of the horizontal line passing through this O ₃ and the beam BM _{n. If} the distance to ₀ is X _B , the sample point S ₃ is located at the intersection of the line drawn from the center position O ₃ on the beam BM _n , and the deflection angle of the beam is θ, the sample point S on the beam BM _n is ₀
The distance r _B from to another sample point S ₃ is calculated by the following equation (2).

r _B = X _B · sin θ (2) The sample point S ₀ is a coordinate obtained by cumulative addition in the X direction, and r in the figure is a radius obtained by cumulative addition in the radial direction.

The position of the sample point S ₃ can be known by adding the r to the r _B obtained by the above equation (2).

Similarly, the sample point S ₃ ′ of the adjacent beam BM _n-1 is obtained, the filter operation is performed based on the data at both ends, and the result is written in the center O ₃ of the pixel P ₃ . In this case, the filter coefficient can be determined by inputting the _XB and L to determine the positional relationship between the writing point and the adjacent beam, and giving it the filter characteristic. As a result, since the data and the coefficient can be output, the convolution operation can be performed based on the both, and the output can be written in the target pixel.

Further, in the present invention, processing is performed so that all pixels are filled in order to prevent occurrence of empty pixels. This will be described with reference to FIG. Here, the nth beam BM _n and n
A case will be described in which all of the space between the _first beam BM _n-1 is filled.

First, two systems of vector generators are prepared, and an address is generated by cumulatively adding +1 in the Y direction and ΔX _n and ΔX _{n−1 in the} X direction. After calculating the Y address Y and the X address _Xn , _Xn-1 , _Xn- X
_The number of empty pixels is calculated by performing _n-1 calculation. And (Y, X
After performing the write to _n), +1 Mr. _{X n} (Y, _{X n}
Write to (+1). After this operation was performed _{X n} -X _n-1 times to generate a new guess address as _{Y = Y + 1 X n =} X n + ΔX n X n-1 = X n-1 + ΔX n, repeating the above operation By the ninth
As shown, all the pixels 1 to 36 in the area surrounded by the beam can be filled.

The X-address cumulative adder has a two-system configuration, and in addition to the n-th beam cumulative adder described above, there is an n-1 th cumulative beam adder 20 immediately before the beam.
This is for performing the cumulative addition of the clock signal CK ₁ and the unit selection signal ΔX _n-1 of the (n-1) th beam. This is provided in order to realize the above-mentioned calculation of FIG. 8 as described below.

That is, a subtractor 23 for subtracting the outputs of the two X-address cumulative adders 19 and 20 is provided to intersect two adjacent beams BM _n and BM _{n-1 as shown} in FIG. obtains distances L of the line passing through the center O ₃ of the object pixel P _3, and inputs a parameter of filter operation unit 15 to be described later output L as one of the first base address signal, the next stage of the comparator 24 Is output to. The comparator 24 compares the distance L with the output + δ of the +1 counter 22, and outputs a clear signal to the clock generator 17 based on the output when both match. As a result, X
Addresses are sequentially selected up to the distance L, but when cleared, the address returns to the original position and address selection is performed in relation to the next Y address selection signal. Further, the output + δ from the +1 counter 22 is led to the adder 25 together with the output of the cumulative adder 19 for the X address (n), and the sample of the beam BM _n shown in FIG. 8 is sampled from the adder 25. The distance X _B from the point S ₀ to the center O ₃ of the target pixel P ₃ is output as one of the first basic address signals. This output X _B is XY-R together with the beam deflection angle θ.
It is input to the θ converter 26, and this converter 26
The distance r _B (sin θ · x _B ) from the reference sample point S ₀ to the target sample point S ₃ in the figure is calculated.

The addresses of the high speed buffers 13A to 13N are selected by the following signals. First, a high-speed buffer address selecting cumulative adder 27 for outputting the radius signal r shown in FIG. 8 by cumulatively adding the clock signal CK ₁ from the clock generator 17 and the sampling interval signal Δr, and this cumulative adder An adder 28 for adding the output signal r from 27 and the output signal r _B from the XY-Rθ converter 26 and sending the addition result as one of the first basic address signals is provided. The sampling point S ₃ will be selected based on the output of The sampling interval Δr is set to a fineness of 1 which is several tens of minutes in the related art.

On the other hand, the filter calculator 15 (for example, 15N) outputs the output signal L of the subtractor 23, the output signal X _{B of} the adder 25,
A coefficient determining circuit 15a having three filter characteristics, a filter coefficient determined thereby, and the switch SW
A multiplier (convolution operation unit) 15b that multiplies the data obtained via ₂ and the filter operation is performed on the selected sample point.

Next, the operation of the device configured as described above will be described focusing on the operation of the write address designating means 5.

Since the operation of the interpolation processing unit 4 has been described in the above-mentioned principle description, only the outline operation will be described below.

The controller 30 sends a second basic address signal consisting of an X address selection signal and a Y address selection signal to the vector data generator 31 of the write address designating means 5. At this time, the X address cumulative adder 1 having two systems
The difference between the outputs of 9 and 20 is obtained by the subtractor 23, and 1 is sequentially added to the X address until all the empty pixels within the distance L are filled. Then, each time the X address is determined, the value r _B is obtained by the XY-Rθ converter 26 based on the value X _B obtained by the adder 25 and the angle θ, and this result and the radius r are added by the adder 28. Then, by using the addition result as a high speed buffer address selection signal, the sample data on the same radius as the writing point of the target pixel is read out from several peripheral high speed buffer memories (at least two). Since the positional relationship between the target writing point and the adjacent beam can be known by inputting the values X _B and L, the filter coefficient can be determined by giving the value and the filter characteristic. A convolution operation is performed based on this filter coefficient and data, and this is sent to the frame memory 6 as interpolation processing result data. After that, the operation of obtaining the calculation result data for filling the empty pixels in the horizontal direction sandwiched between the two ultrasonic beams by sequentially adding 1 to the X address is repeated for the distance L, and then the empty pixels in the lower stage in the vertical direction are further added. The calculation result data to be filled is obtained, and these are also sequentially sent to the frame memory 6.

In this way, the data of the entire storage target pixel area on the frame memory 6 can be obtained.

On the other hand, in the write address designating means 5, the vector data generator 31 generates the vector data x _A , y _A of the A block and the basic address generator 32 generates A.
The block address is generated, the coordinate conversion unit 33 converts the address of the A block into other blocks B, C, and D blocks, the bias addition unit 33 adds predetermined bias values α and β, and the address determination unit 34. Area determination processing of the addition processing result is performed.

Now, when the interpolation processing result data to be stored in each pixel of the A block is sent from the interpolation processing unit 4 to the frame memory 6, the write address designating means 5 is controlled by the controller 30 and the address of the A block is addressed. Bias values α ₁ and β ₁ are added to this address by the bias addition unit 33 without conversion processing, and the addition result is sent to the address determination unit 34 as the address of the shaded area A block shown in FIG. 4 (b). It is sent to the frame memory 6 as a write address signal for the A block after area determination is performed. As a result, the interpolation processing result data from the interpolation processing unit 4 to the A block is sequentially written in each pixel of the A block on the frame memory 6.

When the interpolation processing result data is output to the B block from the interpolation processing unit 4 after the writing process to the A block is completed, the coordinate conversion unit 32 is controlled by the controller 30 and the address of the A block is addressed. Address conversion processing to block B is performed. Then, after the bias values α ₁ and β ₁ are added to this address and the area discrimination processing is performed, it is sent to the frame memory 6 as a B block write address signal. As a result, the interpolation processing result data for the B block is sequentially written in each pixel of the B block on the frame memory 6.

Similarly, in synchronization with the timing when the interpolation processing result data for the C and D blocks is sent to the frame memory 6, a write address signal based on the conversion processing corresponding to the C and D blocks is sent from the write address designating means 5 to the frame memory 6. By the above operation, the interpolation processing result data is written in real time to the respective storage target pixels in the entire areas of the A block to D block.

The interpolation processing result data of the radial scan data thus stored in the frame memory 6 is read out in the horizontal direction by the reading circuit 7 controlled by the controller 30 and sent to the TV monitor 8. As a result, a high-quality radial scan image that has been subjected to interpolation processing is displayed on the screen of the TV monitor 8.

Next, a case where a partial display or zoom display of the radial scan image is performed will be described.

In this case, the bias adders 34 add the bias values α ₂ and β ₂ to the respective addresses of the blocks A to D to obtain the address of the circular area shown in FIG. 35, the vector data belonging to the shaded area in the figure is discriminated, and in synchronization with the transmission timing of the interpolation result data, the basic address signal based on the data of the portion belonging to this area and the write inhibition of the portion not belonging to this area And a command is sent to the frame memory 6.

As a result, of the interpolation processing result data, only those belonging to the central portions of the B block and C block and the A block and D block are written to the frame memory 6, and the other portions are not written.

In this way, the bias value in the bias addition unit 34 is arbitrarily set, so that the interpolation processing result data is partially written.

Further, when the partial enlargement display is performed based on the interpolation processing result data, the bias value of the bias addition unit 34 is further changed, and the address determination unit 35 performs the region determination corresponding to the region to be enlarged and the interpolation is performed. A write address signal for changing the write address of the processing result data on the frame memory 6 is sent to the frame memory 6. The same applies to the case where partial reduced display is performed.

The above-mentioned change of the bias value is performed by sending a bias value change signal from the input means 9 to the bias adding section 34 via the controller 30.

The data for partial or zoom display written in the frame memory 6 by the above procedure is read by the reading circuit 7 and displayed as a partial image or a zoom image on the screen of the TV monitor 8.

It is needless to say that the present invention is not limited to the above-described embodiments and various modifications can be made within the scope of the gist thereof.

For example, in the above-described embodiment, the case where the vector data for writing the interpolation processing result data in the frame memory is generated only in the A block obtained by dividing the circular area into four has been described. The vector data may be generated for one block.

〔The invention's effect〕

According to the present invention described in detail above, the write address designating means generates vector data for one block divided into a plurality of circular areas formed by radial scan data and its address, and performs coordinate conversion on the address. Since the write address signal to the storage means is obtained by performing the processing, the bias addition processing and the area discrimination processing, the writing for the partial display and the zoom display of the radial scan image can be performed only by holding a small amount of vector information. An ultrasonic diagnostic apparatus that can perform an operation can be provided.

Further, since the radial scan data is interpolated to the storage target pixel of the storage means and then written into the storage means, an ultrasonic diagnosis capable of obtaining a high-quality image without causing empty pixels A device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of write address designating means in the same device, and FIG. 3 is an explanation showing an area formed by radial scan data on a frame memory. Fig. 4 (a) is an explanatory view showing the coordinates of vector data in the x, y coordinate system of the area shown in Fig. 3, and Figs. 4 (b) and 4 (c) are respectively FIG.
FIG. 5 is an explanatory view showing a state in which bias is added to the area shown in FIG. 5A, FIG. 5 is a circuit diagram showing a configuration of an interpolation processing section, a basic address generating section and a write address designating means in the apparatus of this embodiment, FIGS. FIG. 9 is an explanatory diagram showing the principle of interpolation processing by the interpolation processing unit in the apparatus of this embodiment,
FIG. 10 is an explanatory diagram showing a storage state of conventional radial scan data in a frame memory. DESCRIPTION OF SYMBOLS 1 ... Ultrasonic probe, 2 ... Transmission / reception circuit, 3 ... Control circuit, 4 ... Interpolation processing part, 5 ... Write address designation means, 6 ... Frame memory, 7 ... Read circuit, 8 ... TV monitor, 31 ... Vector data generation part , 32 ... Vector data conversion unit, 33 ... Bias addition unit, 34 ... Address discrimination unit.

Claims (2)

[Claims] 1. An ultrasonic diagnostic apparatus for storing radial scan data obtained by performing a radial scan of an ultrasonic probe in a storage means and displaying a radial scan image based on the radial scan data on a display means. An interpolation processing unit for performing a predetermined interpolation process on the scan data and sending the interpolation result data to the storage unit, and one of the regions obtained by dividing the pixel region on the storage unit for storing the interpolation result data into a plurality of regions. A conversion process for setting data corresponding to the entire area based on vector data indicating the raster direction in the above, addition processing of a predetermined bias value for these vector data, and area determination processing of the addition processing result are performed from the interpolation processing unit. Before being divided in synchronization with the transmission timing of the interpolation result data to the storage means Ultrasonic diagnostic apparatus characterized by comprising a write addressing means the write address signal is determined by a write address signal or the region discrimination processing corresponding to each area is sent to the storage means. 2. The interpolation processing section performs sampling for the radial scan data smaller than one pixel in the storage means, and stores the storage target pixel in a plurality of ultrasonic beams near the storage target pixel in the storage means. All pixels located in the ultrasonic beam are repeatedly processed by performing a filter operation based on the data of sample points at the same distance and storing the operation result in the storage means based on the write address signal from the write address designating means. The ultrasonic diagnostic apparatus according to claim 1, which is configured to store interpolation result data therein.