JPH0642629B2 - Complementary insulation gate type semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a complementary insulated gate (CMOS type) semiconductor circuit.

(Prior Art) As a conventional CMOS type semiconductor circuit, for example, there is a circuit in which two CMOS inverters 51 and 52 are connected in series as shown in FIG. Normally, CMOS type semiconductor circuits have an input level of V
is said to be low power consumption since the through current is not generated when _cc is the power supply potential or V _cc power supply voltage. However, in the transient characteristics at the time of switching of the CMOS inverter, the shoot-through current and the charge / discharge current of the output node transiently flow to become the consumption current. Moreover, when the level of the input voltage V _IN changes gently, the proportion of the through current that transiently flows increases. That is, in CMOS semiconductor circuit shown in the FIG. 5, the voltage V _a of the intermediate nodes when slowly changing input voltage V _IN level (first-stage inverter output _node), the voltage V _out of the output node of the next stage inverter,
The waveforms of the current I _cc of the V _cc power supply and the current I _ss of the I _ss power supply are the sixth.
As shown in the figure. Here, when the threshold value of the N-channel transistor of the CMOS inverter is represented by V _TN and the threshold value of the P-channel transistor is represented by V _TP , the through current continues to flow while the input level is almost between V _cc − | V _TP | Strongly depends on the slope of. Further, the waveform of the output voltage V _out changes gently when the waveform of the input voltage V _IN is gentle. This means that the CMOS of the next stage which receives the output voltage V _out as an input
Also in the semiconductor circuit (not shown), the current consumption increases in the same manner as described above, and as a result, the power consumption of the entire CMOS semiconductor circuit system increases. Then, this power consumption is greatly increased in the circuit which repeats the switching operation.

(Problems to be Solved by the Invention) In the present invention, as described above, the current consumption increases when the input level changes gently, and the output level also changes gently and the current consumption of the next-stage circuit increases. The object of the present invention is to provide a complementary insulated gate semiconductor circuit capable of reducing the current consumption and abruptly changing the output level when the input level changes gently. To do.

[Structure of the Invention] (Means for Solving the Problems) The CMOS semiconductor circuit of the present invention is provided with a CMOS ratioless circuit in the input stage, and the voltage of the output node of this ratioless circuit is set within the power supply voltage range of 2 CMOS with two input inversion voltages
A CMOS type inversion accelerating circuit which is input to a type inverter and is controlled by the voltages of the two output nodes of the inverter to accelerate the output inversion operation of the ratioless circuit. It is characterized by being connected in between.

(Operation) By connecting each circuit as described above, even if the level change of the input voltage is gradual, a direct current path is not generated in each and the output voltage of the ratioless circuit changes sharply.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

In the CMOS type semiconductor circuit shown in FIG. 1, A is a ratioless circuit of the input stage.
An inverter, B is an inversion accelerating circuit for accelerating the output inversion operation of the ratioless circuit A, and C is an input of the output of the ratioless circuit A and has two predetermined input inversion voltages and two outputs. The CMOS inverter of the next stage which becomes the control input of the inversion acceleration circuit B, D is the ratioless circuit A
Is a flip-flop circuit for holding the output voltage of the.

The input stage inverter A includes a first P-channel transistor P and a second P-channel transistor P between the V _cc power supply node and the V _ss power supply node.
₁ , P ₂ and first and second N-channel transistors N
₁ and N ₂ are connected in series, and the gates of a pair of P-channel and N-channel transistors (for example, the first P-channel transistor P ₁ and the second N-channel transistor N ₂ ) are connected to the first input node. 1 and the gates of the remaining pair of transistors P ₂ and N ₁ are connected to the second input node 2. The second P-channel transistor P ₂ and the first N-channel transistor N ₁
An output node 3 is a connection point with.

The inversion accelerating circuit B includes third and fourth P-channel transistors P ₃ , between the V _cc power supply node and the V _ss power supply node.
P ₄ and the third and fourth N-channel transistors N ₃ ,
N ₄ are connected in series, and the gates of a pair of P-channel and N-channel transistors (for example, a third P-channel transistor P ₃ and a fourth N-channel transistor N ₄ ) are connected to the first input node 1. Connected to the
The gates of the remaining pair of transistors P ₄ and N ₃ are connected to the two output nodes 4 and 5 of the next-stage inverter C, respectively.

In the next-stage inverter C, a fifth P-channel transistor P ₅ and a fifth N-channel transistor N ₅ are connected in series between the V _cc power supply node and the V _ss power supply, and both the transistors P ₅ , N are connected. ₅ high-impedance circuit (or device) 6 having a high impedance characteristics than the two transistors are inserted between, the gates of the transistors P _5, N ₅ to the output node 3 of the input stage inverter a It is connected. In the high impedance circuit 6, for example, a sixth P-channel transistor P ₆ and a sixth N-channel transistor N ₆ are connected in parallel, the gate of the sixth P-channel transistor P ₆ is connected to the V _ss power supply node, The gate of the sixth N-channel transistor N ₆ is connected to the V _DD power supply node. The dimensions of the transistors P ₆ and N ₆ are the same as those of the transistors P ₅ and N ₅ .
The gm between nodes 5 and 4 is set to be sufficiently smaller than gm. The drain of the fifth P-channel transistor P ₅ (output node 5) and the drain of the fifth N-channel transistor N ₅ (output node 4) respectively correspond to the gate of the _third N-channel transistor N ₃ . And the gate of the fourth P-channel transistor P ₄ .

The flip-flop circuit D includes a first CMOS inverter 7 having an input terminal connected to the output node 3 of the input stage inverter A, and an output impedance between the output terminal and the input terminal of the first CMOS inverter 7. High second CMOS inverter 8 is connected. This second CMOS inverter 8 is provided with a seventh and a seventh node between the V _cc power supply node and the V _ss power supply node.
Eighth P-channel transistor P ₇ , P ₈ and seventh,
The eighth N-channel transistors N ₇ and N ₈ are connected in series, the gate of the seventh P-channel transistor P ₇ is connected to the V _ss power supply node, and the gate of the eighth N-channel transistor N ₈ is V _cc. Connected to power node, 8th
The gate of the P-channel transistor P _{8 and} the gate of the seventh N-channel transistor N ₇ are commonly connected and serve as an input terminal. The seventh P-channel transistor P ₇ and the eighth N-channel transistor N ₈ are
The conductance is set so small that the output end of the CMOS inverter 8 (that is, the output node 3 of the input stage inverter A) does not enter into a floating state.

Next, the operational characteristics of the above circuits will be described. As shown in FIG. 2, the rising of the first input voltage V _A of the input node 1, the falling period and the second input voltage V _B at the input node 2
If the timing is set so as not to overlap the rising and falling periods, the through current does not flow in the input-stage inverter A even when the changes in the input voltages V _A and V _B are gradual. The next stage inverter C is, V _cc power supply node V _ss and
Since the high impedance circuit 6 is inserted between the power supply node and the power supply node, the through current is suppressed and the operation as shown in FIG. 3 is performed. That is, when the input voltage (the output voltage of the input stage inverter A) V _c rises, the voltage V _{E of the} output node 4 rises from the point when the threshold voltage V _TN of the fifth N-channel transistor N ₅ is exceeded. Further, the voltage V _{D of the} output node 5 falls along with the delay due to the small conductance of the sixth P-channel transistor P ₆ and the sixth N-channel transistor N ₆ . Contrary to the above, when the fall of the input voltage _{V C} is, V _cc - | V _TP |
(V _TP is the threshold voltage of the fifth P-channel transistor P ₅ ), the voltage V _D of the output node 5 falls from the time when it becomes lower, and the sixth P-channel transistor P ₆ and the sixth N-channel transistor N 6 The voltage V _E of the output node 4 falls with a delay of ₆ .

Next, the operation of the CMOS type semiconductor circuit of FIG. 1 will be described. When the input voltages V _A and V _B are both 0 V (in FIG. 2,
During the period from t _{0 to} t ₁ ), the P-channel transistors P ₁ and P _{2 of} the input stage inverter A are both turned on, the voltage V _c of the output node 3 thereof becomes the V _cc potential, and the N of the next stage inverter C becomes N.
The channel transistor N ₅ turns on, its output nodes 4 and 5 both become 0V, the P channel transistors P ₃ and P ₄ of the inversion accelerating circuit B both turn on, and the output voltage V _out of the flip-flop circuit D becomes 0V. _Therefore , in each circuit, a DC current path between the V _cc power supply node and the V _ss power supply node does not occur. Next, when the input voltage _{V B} is the input voltage _{V A} remains 0V rises from 0V to V _cc voltage (second
During the period from t _{1 to} t _{2 in} the figure), in the input stage inverter A, the N-channel transistor N ₁ is turned off by the input voltage V _B , and each circuit is a direct current between the V _cc power supply node and the V _ss power supply node. No current path is created. Next, when the input voltage V _B is 0 V and the input voltage V _A is the V _cc voltage (in FIG. ₂ , t ₂
During a period from t ₃ to t ₃ , the P-channel transistor P ₁ of the input stage inverter A is also turned off and the P-channel transistor P ₃ of the inversion accelerating circuit B is also turned off, but the output voltage V _c of the input stage inverter A is the flip-flop circuit D. Only held by. Next, when the input voltage V _A remains at the V _cc potential and the input voltage V _B rises from 0 V to the V _cc potential (second
During the period from t _{3 to} t _{4 in} the figure), the input voltage V _B is the threshold voltage V _TN of the N-channel transistor N ₁ of the input stage inverter A.
When the voltage exceeds V, the transistor N ₁ is turned on and the output voltage V _c of the input stage inverter A starts to fall. This change in the output voltage V _c is dependent on the change in the input voltage V _B, the falling edge of the variation of the output voltage V _c is when the change in the rise of the input voltage V _B is gentle is very slow, the time , There is no direct current path between the V _cc power supply node and the V _ss power supply node. The output voltage V _c is the next stage inverter C on the high potential side of the input inversion voltage V _cc - | V _TP | becomes lower than, rises the output voltage V _D of the next-stage inverter C. Then, the N-channel transistor N ₃ of the inversion accelerating circuit B is turned on, and the N-channel transistor N ₄ receives the input voltage V
Since it has already been turned on by _A (the V _cc potential at this time), the electric charge of the output node 3 of the input stage inverter A is discharged by the transistors N ₃ and N ₄ . At this time,
The above-mentioned transistors N ₃ and N ₄ enable the next-stage inverter C
Is fed back, and as a result, the voltage V _{c of the} output node 3 is
Will fall rapidly. And this output voltage V
The output voltage V _out of the flip-flop circuit D rapidly changes from 0 V to the V _cc potential by _c . At this time, the voltage V _E of the output node 4 of the next-stage inverter C rises later than the voltage V _D of the output node 5 and the N-channel transistor N ₃ of the inversion accelerating circuit B is turned on, but the P-channel transistor P ₃ is input. Since it has already been turned off by the voltage V _A (at this time, the V _cc potential), no direct current path is generated between the V _cc power supply node and the V _ss power supply node. The input voltage _{V A} remains the input voltage _{V B} of the V _cc voltage from V _cc potential 0
The operation of when changing to V, the input voltage V _A of the above-described input voltage V _B are in the original V _cc potential that is symmetrical to the operation when the rises from 0V to V _cc potential thereof is omitted detail To do.

Here, the middle of _t 3 ~t ₄ period in the above description _{t a}
FIG. 4 shows the voltage waveform of each node of the above circuit and the waveforms of the V _cc power supply currents I _cc and V _ss power supply current I _ss during the period up to t _b . FIG. 4 shows the characteristics when the same load connection as that of the circuit of FIG. 5 of the above-mentioned conventional example is made to the above circuit, and the input voltage V _IN is input in comparison with FIG. 6 described above. The slope of the waveform is the same, and the display section of each time is different. As can be seen from the comparison of FIG. 4 with FIG. 6, the consumption current is about 1/25 times, and the slope (voltage change / time) at the rising and falling of the output voltage V _out is about 15 times. It has become.

The present invention is not limited to the above-described embodiment, but the next-stage inverter C
The P-channel transistor P ₆ and N-channel transistor N _{6 of the} flip-flop circuit D and the P-channel transistor P ₇ and N-channel transistor N ₈ of the flip-flop circuit D can be replaced with resistance elements having equivalent conductances. The flip-flop circuit D may be omitted if necessary.

[Effects of the Invention] As described above, according to the CMOS type semiconductor circuit of the present invention, even when the input voltage level changes gently, the output voltage changes sharply with almost no direct current. Therefore, it is very effective for adoption in LSI circuits, which are expected to consume less power.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a CMOS type semiconductor circuit of the present invention, FIG. 2 is a diagram showing an example of a waveform of an input voltage of the circuit of FIG. 1, and FIG. shows an input voltage of the inverter stages, an example of the waveform of the output voltage, Figure 4 shows a voltage waveform and a power supply current waveform of each node in the circuit of FIG. 1 in t _a ~t _b period of the input voltage of FIG. 2 FIG. 5 is a circuit diagram showing a conventional CMOS type semiconductor circuit, and FIG. 6 is a diagram showing voltage waveforms and power supply current waveforms of respective nodes when the input voltage rises in the circuit of FIG. A: Input stage CMOS inverter, B: Inversion acceleration circuit, C
...... Next stage inverter, P _{1 to} P ₃ ...... P channel transistor, N _{1 to} N ₃ ...... N channel transistor, 1,
2, 3, 4, 5 ... Node, 6 ... High impedance circuit.

Claims (1)

[Claims] 1. A first channel type first transistor serially connected to a first channel type transistor of a CMOS circuit to which an input signal is gate-supplied and serially connected to a second channel type transistor of the CMOS circuit. The second done
A pre-stage CMOS type ratioless circuit having a channel type second transistor, wherein a timing signal whose logical level changes do not temporally overlap with the input signal becomes a gate input of the first and second transistors; A series circuit in which a first channel type third transistor, an impedance, and a second channel type fourth transistor are connected in series in this order between the first power source electrode node and the second power source electrode node is provided. The second CMOS type circuit in which the output of the ratioless circuit is applied to the gates of the third and fourth transistors, and the impedance and the third power supply node are provided between the node which provides the output of the ratioless circuit and the second power supply electrode node. It has a fifth transistor of the second channel type in which the voltage at the connection point with the transistor is applied to the gate. A sixth transistor of a second channel type connected in series with the transistor, the node between the node for providing the output of the ratioless circuit and the first power supply electrode node, and the connection point of the impedance and the fourth transistor. A seventh channel of a first channel type having a voltage applied to the gate thereof, and an eighth transistor of a first channel type connected in series to the seventh transistor. A CMOS type inversion accelerating circuit for accelerating the inversion operation of the ratioless circuit by applying the timing signal to the gate input of the transistor of the first transistor, the second transistor, the sixth transistor, and the eighth transistor, Complementary insulated gate semiconductors characterized in that they are turned off at timings that are not used to determine the output of the ratioless circuit and the inversion accelerating circuit. Road.