JPS6282817A - Logic circuit - Google Patents

Abstract

PURPOSE:To reduce charging/discharging current and to reduce noise disturbance to an analog circuit by selecting a serial resistance value so that the states of (n) logical elements circuits to be subcircuits connected to a main circuit in parallel are successively changed with delays. CONSTITUTION:When the change of an input signal from an inverter 2 is received by an inverter 6, a MOS transistor (TR) 9 is connected and electrostatic charge accumulated in a capacitor 7 starts to be discharged. On the other hand, the output signal from the inverter 2 is supplied to an inverter 4 through a serial resistor 3. The output of the inverter 4 is changed by a time delay determined by the resistance value of the serial resistor 3 and the input capacity of the inverter 4 to discharge the charge accumulated in the capacitor 5. When respective load current values of TRs 8, 9 are selected as a half of the capacity of an output buffer TR, the capacity of an input data becomes also a half, the ON resistance value of the inverters 4, 6 become about twice and the discharge peak current values of the capacitors 5, 7 become about a half. If the discharge is slightly shifted by inserting the serial resistor 3, noise due to discharge can be reduced to about a half.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, and particularly to logic circuits used in MO8 integrated circuits in which analog circuits and digital circuits coexist.

[Conventional technology]

Conventionally, MO8 has a mix of analog and digital circuits.
As for the logic circuit used in the 8M circuit, similarly to the MO8 integrated circuit composed only of digital circuits, the drive capability of the preceding stage logic circuit is determined from the input gate capacitance of the buffer circuit or the like serving as the load.

FIG. 3 is an equivalent circuit diagram of a configuration example of a conventional logic circuit. In the third factor, 33 is an n-channel MOS transistor constituting an open dofin output buffer circuit;
Reference numerals 30 and 31 designate an inverter that fully drives these, and 32 a capacitor equivalent to the sum of the parasitic capacitance of the inverter 31 and the input gate capacitance of the MOS transistor 33.

In the circuit shown in FIG. 3, the capacitance value of the capacitor 32 is set to 01, and the on-resistance when the MOS transistor on the ground potential side constituting the inverter 31 is turned on, and the charge of the capacitor 32 is discharged via the on-resistance of the star. think about it. If the potential of the capacitor 32 at time t is V (t), then V(tl=Vcexp(-t/CR) ・-・-・
・------・(1) holds true. Let the current flowing through the MOS transistor on the ground/potential side of the inverter 31 at time t be 1 ft), and the charge tQ of the capacitor 32 (t
), then I (tl = dQ(tl/d t :
-V(t)/R......(2). From this, the current at time 1=0 is I (o)
= Vc/Rtft, grounding position 1t411 (
7) MOS) It can be seen that the smaller the on-resistance R of the transistor, the larger the current. On the other hand, (1)
From the formula, the rate of change of the potential V (t) of the capacitor 32 is C
It can be seen that it depends on the product of R, and that when C is large, the capacity must be made small.

[Problem that the invention seeks to solve]

That is, in the conventional circuit shown in FIG. 3 described above, the output M
If the input gate current of the OS transistor 33 is wide, the input gate capacitance will also be large.
It is necessary to reduce the on-resistance of the inverter 31, which results in an increase in the discharge current from the capacitor 32 to the ground potential.

In an integrated circuit in which analog circuits and digital circuits coexist, there is a problem that this radiation current deteriorates the characteristics of the analog circuit through a common resistance component to the ground terminal. In particular, when noise due to the above-mentioned pulsed discharge current is introduced at the boundary point when the sampling period changes to the hold period in the sample/hold circuit, etc.
The hold value fluctuates widely, which directly leads to deterioration of sample-and-hold circuit characteristics. This further characteristic deterioration is t%.
This is caused not only by the charging current from the power supply, but also by the charging current from the power source.

The purpose of the present invention is to reduce the amount of light emitted by i
It is an object of the present invention to provide a logic circuit that reduces mx flow and causes less noise interference to analog circuits.

[Means to solve the problem]

The logic circuit of the present invention is a logic circuit of a semiconductor integrated circuit in which analog circuits and digital circuits coexist. and N (an integer of N≧1) subcircuits connected in parallel with the main circuit and having the same configuration as the main circuit and a series resistor inserted into the input of the logic element circuit, and the logic element circuit of each of the subcircuits. The resistance value of the series resistor of each of the sub-circuits is selected such that the state of the sub-circuit changes sequentially later than the state of the logic element circuit of the main circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention.

In FIG. 1, 1 is the main circuit, la is the sub circuit, 2°4.
6 is an inverter, 3 is a series resistor, 8 and 9 are MOS transistors serving as the 9 loads of the inverters 4 and 6, and their outputs are wired OR connected. Capacitor 5, 7
is the sum of the parasitic capacitance of the inverters 4 and 5 and the gate capacitance of the MOS transistors 8 and 9, each expressed by one equivalent capacitor for the sake of explanation. Below, complementary MO
8) Taking the transistor circuit 2 as an example, the series resistor 3 is connected to the transmission gate (the source and drain of the n-channel transistor are connected to each other, the gate electrode of the n-channel transistor is connected to the ground potential, and the gate electrode of the n-channel transistor is connected to the ground potential). What if the terminals are connected to the power supply respectively)? explain.

Of course, the series resistor 3 may be constructed using polysilicon or a diffused resistor instead of a transmission gate.

The circuit of FIG. 1 operates as follows. When the input IN of the inverter 20 that starts the logic circuit of the present invention changes from H level to L level, the output of the inverter 2 changes from L level to H level. In response to the change in the output signal of the inverter 2, the ground 9111M081 register of the inverter 6 becomes conductive, and the charge stored in the capacitor 7 starts to be released.

The output of the inverter 6 changes from H level to L level.

Since the output signal of the inverter 2 is supplied to the inverter 4 through the series resistor 3 using a transmission gate, the input of the inverter 4 is delayed by a time determined by the resistance value of the series resistor 3 and the input capacitance of the inverter 4. Change. In response to this delayed signal, the output of inverter 4 changes from H level to L level.
level, and the charge stored in the capacitor 5 is discharged. If the load current of MOS transistors 8 and 9 is selected to be half of that of MOS transistor 330 shown in FIG.
The on-resistance of capacitor 5,
The discharge peak current of No. 7 is approximately. Furthermore, by inserting the series resistor 3, the time is slightly shifted and the inverter 6 first releases 1! and then release 1 with inverter 4! Since this is done naturally, the noise associated with the discharge can be reduced by about half.

FIG. 2 is an equivalent circuit diagram of a second embodiment of the present invention, which is composed of a main circuit 10 and three subcircuits 10a and operates in substantially the same manner as the first embodiment. In Figure 2, 12, 16.2
0 is p-channel MO8) transistor, 13, 17.2
1 is an n-channel MOS transistor, and one p-channel and one n-channel constitute a transmission gate'. The resistance value of each transmission gate is selected so as to obtain the desired delay time, and the resistance value of each transmission gate is selected to obtain the desired delay time.
and 17. It is assumed that the transmission gates formed by the pairs 12 and 13 are selected such that the resistance values increase in the order of the transmission gates. First, when the input IN of the inverter 11 that starts up the logic circuit of the present invention changes from H level to L level, the output of the inverter 11 changes from L level to H level.

Inverter 2 receives a change in the output signal of inverter 11.
4 changes from H level to L level, and the charge stored in capacitor 25 begins to discharge. Next, the MOS
) A signal delayed through a transmission gate formed by transistors 20 and 21 changes the output signal of inverter 22 from H level to L level, and the charge stored in capacitor 23 begins to be discharged. Inverters 18 and 14 each output a high signal after a delay time equal to the resistance value of the transmission gate.
The level changes from the level to the L level, and the charges stored in the capacitors 19 and 15 are discharged. As explained above, the circuit of the embodiment shown in FIG. 2 is composed of four rows of parallel circuits, and in each circuit, the n-channel MOS transistors on the ground side of each inverter are turned on in the order of inverters 24, 22°19.14. The current noise can be reduced to about K.

Note that the present invention is not limited to any number as long as there are two or more sets of logic circuits connected in parallel. Furthermore, although the embodiment has been explained using a complementary MOS transistor circuit, NM
O8) Even if applied to a transistor circuit or a PMOS transistor circuit, it operates in the same way and has the same effect. Furthermore, in the above-described embodiment, the front-stage circuit that drives the output buffer circuit is impark, but the technical idea of the present invention applies even if it is a logic circuit other than an inverter (for example, a two-person AND circuit). Applicable.

〔Effect of the invention〕

In this system, logic element circuits each having a series resistor inserted into the input are connected in parallel according to a capacitive load such as an input, and the output of each logic element circuit connected in parallel is sequentially delayed and changed. Therefore, since a logic circuit with less current noise can be provided, an MO8 integrated circuit having a mixture of analog circuits and digital circuits with less characteristic deterioration can be realized.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a first embodiment of the logic circuit of the present invention, FIG. 2 is an equivalent circuit diagram of the second embodiment, and FIG. 3 is an equivalent circuit diagram of a conventional circuit. l, 10... Main circuit, la, 10a...
・Sub circuit, 2.4, 6, 11, 14, 18, 22, 24
,30.31... Inverter, 3...
・Series resistance, 5, 7, 15, 19, 23°25.32・
...Capacitor, 8, 9, 26, 27゜28.2
9.33...n-channel MOS transistor. ,()1, Representative Patent Attorney Susumu Uchihara (g,, ,',
'$ 2 Funamine 3 Ga

Claims (1)

[Claims] In a logic circuit of a semiconductor integrated circuit in which analog circuits and digital circuits coexist, there is a main circuit consisting of an output buffer transistor and a logic element circuit that drives the output buffer transistor, and a main circuit connected in parallel with this main circuit. It is composed of N sub-circuits (an integer of N≧1) having the same configuration as the logic element circuit and a series resistor inserted into the input of the logic element circuit, and the state of the logic element circuit of each of the sub-circuits is the same as that of the main circuit. A logic circuit characterized in that the resistance value of the series resistor of each of the sub-circuits is selected so as to change sequentially with a delay from the state of the logic element circuit.